ECE 103 Digital Electronics Lab Spring 2025
Department of Electrical Engineering Document Number: Version: 2.0
SNU/MAN/EHS/EL/003 Effective Date: 13/01/2025
Title: Digital Electronics Lab Manuals (ECE 103) Pages 2
Instructors: Prof. Sonal Singhal
Dr. Rakesh Palisetty
Experiment 2 Combinational Circuits for Binary Arithmetic
We will use various kinds of CMOS gates as required for the implementation of the logic. The pin
connections of all the ICs are the same as given in the write-up for Experiment 1. Remember that
for all experiments, the VDD/VCC and Gnd pins of each IC chip used must be connected to the VDC
and Gnd buses on the breadboard, using RED and BLACK wires respectively. As done in
Experiment 1, the top horizontal strip of the breadboard will be connected to the VDC bus, and
similarly the bottom horizontal strip of the breadboard will always be connected to the Gnd bus.
Connections to these buses will always be made by RED and BLACK banana wires respectively to
the d-c power supply. As in Experiment 1, the inputs will be applied through wires connected to VDC
/ Gnd, and the outputs will be checked by LEDs provided on the breadboard.
You will use the following ICs for different parts of this experiment, as given below:
Part A – 74HC00, 74HC08 and 74HC32.
Parts B and C – CD4070/HEF4070 and 74HC08.
You will first get the breadboard with the set of ICs to be used for Part A, and after completing
Part A, you will have to get the ICs changed by taking the breadboard to the Lab in-charge.
Part A. De Morgan’s Laws
De Morgan’s laws state that (A + B)’ = A’ • B’ and (A • B)’ = A’ + B’. Verify these laws by
proceeding step by step as follows:
A B (A + B)’ A’ • B’ (A • B)’ A’ + B’
0 0
0 1
1 0
1 1
1. Set up a circuit consisting of two Inverters, obtained by shorting together the inputs of a two-
input NAND gate from a 74HC00 Quad NAND IC, and one AND gate out of a 74HC08 Quad
AND IC to perform the function Y = A’ • B’. Draw the complete circuit diagram in your Lab
Notebook, marking all the IC pin numbers on the diagram.
2. Apply the four possible combinations of (binary) values to the inputs A and B through wires
connected to VDC / Gnd and tabulate the corresponding values of the output Y as observed
on the LED. Verify that the truth table so obtained is the same as that of a NOR gate.
3. Proceed in a similar manner, using two inverters and an OR gate out of a 74HC32 Quad OR
IC instead of an AND gate, to verify that the truth table of the function Y = A’ + B’ is the
same as that of a NAND gate.
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ECE 103 Digital Electronics Lab Spring 2025
Part B. Binary Half Adder using Gates
A binary Half Adder adds two bits A and B to generate SUM and CARRY bits as output according
to the following Boolean expressions for the outputs:
SUM = A’ • B + A • B’ = A B and CARRY = A • B.
1. Set up the circuit of a Half Adder using an XOR gate out of the CD4070 IC and an AND gate
out of the 74HC08 IC. Apply the inputs A and B through wires and observe the outputs SUM
and CARRY on the two LEDs provided on the breadboard for all combinations of the inputs.
2. Tabulate these values and verify the operation of the Half Adder. DO NOT dismantle this
circuit as it will be used as part of the circuit to be used in the next Part.
Part C. Binary Full Adder using Two Half Adders and Gates
A binary Full Adder adds two bits A and B along with a carry-in bit C to generate SUM and CARRY
bits as output. It can be implemented with two Half Adders and one AND gate. In this
implementation, one Half Adder is used to add the bits A and B to generate intermediate sum and
carry bits S1 (= A B) and C1 (= A • B). Another Half Adder is then used to generate the final
SUM by adding the carry-in bit C to the S1 bit generated by the first Half Adder:
SUM = S1 C.
The carry bit C2 (= S1 • C) generated by this Half Adder is combined with C1 to generate the final
CARRY output given by the expression:
CARRY = C1 + C2.
1. Set up another Half Adder using another XOR and another AND gate out of the same ICs
used in step B.1 and connect the C input and the S1 output generated by the first Half Adder
as its inputs to generate the final SUM output and the C2 output.
2. Note that the logic for CARRY can also be implemented with an XOR gate (i.e. CARRY = C1
C2 because C1 and C2 can never be equal to ‘1’ together), thereby eliminating the need for
a separate OR chip and making the complete realization of the Full Adder possible using two
IC chips. Generate the final CARRY output from the intermediate carry outputs C1 and C2,
using one of the unused gates in the XOR chip.
3. Complete the truth table shown below experimentally by applying all combinations of the
inputs A, B and C through wires and noting the S1, C1, C2, SUM and CARRY outputs on the
LEDs, observing two variables at a time. Verify that the table does correspond to the logic of
a Full Adder.
A B C C1 S1 C2 CARRY SUM
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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