CHAPTER ONE: INTRODUCTION

1.0 INTRODUCTION

The development of science and technology has affected in one way

uor the other the activities of human beings in all field of their endeavours.

Indeed, in his search for security man has developed several

techniques. In trying to achieve security locks, several methods were used

and new methods are also being developed. This has permitted the

implementation of both electromechanical and electronic security locks.

The ancient Egyptians have since used security locks to protect their

belongings. The Egyptian security lock had a wooden bolt with holes in it.

When it was locked, wooden pegs fell into the hole. The turning of a key

raised the pegs and allows the bolt to be withdrawn. The warded lock made

by the ancient Romans has a number of barriers that the key must pass

through before it unlocks the lock. The level trumbler lock on the other hand

has levers that must be raised to a certain height before it unlocks. All these

mechanical locks are easy to unlock.

1
 The advancement in electronic technology, especially in security and

lock technology leads to the replacement of most equipment with electronic

systems.

Electronic security lock system has been able to provide security at

low cost and among them is the micro controller based sliding door.

1.1 AIMS OF THE PROJECT

Most mechanical security locks are unreliable, inaccurate and offer

low level of security. As a result of these, new technologies are answerable

to these performance set-backs (problems) related to mechanical safe locks.

These new and more reliable modules are conceived and implemented.

The project is based on the design and construction of a

microcontroller based sliding door system used to lock and unlock a safe,

but its use can be extended to other locking systems such as; doors etc.

1.2 STATEMENT OF THE PROBLEM

The high level of burglary and insecurity in the society, makes the

mechanical locking system becomes easy to disengage by criminals.

Therefore a safer and more reliable security lock must be developed.

1.3 OBJECTIVES

2
 This work will make or bring the issue of burglary and insecurity to a

minimum level not only that, the programmable sliding door will make the

user forget the issue of losing keys or carrying keys around.

1.4 JUSTIFICATION OF THE WORK

The justification of this project lies on three basic facts:

1. The use of 6-digit programmable combination to offer more security

as compared with 4 and 2 digits lock earlier in use.

2. Use of a fully microcontroller based sliding door system as compared

with analog lock versions to achieve increased speed of operation and

enhance the system performance.

3. The relatively low cost of components involved in the project.

4. use of touch activated alarm to avoid burgling as well as wrong code

alarm to avoid hacking

1.5THESIS OUTLINE

3
 This study comprises of five different chapters arranged sequentially.

Chapter one gives a brief history of the various forms of locks and

their technological advancements.

Chapter two explains the operating principles of the various stages

involved in the digital combination lock using microcontroller.

In chapter three, the design and implementation of the whole project

work is discussed fully.

Chapter four presents the results and discussions drawn from tests

performed on the system, while the last chapter gives a conclusion and

recommendation on the entire work.

4
 CHAPTER TWO: THEORETICAL BACKGROUND

2.1 INTRODUCTION

In this chapter, an attempt is made to give a detailed review of the

microcontroller based sliding door as regards to the system’s sub-units. The

relationship between the various units was expressed as an aid to the

understanding of the system’s operation.

2.1SYSTEM BLOCK DIAGRAM

Fig. 2.0 Block Diagram

5
2.2 POWER SUPPLY UNIT

The power supply unit is the unit that energizes all other units of the

sliding door system at a steady voltage.

Functionally, the power supply converts A.C voltage of 50 Hz power

line to D.C voltage. In this design, 12V and 5V D.C voltage levels are

required for all the system units. The process for the conversion of A.C

supply to D.C is termed “rectification” which has the following components:

1. Step-down transformer.

2. Rectifier.

3. Filter.

4. Voltage Regulator.

2.2.1 Step-Down Transformer

The transformer is a device used in transforming electric power in one

circuit into electric power of the same frequency but different voltage in
another circuit but with a corresponding decrease or increase in current.
The transformation is based on the mutual induction between the two
circuits linked by a common magnetic flux. In its simplest form, it consists
of two inductive coils which are electrically separated but magnetically link
through a path of low reluctance.

6
 T1
10TO1

V1 N1 N2 V2

Figure 2.1; Step-down Transformer

If one coil is connected to a ac voltage source, an alternating flux is set
up in the laminated core, most of which is linked with the other coil in which
it produces mutually induced e.m.f. (according to the faraday’s law of

electromagnetic induction e=M ). If the second coil is closed, a current

flow in it and so electric energy is transferred. In this design a 240VA.C is

stepped down to 15VA.C which is then rectified and regulated to 12V and
5V D.C respectively.

2.2.2 Rectifier

A full wave bridge rectifier is used to achieve the conversion of the

15V A.C to D.C. as shown in the figure below:

7
 Terminal 1
240/15V D4 D1

D3 D2
Terminal 2

+
C1

Fig. 2.2: Full-wave Bridge Rectifier.

When terminal 1 is positive with respect to 2, diodes D1 and D3

conduct. When terminal 2 is positive with respect to 1, diodes D2 and D4

would conduct, thereby giving a pulsating D.C output as shown below:

Fig. 2.3: Rectifier Output

2.2.3 Filter

The function of the filter is to smooth the pulsations present in the

output voltage supplied by the rectifier. In practice, no filter gives output

voltage that is as ripple-free as that of a battery, but it considerably reduces

the ripple to certain extent. A capacitor is used to achieve the filtering as

Shown in Fig. 2.4:

8
 Fig. 2.4: Rectified and Filtered Output

(2.0)

Equation (i) refers to the relationship between the filter capacitor and

other supply parameters.

Where,

Expected DC output from the

regulator

Supply frequency

= Output current of regulator

Transformer Secondary Voltage

Capacitance of the filter capacitor

2.2.4 Voltage Regulator

9
 In order to keep the terminal voltage of the DC supply constant, a

voltage regulator was used. The regulators used were 7812 and 7805 since

12V and 5V respectively are needed for the system operation. It maintains a

constant DC supply even when there is a variation of the AC input from the

transformer and when the load varies.

D1
240/15V BRIDGE
50Hz
78L12
IN OUT

COM

78L05
+

C1 IN OUT

COM

Fig. 2.5 Overall Power Supply Circuit

2.3 THE CONTROL UNIT

The control unit consists of the microcontroller pic 16f84A chip. The

PIC16F84A belongs to the mid-range family of the PIC micro®

microcontroller devices. A pin diagram and block diagram of the device is

shown in Figure 2.6.

10
 Fig 2.6 Pin Diagram of PIC16f84A

OSC1/CLKIN : Oscillator crystal input.

External clock source input.
OSC2/CLKOUT : Oscillator crystal output.
Connects to crystal or resonator in crystal oscillator mode.
MCLR(inv) : Master clear(reset)input.
Programming voltage input.
This pin is an active low reset to the device.
RA0 - RA3 : Bi-directional I/O port.
RA4/T0CKI : Bi-directional I/O port.
Clock input to the TMR0 timer/counter.
RB0/INT : Bi-directional I/O port.
External interrupt pin.
RB1 - RB7 : Bi-directional I/O port.
VSS : Ground
VDD : Positive supply(+2.0V to +5.5V)

11
Fig 2.7 PIC16F84A Block Diagram

2.3.1 Flash Program Memory

Flash memory is used to store the program. One word is 14 bits long

and 1024 words (1kbyte words ) can be stored. Even if power is switched off

the contents of the flash memory will not be lost. Flash memory can be

12
written to address using the writer, but the number of times it be rewritten is

limited to 1000 times.

The usage of some program memory addresses is already decided.

Fig. 2.8: Flash Program memory

Reset Vector ( 0000h )

When a reset is executed, either by turning power on, by the WDT

(Watchdog Timer) or any other factor, the program will start from this

address.

Peripheral Interrupt Vector ( 0004h )

When there is a time-out interruption from the timer (TMR0) or an outside

interrupt, the program will start from this address.

Configuration word ( 2007h )

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The basic operation of the PIC is specified at this memory location. The

enable bits of the Power-up timer, and the Watch-dog timer as well as the

oscillator selection bits are set here. This area is behind the usual program

area and can not be accessed by the program. These parameters must be

specified using the burner when burning the program into flash memory.

RAM (Random Access Memory) File Registers. Bank switching is used to

access this memory. Each bank has a memory capacity of 80 bytes (00h-

4Fh). The PIC16F84A has two banks. This memory is divided into two

sections. The first 12 bytes (00h-0Bh) of each bank are called SFR (Special

Function Registers) and are used to record the operating states of the PIC,

the input/output (I/O) port conditions and other conditions. There are 16

different registers in the SFR (11 in bank 0 and 5 in bank1). The content of

each register is managed by the PIC. Although there are a total of 24 file

registers, several of them are in both banks. The remaining 68 bytes (0Ch-

4Fh), from byte 13 upward, are called GPR (General Purpose Registers) and

can be used to temporally store results and conditions while the program is

running. The contents of the GPR are the same in both banks, so even with

bank switching the total capacity is only 68 bytes. The contents of the GPR

are lost when the power is switched off. There is no limit to the number of

times data can be rewritten.

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2.3.2 EEPROM (Electrically Erasable Programmable Read Only

Memory)

This is nonvolatile memory, the contents is not lost when power is

turned off. The memory contents can be rewritten by the program. The total

capacity is 64 bytes, and the number of times it can be rewritten to is limited

to about one million. For this reason it is not recommended for temporary

data storage. It is used to store data which will not change frequently.

Data can be safely stored for 40 years.

2.3.3 SFR Registers

16 different SFR (Special Function Registers) can be specified by the

bank switching technique. Fig. 2.9 shows the RAM File Registers. The

memory capacity is only 160 bytes. The contents of the registers with the

left pointing arrow are the same on both banks. The other registers of the

SFR are accessible through bank switching, and the gray colored registers

are not used.

15
 Fig. 2.9: SFR Register

Each SFR has the following function.

INDF : Data memory contents by indirect

addressing
TMR0 : Timer counter
PCL : Low order 8 bits of program counter
STATUS : Flag of calculation result
FSR : Indirect data memory address pointer
PORTA : PORTA DATA I/O
PORTB : PORTB DATA I/O
EEDATA : Data for EEPROM
EEADR : Address for EEPROM
PCLATH : Write buffer for upper 5 bits of the
program counter
INTCON : Interruption control
OPTIN_REG : Mode set
TRISA : Mode set for PORTA
TRISB : Mode set for PORTB
EECON1 : Control Register for EEPROM
EECON2 : Write protection Register for EEPROM

16
2.3.4 Program Counter

This counter contains the address of the next instruction (fetch

address) to be read from the program memory (flash memory). It is a 13 bit

counter. Generally the count increments each time an instruction are

executed, and the location of the following instruction is shown in the PC.

But when a jump is executed the contents of this counter is rewritten to that

of the jump address.

2.3.4 8 Level Stacks

The stack stores the program return address when a jump is executed.

For example if the same instructions are to be executed more than once, a

subroutine is used. A RETURN instruction signifies the end of the

subroutine and the program continues were it left off. A CALL instruction

tells the program to jump to a subroutine. When the CALL instruction is

encountered, the return address (the address of the instruction immediately

after the CALL) is stored at the top of the stack. This operation is sometimes

called a PUSH. When the subroutine processing is finished and the

RETURN instruction is executed, the address at the top of the stack is put in

the PC and the program continues normal execution. This operation is

sometimes called a POP. This way multiple subroutines can be called and

17
the processing will return to the part of the program which called the

subroutine. Since there are eight stack registers, eight subroutine calls can be

made sequentially. After the eighth, a call will roll the contents of the eighth

(and last register) back to the top of the stack. When a return is executed, the

PC will send the program to the wrong address, and the program will not

work properly. For this reason only eight sequential subroutines calls can be

made.

A return from a subroutine call must be done by the RETURN instruction.

Never use the JUMP instruction to return from a subroutine.

Fig.2.10: 8 Level Stacks.

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2.3.5 Instruction Register

The instruction at the address specified by the PC is read to this

register. This operation is called a FETCH

Instruction Decode & Control The instruction in the Instruction Register is

analyzed here, and (according to its contents) the operation is performed

Multiplexer and Arithmetic Logic Unit. The calculations are performed by

the Multiplexer and Arithmetic Logic Unit (ALU).Without these two it

would not be a computer

2.3.6 W Register

This is the working register. It is used to temporarily store the contents

of the ALU. It is indispensable for calculation operations. The contents of

this register can be transferred to the various registers to be utilized by the

program. It is also used to control the I/O ports.

2.3.7 STATUS Register

This Register stores the result of the ALU (Zero, positive or negative),

a time-out condition, register bank select etc

2.3.8 FSR Register

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 FSR (File Select Register) is used to specify the address of the RAM file

register when using the indirect addressing method. In the direct address

method the register address is specified by the program instructions. In this

case a 7 bit address, from 0 to 127, can be specified. This range is for one

bank. To change the bank, the RP0 bit of the status register must also be

specified. Since the FSR is 8 bits, it is possible to specify the address and

bank at the same time, saving instruction cycles. In the PIC16F84A memory

locations 80 (50h) to 127 (7Fh) are not installed. When using the FSR it is

convenient to make the file register data area continuous. Incrementing the

FSR simplifies processing during read and write operations

2.3.9 Address Multiplexer

This distinguishes between the direct and the indirect addressing.

2.3.10 EEDATA

This register is used when reading from, or writing data to the

EEPROM.

2.3.11 EEADR

This register specifies the EEPROM address. Since it is composed of

eight bits addresses from 0 to 255 can be specified. The PIC16F84A has

only 64 bytes of memory installed. The address of EEPROM is started from

20
2100h.

When writing data during program execution it is necessary to sequentially

write 55h then AAh to the EECON2 register

2.3.12 Timer

The PIC16F84A has only one timer (TMR0, an 8 bit timer). It times out

when the count reaches 256 and the TOIF bit of the INCON register of the

SFR becomes "1". With a timed out condition it is possible to make an

interrupt occur. The interrupt will stop the processing which was in progress

at that time. To make the interrupt occur the GIF and the TOIE bits of the

INTCON register of the SFR must be set (1)

2.3.13 I/O Ports

There are 13 I/O pins, with individual direction controls. The mode

(input or output) of each pin can be set from within the program. The 13 pins

are divided into two groups. The A Port has five pins and the B Port has

eight. There is a limitation on control timing, but each of the 13 pins can be

individually controlled.

Timing Generation

21
This circuit generates the clock pulses which determine the speed of

operation. Oscillator operation is determined by external capacitors and a

crystal (or ceramic) oscillator. If high stability is desired a crystal or ceramic

resonator is used. Generally the circuitry is simpler with the resonator, which

incorporates the ceramic and capacitors in one module. An external clock

can also be [Link] PIC16F84A executes one instruction (one cycle) every

four clock pulses, using pipeline architecture. But when a JUMP is executed

two cycles are necessary (8 clock pulses). With a 20MHz clock the

execution time of an instruction is 200ns. (The pulse period of 20MHz is

50ns (1 / 20MHz = 50ns), so 50ns x 4 cycles = 200ns). 5,000,000

instructions can be executed in one second. (2,000,000 / 4 = 500,000)

2.3.14 Initialization circuits

The PIC16F84A has various initialization circuits.

POW ON : When power is turned on this timer inhibits operation until

Timer the voltage is stable.
OSC Start : When power is turned on this timer inhibits operation until
Timer the clock is stable.
POW ON : When power is turned on this timer initializes the inner
Reset circuitry of the PIC.
Watchdog : This timer watches over the normal operation of the PIC
Timer
software. It must be regularly cleared by software. When it

times out the PIC returns to the point in the program

22
 immediately after power on. This timer is used to recover

program operation when the software has a defect (or bug).

Even if the program is reinitialized the bug is still in the

program.

2.4 SWITCHING UNIT

This unit consists of a transistors (BC109) operating as a switch,

relays and a DC motor.

2.4.1 Transistor

This is a three terminal, three layer device formed by adding a second

p or n region to a p-n junction diode. With two n-regions and one p-region,

two junctions are formed and it is known as an NPN transistor. The common

emitter configuration for an NPN transistor is generally used in switching

applications and it is shown below;

NPN

Fig. 2.8: NPN transistor

2.4.2 Relay

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 This is an electromagnetic switch having an electromagnetic coil with

a specified inductance that causes a contact to open or close when a

specified current flows through it. The contact remains in the same position

until the current falls below the holding value at which point the contact

returns to its initial position. The schematic representation of a relay is

shown below;

CONTACT

COIL

Fig. 2.9: Relay Symbol

2.4.3 DC Motor

This is a machine that converts electric energy into mechanical energy.

Its action is based on the principle that when a current-carrying conductor is

placed in a magnetic field, it experiences a mechanical force whose direction

is given by Fleming’s Left-Hand Rule and whose magnitude is given by;

(2.1)

Where, Mechanical force in Newton (N)

Magnetic field in Weber (Wb)

Current through the conductor in Amperes (A)

Length of Conductor in meters (m)

24
 The schematic representation of a DC motor is shown below;

Fig. 2.10: DC Motor symbol.

Based on the above principle, a change in the direction of current flow

reverses the direction of rotation. Thus, the motor was connected in the

switching unit to lock and unlock the safe when its supply current is

switched in different directions.

2.5 KEYPAD

This unit comprises of thirteen Normally Open (NO), Single-Pole-

Single-Throw (SPST) push-button switches. They were connected to achieve

the desired input combination and also to close the system.

2.6 TOUCH ACTIVATED ALARM

This is basically a pulse generator circuit that produces a one shot

pulse for some duration T which is use to switch a relay that supplies the

power to the alarm. A 555 timer in the mono stable mode has this capability.

The 555 timer IC is a highly stable controller capable of producing accurate

25
time delays, or oscillation. For operation as a one shot (mono stable mode),

the frequency is accurately controlled with external resistor and a capacitor

connected on the threshold and discharge pins. It allows the setting up of

accurate time delays from several micro-seconds to hours, and generates

pulse. The 555 timer configuration is shown below:

Fig. 2.11: 555 Timer pin configuration.

2.7 ALARM UNIT

The alarm is also 555 timer in astable mode used as atone generator. A
555 timer connected to operate as an astable multivibrator which is free
running non-sinusoidal oscillator is shown in figure 2.3 below

26
 Vcc

R1
4 8

R2 3
6
5
2 0.01µF
1 (Decoupling Optional)
C1

Figure 2.12 Astable MultiVibrator

From the figure above, the threshold input is connected to the trigger
input. The external components R1, R2 and C1 form the timing network that
sets the frequency of oscillation. The 0.01µf capacitor C 2 connected to the
control input is strictly for decoupling and has no effect on the operation, so,
in some cases it can be left off.

2.8 THE CLOSING BUTTON

This is basically a pulse generator circuit that produces a one shot

pulse for some duration T (about 1 minute) which is use to switch a relay

that supply the power to the motor. A 555 timer in the mono stable mode has

this capability. The 555 timer IC is a highly stable controller capable of

producing accurate time delays, or oscillation. For operations as a one shot

27
(mono stable mode), the frequency is accurately controlled with external

resistor and a capacitor connected on the threshold and discharge pins. It

allows the setting up of accurate time delays from several micro-seconds to

hours, and generates pulse over a wide range of frequency. The 555 is shown

here in its utmost basic mode of operation; as a triggered monostable. One

immediate observation is the extreme simplicity of this circuit. Only two

components to make up a timer, a capacitor and a resistor. And for noise

immunity maybe a capacitor on pin 5. Due to the internal latching

mechanism of the 555, the timers will always time-out once triggered,

regardless of any subsequent noise (such as bounce) on the input trigger (pin

2). This is a great asset in interfacing the 555 with noisy sources. Just in case

you don't know what 'bounce' is: bounce is a type of fast, short term noise

caused by a switch, relay, etc. and then picked up by the input pin.

The trigger input is initially high (about 1/3 of +V). When a negative-going

trigger pulse is applied to the trigger input, the threshold on the lower

comparator is exceeded. The lower comparator, therefore, sets the flip-flop.

That causes T1 to cut off, acting as an open circuit. The setting of the flip-

flop also causes a positive-going output level which is the beginning of the

output timing pulse.

28
The capacitor now begins to charge through the external resistor. As soon as

the charge on the capacitor equal 2/3 of the supply voltage, the upper

comparator triggers and resets the control flip-flop. That terminates the

output pulse which switches back to zero. At this time, T 1 again conducts

thereby discharging the capacitor. If a negative-going pulse is applied to the

reset input while the output pulse is high, it will be terminated immediately

as that pulse will reset the flip-flop.

Whenever a trigger pulse is applied to the input, the 555 will

generate its single-duration output pulse. Depending upon the values of

external resistance and capacitance used, the output timing pulse may be

adjusted from approximately one millisecond to as high as on hundred

seconds. In this application, the duration of the output pulse in seconds is

approximately equal to:

T = 1.1 x R x C (in seconds)

29
 CHAPTER THREE: DESIGN AND IMPLEMENTATION

3.1 INTRODUCTION

The design and implementation of each of the fundamental circuit units

and how the program was implemented to control the design and perform

the required functionality is presented in this chapter.

3.2 POWER SUPPLY

This unit comprises of the transformer, diode rectifier, filtering capacitor,

switching relay, back-up battery and regulators.

3.2.1 Transformer

The local main is expected to deliver 240V, the system voltage

requirement is 12V and 5V, therefore a 240V/15V transformer was used.

The system input resistance is about 200Ω, therefore the expected load

current is

I = V/R = 5/200 = 250 mA

A transformer with the current rating of 500mA which is greater than load

current was used. Thus the power rating of the transformer was completed to

be

S = VI = 12 X 500 mA = 6VA

30
3.2.2 Rectifier

The voltage employed is bridge rectifier arrangement. The circuit diagram is

as shown In figure3.1 below

Terminal 1
240/15V D4 D1

D3 D2
Terminal 2

+
C1

Fig. 3.1: Full-wave Bridge Rectifier

3.2.3 The filter

This is made up of capacitor connected across the out put of the rectifier to

smoothen the voltage to have the minimum ripple factor (at least 10% of the

dc voltage). It is preferable to choose a filtering capacitor that will hold the

peak-to-peak ripples at approximately 10% of the peak voltage. Therefore;

Vripple = 0.1Vpeak
Vripple = 0.1 × 16.97
Vripple = 1.697V
But also Vripple = I/2fC for full wave
Where; I = current taken by the load
f = frequency of supply
C = filtering capacitor

31
 C = I /2fVripple
= 0.17/ (2 × 50 × 1.697)
C = 1001.7µF
From this calculation, a standard capacitor of 2200µF was chosen.

3.2.4 The Regulator

The regulator is a single chip that regulates the ripple free rectified
voltage to give a constant out put voltage. Since the circuit needs a supply
voltage of 12V and 5V, a 12V and 5V regulators were used. The percentage
regulation or simply regulator of a power supply is given by:
% regulation = [(Vmax – Vmin)/Vmax] × 100
Where;
Vmax = maximum dc output voltage
Vmin = minimum dc output voltage
In a general form
% regulation = [(Vno load – Vfull load)/Vfull load] × 100

3.3 CONTROL UNIT

DEVICE OVERVIEW

The PIC16F84A belongs to the mid-range family of the PIC micro®

microcontroller devices. A block diagram of the device is shown in Figure 1-

1. The program memory contains 1K words, which translates to 1024

32
instructions, since each 14-bit program memory word is the same width as

each device instruction. The data memory (RAM) contains 68 bytes. Data

EEPROM is 64 bytes. There are also 13 I/O pins that are user-configured on

a pin-to-pin basis. Some pins are multiplexed with other device functions.

These functions include:

• External interrupt

• Change on PORTB interrupt

• Timer clock input

PIC 16F84 Instruction Set

Move or Define Data

MOVLW k Loads W with literal.

MOVF f, d Moves copy of selected register contents

into W or f.

MOVWL f Moves copy of W contents into selected register

Change Register Contents

CLRF f Clears selected register to 0.

CLRW Clears W register to 0.

COMF f, d Complements selected register contents.

Result in W or f.

33
 DECF f, d Decrements selected register. Result in W or f.

(DECF 0x00  0xFF)

INCF f, d Increments selected register. Result in W or f.

(INCF 0xFF  0x00)

BCF f, d Clears selected bit in selected register to 0.

BSF f, d Sets selected bit in selected register to 1.

RLF f, d Rotates bits in selected register one position to the

left.

Bits rotate through carry flag. Result in W

or f.

RRF f, d Rotates bits in selected register one position to the

right.

Bits rotate through carry flag. Result in W

or f.

SWAPF f, d Exchanges MS and LS nibbles of selected

register. Result in W or f.

Control Program Flow

GOTO k Go to specified address.

CALL k Call subroutine at specified starting address.

RETURN Return from subroutine.

34
 RETLW k Return from subroutine. Load W with

literal.

RETFIE Return from interrupt.

BTFSC f, b Tests specified bit in specified register, skip

next instruction if clear.

BTFSS f, b Tests specified bit in specified register, skip

next instruction if set (1).

DECFSZ f, d Decrements specified register, skips next

instruction if register = 0.

Result in W or f.

INCFSZ f, d Increments specified register, skips next

instruction if register = 0.

Result in W or f.

Nothing

NOP Do nothing for one instruction cycle.

Control Microcontroller

CLRWDT Clear watchdog timer (reset to 0). Also resets

watchdog timer

Pre scalar. Status bits TO and PD are set

35
 OPTION W contents (bit pattern) sent to option register.

(Pre scalar ratio, RTC

Trigger edge and RTC source)

SLEEP Puts microcontroller to sleep to reduce

power consumption.

(wake up via reset, WDT, or external input)

TRIS f W bit pattern determines port line input vs. output

for selected port.

Logic SUBWF f,

ANDLW k W & k  W. d f - W  W or f.

ANDWF f, d W & f  W or f.

IORLW k W || k  W.

IORWF f, d W || f  W

or f.

XORLW k W xor k  W.

XORWF f, d W xor f  W or f.

Arithmetic

ADDLW k W + k  W.

ADDWF f, d W + f  W or f.

SUBLW k k - W  W.

36
 37

There are two memory blocks in the PIC16F84A. These are the program

memory and the data memory. Each block has its own bus, so that access to

each block can occur during the same oscillator cycle. The data memory can

further be broken down into the general purpose RAM and the Special

Function on each individual peripheral module. The data memory area also

contains the data EEPROM memory. This memory is not directly mapped

unto the data memory, but is indirectly mapped. That is, an indirect address

pointer specifies the address of the data EEPROM memory to read/write. The

64 bytes of data EEPROM memory have the address range 0h-3Fh.

3.3.1 Program Memory Organization

The PIC16FXX has a 13-bit program counter capable of addressing an 8K x

14 program memory space. For the PIC16F84A, the first 1K x 14 (0000h-

03FFh) are physically implemented (Figure 2-1). Accessing a location above

the physically implemented address will cause a wraparound. For example, for
 38

locations 20h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h, the

instruction will be the same.

The RESET vector is at 0000h and the interrupt vectors at 0004h

Fig. 3.2: Program memory map and stack.

3.3.2 Data Memory Organization

The data memory is partitioned into two areas. The first is the Special

Function Registers (SFR) area, while the second is the General Purpose

Registers (GPR) area. The SFRs control the operation of the device. Portions

of data memory are banked. This is for both the SFR area and the GPR area.
 39

The GPR area is banked to allow greater than 116 bytes of general purpose

RAM. The banked areas of the SFR are for the registers that control the

peripheral functions. Banking requires the use of control bits for bank

selection.

These control bits are located in the STATUS Register. Figure 2-2 shows the

data memory map organization. Instructions MOVWF and MOVF can move

values from the W register to any location in the register file (“F”), and vice-

versa. The entire data memory can be accessed either directly using the

absolute address of each register file or indirectly through the File Select

Register (FSR). Indirect addressing uses the present value of the RP0 bit for

access into the banked areas of data memory. Data memory is partitioned into

two banks which contain the general purpose registers and the special function

registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting

the RP0 bit selects Bank 1. Each Bank extends up to 7Fh (128 bytes). The first

twelve locations of each Bank are reserved for the Special Function Registers.

The remainders are General Purpose Registers, implemented as static RAM.

 40

Fig. 3.3: Data memory map

3.3.3 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable during normal operation

(full VDD range). This memory is not directly mapped in the register file

space. Instead it is indirectly addressed through the Special Function

Registers. There are four SFRs used to read and write this memory. These

registers are:
 41

• EECON1

• EECON2 (not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and EEADR holds the address

of the EEPROM location being accessed. PIC16F84A devices have 64 bytes

of data EEPROM with an address range from 0h to 3Fh. The EEPROM data

memory allows byte read and writes. A byte write automatically erases the

location and writes the new data (erase before write). The EEPROM data

memory is rated for high erase/write cycles. The write time is controlled by an

on-chip timer. The write time will vary with voltage and temperature as well

as from chip to chip. Please refer to AC specifications for exact limits. When

the device is code protected, the CPU may continue to read and write the data

EEPROM memory. The device programmer can no longer access this

memory.

[Link] Reading the EEPROM Data Memory

To read a data memory location, the user must write the address to the

EEADR register and then set control bit RD (EECON1<0>). The data is

available, in the very next cycle, in the EEDATA register; therefore, it can be
 42

read in the next instruction. EEDATA will hold this value until another read

or until it is written to by the user (during a write operation).

EXAMPLEOF DATA EEPROM READ

[Link] Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first write the address to

the EEADR register and the data to the EEDATA register. Then the user must

follow a specific sequence to initiate the write for each byte.

EXAMPLE OF DATA EEPROM WRITE

 43

3.4 THE CLOCK

The PIC16F84A can be operated in four different oscillator modes. The user

can program two configuration bits (FOSC1 and FOSC0) to select one of

these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP, or HS modes, a crystal or ceramic resonator is connected to the

OSC1/CLKIN andOSC2/CLKOUT pins to establish oscillation (Figure 6-1).

The PIC16F84A oscillator design requires the use of a parallel cut crystal. Use

of a series cut crystal may give a frequency out of the crystal manufacturers

Specifications. When in XT, LP, or HS modes, the device can have an

external clock source to drive the

OSC1/CLKIN pin.
 44

Recommended values of C1 and C2 are identical to the ranges tested in this

table. Higher capacitance increases the stability of the oscillator, but also

increases the start-up time. This circuit was operated in the HS mode and thus

the choice of capacitor used for this design was 33PF.

Capacitor selection for clocking is shown in the table below.

 45

3.5 LOADING THE PROGRAM

The program was loaded on the microcontroller by means of an interfacer

known as the programmer. The program and Hex code is given in appendix.

3.5.1 Assembler

The assembler used for this project is the MPLAB version 5.7 which was

downloaded from the microchip website. This is windows based integrated

development environment (IDE) software which gives support for the PIC and

other microcontrollers. This software contains a full featured editor, three

operating modes (editor, emulator, simulator, a project manager, customizable

tool bar and key mapping, status bar with project information.

MPLAB allows you to edit your source files (either in assembly or ‘C’).

Other features include debugging using:

 Source files

 Absolute listing file

3.5.2 PIC Programmer

This was used to burn the hex files into the PIC. This programmer has the

facility to program a PIC 16F84, erase the EEPROM, and also verify the

already written program for errors

3.6 PROGRAM FLOW CHART

 46

The program flow chart is given in appendix B

3.7 SWITCHING UNIT

The base of the BC109 transistor was connected to R 19 current limiting

resistor as shown, the value of which is obtained as;

R19
C945

Fig. 3.3: Transistor switch.

Where, , and
 47

3.8 ONE SHOT MULTIVIBRATOR

12V
Vs

R1 J1
VCC NO
RST OUT D1
1N4009 NC
DI S Key = Space
THR
555_VIRTUAL Rl
SI GNAL FROM THE SENSOR TRI
Timer
CON Q1
GND

C Cf BJT_NPN_VIRTUAL

Fig. 3.4: Monostable Multivibrator

Whenever a trigger pulse is applied to the input, the 555 will generate

its single-duration output pulse. Depending upon the values of external

resistance and capacitance used, the output timing pulse may be adjusted from

approximately one millisecond to as high as on hundred seconds. For time

intervals less than approximately 1-millisecond, it is recommended that

standard logic one-shots designed for narrow pulses be used instead of a 555

timer. IC timers are normally used where long output pulses are required. In
 48

this application, the duration of the output pulse in seconds is approximately

equal to:

T = 1.1 x R x C (in seconds)

3.9 TONE GENERATOR

12V
Vs
f r om count er

R1
VCC

RST OUT t o ampl i fi er

DI S

THR

TRI
R2
CON

GND
555_VIRTUAL
Timer
C Cf

Fig. 3.5: Tone generator.

The frequency of operation of the astable circuit is dependent on the

values of R1, R2 and C.

The frequency is obtained from:

(3.0)

Where, Transmission frequency in Hertz (Hz)

 49

MECHANICHAL PART
 50

CHAPTER FOUR: TESTS, RESULTS AND DISCUSSION

4.1 INTRODUCTION

This chapter deals with the description of tests performed on the various

sections of the overall system and their corresponding results as well as the

result of the overall system. In order to verify the correct functionality of the

system, each component had to be tested individually. To achieve the

effective testing of these various components, the following tools were used:

 Digital multimeter

 Bread board

 Logic probe

 Light emitting diodes

 MPLAB simulation software

The testing was done on each and every components/sections that make up the

circuit to ensure proper and satisfactory operation of the safe lock. The

debugging was done using the MPLAB; Each and every section of the code

was debugged properly to ensure proper functionality thus a step debugging

was done. This is a facility in the MPLAB that enables you step into program

and at the same Time views the registers and flag settings.
 51

4.2 OVERALL SYSTEM

The whole system was tested with various trials of six digit numbers

and only the sequence (*-1-2-3-4-5-6) turned on the output DC motor to

unlock the door as required. The code can be changed to the desired digital

combination by pressing * 1 2 3 4 5 6 * 1 9 6 8 7 8 # 1 9 6 8 7 8 # for

example. The close button is used to turn on the DC motor in reverse mode to

lock the safe as required. The touch activated alarm is being activated by any

small induced current on the touch plate to alert burgling attempt as expected

and the wrong pin alarm deactivated the whole system in any attempt of

hacking as required.

4.3 POWER SUPPLY

The power supply unit of +5V and +12V were tested for the output

voltage under no-load and full-load conditions.

Under no-load, the voltage of the +5V supply section was measured to

be 4.95V while that of the +12V supply was measured to be 11.94V. At full-

load, the respective voltages were measured as 4.85V and 11.83V.

Voltage Regulation (V.R) is given as;

 52

Where,

No-load Voltage

Full-load Voltage

For the units operating on +5V,

% %

For the units operating on +12V,

% %

From the results obtained above, the performance of the power supply

is satisfactory.
 53

CHAPTER FIVE: CONCLUSION AND

RECOMMENDATION

5.1 CONCLUSION

The aim of the project is to design a microcontroller based sliding door

system that can be used to lock and unlock a safe but its use can be extended

to other electronic locking systems such as doors. Having realized the device

and found working properly based on its design and relatively cheap

components involved in its realization, the aim of the project can be said to be

achieved. The project can be used as an effective security lock.

5.2 RECOMMENDATION

The project was designed to describe fully the locking and unlocking of

a safe system subject to a selected programmed sequence of input

combinations, the sequence manipulation and alarm only allows hardware

adjustment. Therefore means of software manipulation of the device should be

incorporated to enhance the system performance, especially between the touch

activation alarm and opening and closing process.

 54

REFERENCE
Boylestad, R.L and Nashelsky, L. (1996). Electronic Devices and
Circuit Theory, Prentice Hall, London.

Forrest M. M. III (1984). Getting started in Electronics, Printed in

the United States.

Green, D. C. (1982). Digital Electronics Technology, Pitman

Publishing Ltd. New Zealand.

Theraja B.L. & Theraja A.K. (2002). A textbook of Electrical

Technology, S. Chand and Company Ltd. New Delhi.

[Link]
 55

APPENDIX A

Flow Chart

START

ENTER
THE
PASSWORD

NO

NO
IS THE IS
PASSWORD N=4
RIGHT

YES YES

OPEN THE TURN ON THE

DOOR ALARM

END
 56

APPENDIX B
Microcontroller circuit arrangement
 57

APPENDIX C
; CODELOCK program
Author: Abubakar Ibrahim Musa
Supervisor: Engr. (Dr.) G.A Bakare
;=============================================
; HARDWARE
;=============================================
; Keyboard connections
;
; RB0 = scanline 0
; RB1 = scanline 1
; RB2 = scanline 2
; RB3 = returnline 0
; RB4 = returnline 1
; RB5 = returnline 2
; RB6 = returnline 3
;(key = 3 x returnline (0,1,2,3) + scanline (0,1,2)
;
; RA2 = BEEPER active low
;
;RA3 = LED active low
;
; RA0 = level output
; RA1 = pulse output
;
;
;
;============================================
; Configuration
;============================================

RC equ b'11' ;RC oscillator

XT equ b'01' ;XT oscillator
WDTE equ b'100' ;watchdog timer
PWRTE equ b'1000' ;power up timer
CPOFF equ b'10000' ;code protection

PROCESSOR 16c84
__CONFIG RC+CPOFF+PWRTE
 58

;============================================
; Constants
;============================================

;general

w equ 0
f equ 1
indf equ 00h ;indirect file
fsr equ 04h ;pointer to indirect file
ram equ 0ch ;rambottom (start)
status equ 03h ;status register file
porta equ 05h ;port A
portb equ 06h ;port B

intcon equ 0bh ;interrupt control register

rbif equ 00h ;rb has changed, interrupt event flag
rbie equ 03h ;rb interrupt enable flag
gie equ 07h ;global interrupt enable flag
inte equ 04h ;RB0/INT interrupt enable flag
intf equ 01h ;RB0/INT interrupt event flag
optreg equ 81h ;option register
intedg equ 06h ;INT edge

trisa equ 85h ;port A direction register

trisb equ 86h ;port B direction register

eecon1 equ 88h ;eeprom control register

eecon2 equ 89h ;eeprom data control register
eedata equ 08h ;eeprom data register
eeadr equ 09h ;eeprom adress register
eeif equ 04h ;
wrerr equ 03h ;
wren equ 02h ;
wr equ 01h ;
rd equ 00h ;

rp0 equ 05h ;register bank

zero equ 02h ;zero bit position in status register
 59

carry equ 00h ;carrybit position in status register

PC equ 02h ;program counter register

;============================================
; macro definitions
;============================================
jz macro lab1
btfsc status,zero
goto lab1
endm

jnz macro lab2

btfss status,zero
goto lab2
endm

jc macro lab3
btfsc status,carry
goto lab3
endm

jnc macro lab4

btfss status,carry
goto lab4
endm

;============================================
; setbank
;============================================
setbank macro banknr
if banknr == 0
bcf status,rp0
endif
if banknr == 1
bsf status,rp0
endif
endm

;============================================
; portio
 60

;
; sets tris of port
; usage: portio porta,b'10010011' ;example
; 0 is output, 1 is input
;============================================
portio macro portnr,io
clrf portnr
setbank 1
movlw io
if portnr == porta
movwf trisa
endif
if portnr == portb
movwf trisb
endif
setbank 0
endm

;============================================
; program constants
;============================================

nokey equ 0ffh

hekje equ .12
sterretje equ .10

;============================================
; variables
;============================================
org ram

del0 equ ram+0

del1 equ ram+1
del10 equ ram+2
scanln equ ram+3
retval equ ram+4
retln equ ram+5
key equ ram+6
scankey equ ram+7
 61

newkey equ ram+8

digit equ ram+9
match equ ram+0Ah

ncode0 equ ram+0Bh

ncode1 equ ram+0Ch
ncode2 equ ram+0Dh
ncode3 equ ram+0Eh
ncode4 equ ram+0Fh
ncode5 equ ram+10h

tries equ ram+11h

;last ram locatation = ram + 23h

;============================================
; reset addres
;============================================
org 0
goto start

;============================================
; identify interrupt source
;============================================
org 4
goto interrupt

;============================================
; rdeeprom
; reads byte from eeprom
; entry EEADR, exit EEDATA
;============================================
rdeeprom:
bsf status,rp0
bsf eecon1,rd
bcf status,rp0

return
 62

;============================================
; wreeprom
;
; writes a byte of data to eeprom
;
; entry: eedata,eeadr
;============================================
wreeprom:

bcf intcon,gie ;disable ints

bsf status,rp0 ;bank 1
bsf eecon1,wren ;enable write

;write sequence

movlw 55h
movwf eecon2
movlw 0aah
movwf eecon2
bsf eecon1,wr ;begin write

waitwr:
btfsc eecon1,wr
goto waitwr ;wait for writecycle complete

bcf status,rp0 ;bank 0

bsf intcon,gie ;reenable ints

return

;============================================
; interrupt routines
;============================================
interrupt:
retfie

;============================================
;
;============================================
 63

;============================================
; Init
;============================================
init:
portio porta,b'00000'
portio portb,b'11111000'

bcf porta,0 ;clear level output

bcf porta,1 ;clear pulse output

bsf porta,2 ;beeper off

; bsf porta,3 ;led off

movlw 7h
movwf portb ;set keyboard scanlines

movlw 1
movwf newkey

clrf tries

;test if signature is written in EEPROM

;if not then write signature and initial code
;else do nothing
;signature = AAh,55h,CCh, initial accescode = 1 2 3 4 5 6

movlw 6
movwf eeadr ;first signature adress
call rdeeprom
movlw 0AAh
subwf eedata,w
jnz nosig

incf eeadr
call rdeeprom
movlw 055h
subwf eedata,w
jnz nosig
 64

incf eeadr
call rdeeprom
movlw 0CCh
subwf eedata,w
jnz nosig

;signature match, do nothing

return
nosig:
;no valid signature (first startup), write signature and accescode

clrf eeadr
movlw 1
movwf eedata
wrcod:
call wreeprom
incf eedata
incf eeadr
movlw 6
subwf eeadr,w
jnz wrcod

;code written, write signature

movlw 0AAh
movwf eedata
call wreeprom
incf eeadr

movlw 055h
movwf eedata
call wreeprom
incf eeadr

movlw 0CCh
movwf eedata
call wreeprom

return
 65

;============================================
; beep
; beeps 50mS
;============================================
beep:
bcf porta,2
movlw .5
movwf del10
call delay10
bsf porta,2

return

;============================================
; delay10
; delays del10 x 10mS
;============================================
delay10:
;delayloop 10 mS
movlw .40
movwf del1
dec250u:
;delayloop 250 uS
movlw .83
movwf del0
dec1u:
decfsz del0
goto dec1u

decfsz del1
goto dec250u

decfsz del10
goto delay10

return
;============================================
delay macro dly00
movlw dly00
movwf del10
 66

call delay10
endm

;============================================
; scankeyboard
; scans the keyboard
; returns scankey = 1..12, 0ffh = nokey
; scankey is nokey if no key is pressed
; scanlines = RB0..RB2
; returnlines = RB3..RB6
;============================================
scankeyboard:

;find scanline

movlw 0
movwf portb
clrf scanln
bsf portb,0
nop
movf portb,w
andlw b'01111000'
jnz retl
incf scanln
bsf portb,1
nop
movf portb,w
andlw b'01111000'
jnz retl
incf scanln
bsf portb,2
nop
movf portb,w
andlw b'01111000'
jnz retl
goto nokeyp ;no keypress

;scanline found, find returnline

retl:
clrf retln
 67

movf portb,w
movwf retval
rrf retval
rrf retval
rrf retval
nxtrl:
bcf status,carry
rrf retval
jc keyfound
incf retln
movlw 4
subwf retln,w
jnz nxtrl

;no (new) key pressed, exit

nokeyp:
movlw nokey
movwf scankey
return

keyfound:

;key found, calculate keynumber = 3x RL + SL + 1

movf retln,w
bcf status,carry
rlf retln ;2x
addwf retln,f ;3x
movf scanln,w
addwf retln,w
movwf scankey

incf scankey

return

;============================================
; getkey
; exits key:1..12,nokey
; debounced filtered output
;============================================
 68

getkey:
call scankeyboard
movf scankey,w
movwf key
movlw .2
movwf del10
call delay ;delay 20mS
call scankeyboard
movf scankey,w
subwf key,w
jnz getkey

;debounce complete

;test if the key is a new keypress, if not return nokey=0ffh

movlw nokey
subwf key,w
jnz exitkey
movlw 1
movwf newkey ;next key is new
goto pkey

exitkey:
movlw 1
subwf newkey,w
jnz pkey
clrf newkey
return

pkey: ;exit nokey

movlw nokey
movwf key
return
;============================================
; readkey
; reads keyboard until key pressed
; exits key = 1..12
;============================================
readkey:
 69

call getkey
movlw nokey
subwf key,w
jz readkey
call beep

return

;============================================
; main program
;============================================
start:
call init
call beep

rdkey:
call readkey ;wait for key

;key pressed

movlw sterretje
subwf key,w
jnz rdkey

; '*' pressed

nxkey0:
call readkey

;find out if second key is a number, '*' or '#'

movlw sterretje
subwf key,w
jz deactivate ;'**' pressed, deactivate ouput, restart input

movlw hekje
subwf key,w
jz getcode ;'*#' goto new code input

;'*number' pressed, read code, key holds first digit

 70

movlw 6
movwf digit ;digit count, 6
movlw 1
movwf match ;code match to input flag
clrf eeadr ;start with eeprom adress 0
rdee:
call rdeeprom
movf eedata,w
subwf key,w ;compare stored codedigit to key
jz eq00
clrf match
eq00:
decfsz digit
goto nxtdg00

;6 digits compared
btfss match,0
goto nomatch0 ;no match, do nothing, return to input start

;codes match, set outputs

clrf tries
bsf porta,0 ;set level
; bcf porta,3 ;LED on

;pulse 1 sec
;beep 1 sec
bcf porta,2
bsf porta,1 ;set pulse
delay .100
bcf porta,1
bsf porta,2

goto rdkey

deactivate:
bcf porta,0 ;deactivate output
; bsf porta,3 ;LED off
goto nxkey0
 71

nxtdg00:
call readkey ;wait for key

;key pressed
movlw sterretje
subwf key,w
jz nxkey0 ;restart input

movlw hekje
subwf key,w
jz rdkey ;restart input

;digit pressed
incf eeadr
goto rdee

nomatch0:
;wrong accescode entry
incf tries
movlw 4
subwf tries,w
jnz nomatch

;four times mismatch in a row

;alarm for 1 minute
movlw .60
movwf digit

alarm:
call beep ;50mS
delay .15 ;150ms
call beep ;50
delay .15 ;150
call beep ;50
delay .55 ;550mS

decfsz digit
goto alarm
goto rdkey
 72

nomatch:
;beep 3x
delay .30
call beep
delay .10
call beep
delay .10
call beep

goto rdkey

getcode:
;'*#' pressed, get new accescode
;format = '*#ooooonnnnnmmmmm'
;o = oldcode,n = newcode, m = newcode verification

;read and verify the old code

movlw 1
movwf match
movlw 6
movwf digit
clrf eeadr

;read digit and verify

gtdg00:
call readkey ;wait for key
movlw sterretje
subwf key,w
jz nxkey0 ;'*' pressed, restart input

movlw hekje
subwf key,w
jz nomatch ;error in input

;digit pressed, compare to eeprom

call rdeeprom
movf key,w
subwf eedata
 73

jz match00
clrf match ;mismatch in input
match00:
incf eeadr
decfsz digit
goto gtdg00 ;read next

;read and save new accescode

movlw 6
movwf digit
movlw ncode0
movwf fsr ;point to first digit

rdnc00:
call readkey ;wait for key
movlw sterretje
subwf key,w
jz nxkey0 ;'*' pressed, restart input

movlw hekje
subwf key,w
jz nomatch ;error in input

movf key,w
movwf indf

incf fsr
decfsz digit
goto rdnc00

;new code saved

;read verification of newcode and compare

movlw 6
movwf digit
movlw ncode0
movwf fsr ;point to saved code
 74

rdvc00:
call readkey ;wait for key
movlw sterretje
subwf key,w
jz nxkey0 ;'*' pressed, restart input

movlw hekje
subwf key,w
jz nomatch ;error in input

movf indf,w
subwf key,w
jz mok
clrf match ;key and saved digit differ, no match

mok:
incf fsr
decfsz digit
goto rdvc00

;new code verified, test if matched

btfss match,0
goto nomatch ;input mismatch, error signal, restart input

;codes match, store new code in eeprom

;long beep
bcf porta,2
delay .100
bsf porta,2

movlw 6
movwf digit
movlw ncode0
movwf fsr
clrf eeadr

store00:
movf indf,w
 75

movwf eedata
call wreeprom

incf fsr
incf eeadr
decfsz digit
goto store00

goto rdkey ;new code stored in eeprom, restart input

;============================================
; eeprom definition
;============================================
org 2100h

de 0,0,0,0,0,0,0,0,0

end