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MODULE 4
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Unsymmetrical Fault Analysis
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Course Objectives
1. To explain the analysis of synchronous machine and simple power systems for different unsymmetrical faults using
symmetrical components
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4.1 INTRODUCTION
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The sequence circuits and the sequence networks developed in the previous chapter will now be used for finding out fault
current during unsymmetrical faults. Specifically we are going to discuss the following three types of faults:
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• Single-line-to-ground (1LG) fault
• Line-to-line (LL) fault
• Double-line-to-ground (2LG) fault
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4.2 Symmetrical Component Analysis of Unsymmetrical Faults
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For the calculation of fault currents, we shall make the following assumptions:
• The power system is balanced before the fault occurs such that of the three sequence networks only the positive sequence
network is active. Also as the fault occurs, the sequence networks are connected only through the fault location.
• The fault current is negligible such that the pre-fault positive sequence voltages are same at all nodes and at the fault location.
• All the network resistances and line charging capacitances are negligible.
• All loads are passive except the rotating loads which are represented by synchronous machines.
Based on the assumptions stated above, the faulted network will be as shown where the voltage at the faulted point will be denoted
by Vf and current in the three faulted phases are Ifa, Ifb and I fc. We shall now discuss how the three sequence networks are connected
when the three types of faults discussed above occur.
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U Fig4 .1 Representation of faulted segment
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4.3 Single Line-To-Ground (LG) Fault, Line-To-Line (LL) Fault, Double Line-To-Ground (LLG) Fault
Let a 1LG fault has occurred at node k of a network. The faulted segment is shown where it is assumed that phase-a has
touched the ground through an impedance Zf. Since the system is unloaded before the occurrence of the fault we have
Fig. 4.2: Representation of 1LG fault.
Also the phase-a voltage at the fault point is given by
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This implies that the three sequence currents are in series for the 1LG fault. Let us denote the zero, positive and negative
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sequence Thevenin impedance at the faulted point as Zkk0, Zkk1 and Zkk2 respectively. Also since the Thevenin voltage at the faulted
phase is Vf we get three sequence circuits
The Thevenin equivalent of the sequence network is shown
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U Fig 4.3: Thevenin equivalent of a 1LG fault.
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4.3.1 LINE-TO-LINE FAULT
The faulted segment for an L-L fault is shown where it is assumed that the fault has occurred at node k of the network. In this the
phases b and c got shorted through the impedance Zf. Since the system is unloaded before the occurrence of the fault we have
Fig 4.4: Representation of L-L fault.
Also since phases b and c are shorted we have
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Therefore no zero sequence current is injected into the network at bus k and hence the zero sequence
remains a dead network for an L-L fault. The positive and negative sequence currents are negative of
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each other.
The voltage at the faulted point
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U Fig 4.5: Thevenin equivalent of an LL fault.
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5.5 DOUBLE-LINE-TO-GROUND FAULT
The faulted segment for a 2LG fault is shown where it is assumed that the fault has occurred at node k of the network. In this
the phases b and c got shorted through the impedance Zf to the ground. Since the system is unloaded before the occurrence of the
fault we have the same condition as for the phase-a current. Therefore
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Fig. 4.6: Representation of 2LG fault.
Also the voltages of phases b and c are given by
The Thevenin equivalent circuit for 2LG fault is shown
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The zero and negative sequence currents can be obtained using the current divider principle as
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Fig. 4.7: Thevenin equivalent of a 2LG fault.
Course Outcome
At the end of the module, students will be able to:
Analyze unsymmetrical fault currents using symmetrical components. [L4]
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Department of Electrical and Electronics Engineering, Mysuru
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