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Question4 Tutorial

The document presents a set of example questions related to the design and analysis of CMOS complex logic circuits. It includes tasks such as implementing logic functions, sizing circuits to minimize delay with specific load capacitances, and comparing implementations based on speed and transistor width. The questions require calculations and considerations of circuit design principles to achieve optimal performance.

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3 views1 page

Question4 Tutorial

The document presents a set of example questions related to the design and analysis of CMOS complex logic circuits. It includes tasks such as implementing logic functions, sizing circuits to minimize delay with specific load capacitances, and comparing implementations based on speed and transistor width. The questions require calculations and considerations of circuit design principles to achieve optimal performance.

Uploaded by

chenglons
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Design and Analysis of Digital Integrated Circuits

Example Ques:ons – Week 4

CMOS Complex Logic and LE


Ques:on:

For this problem assume that γ=0.8 and tinv is the unit delay of an inverter ( i.e.,
tp = :nv(γ+f) ). Express all the delay values in terms of tinv.

a) Implement the logic func:on given by the expression shown below as a


complex CMOS gate followed by an inverter. Assuming the complex gate is
sized for equal rise and fall delays, what is its LE?
Out = AB + CD
b) Implement the same logic func:on using only NAND2, NOR2, and
inverters.
c) Add a load capacitance of CL=128*Cin at the output of your circuit from
part a). Now size the circuit to minimize the delay. What is the minimum
delay? Note that you can assume that it is always the input closest to the
output node that switches – i.e., you do not need to include any of the
parasi:cs on the intermediate nodes of the complex gate when
calcula:ng delay.
d) Add a load capacitance CL=128*Cin at the output of your circuit from part
b) and size the circuit to minimize the delay. Note that Cin in parts a) and
b) must be equal. Now what is the minimum delay?
Hint: You might want to change the implementa3on from part b) so that the circuit
has a total number of stages that is close to the op3mal one. Also, pay a=en3on to
which gates are be=er drivers and try to rearrange the circuit so that they are placed
closer to the load.
e) If CL=2*Cin, which implementa:on is now faster? Which one is be[er in
terms of total transistor width? Note that you do not need to repeat all of
the calcula:ons; a well-explained, intui:ve answer will receive the full
credit.

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