Basic Electronics [BBEE203] Module-2

MODULE 2:

Syllabus:

Bipolar Junction Transistors: Introduction, BJT Voltages & Currents, BJT Amplification, Common
Base Characteristics, Common Emitter Characteristics, Common Collector Characteristics.

BJT Biasing: Introduction, DC Load line and Bias point.

Field Effect Transistor: Junction Field Effect Transistor, JFET Characteristics, MOSFETs:
Enhancement MOSFETs, Depletion Enhancement MOSFETs.

2.1 BIPOLAR JUNCTION TRANSISTORS: INTRODUCTION

• A bipolar junction transistor (BJT) has three layers of semiconductor material. These are
arranged either in npn (n-type-p-type-n-type) sequence or in pnp sequence, and each of the
three layers has a terminal.
• A small current at the central region terminal controls the much larger total current flow
through the device. This means that the transistor can be used for current amplification and it
can also perform voltage amplification.
• Because the transistor has two pn-junctions, its operation can be understood by applying pn-
junction theory. The transistor equivalent circuit is essentially two pn-junction equivalent
circuits.

2.2 BJT OPERATION (pnp and npn Transistors)

• A bipolar junction transistor is simply a sandwich of one type of semiconductor material (p-
type or n-type) between two layers of the opposite type.
• A block representation of a layer of p-type material between two layers of n-type is shown in
Fig. 2.1a. This is described as an npn transistor.

Figure 2.1 Block representation of npn and pnp bipolar junction transistors (BJTs).

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• Figure 2.1b shows a pnp transistor, consisting of a layer of n-type material between two layers
of p-type.
• The centre layer is called the base, one of the outer layers is termed the emitter, and the other
outer layer is referred to as the collector.
• The emitter, base, and collector are provided with terminals, which are appropriately labelled
E, B and C.
• Two pn-junctions exist in each transistor: the collector-base junction and the emitter-base
junction. Each of these junctions has the characteristics same as Diode.
• Circuit symbols for pnp and npn transistors are shown in Fig. 2.2. The arrowhead on each
symbol identifies the transistor emitter terminal and indicates the conventional direction of
current flow.
• For an npn transistor, the arrowhead points from the p-type base to the n-type emitter.
• For a pnp device, the arrowhead points from the p-type emitter to the n-type base. Thus, the
arrowhead always points from p to n.

Figure 2.2 BJT graphic symbols. The arrowhead identifies the emitter terminal; it always points in
the conventional current direction.

• Two pn-junctions are formed with depletion regions and barrier voltages at each junction.
• The barrier voltages are negative on the p-side and positive on the n-side.
• The base-emitter junction is forward-biased, so that charge carriers are emitted into the base.
• The collector-base junction is reverse-biased, and its depletion region penetrates deep into the
base.
• The base section is made as narrow as possible so that charge carriers can easily move across
from emitter to collector.
• The base is lightly doped, so that few charge carriers are available to recombine with the
majority charge carriers from the emitter.
• Most charge carriers from the emitter flow to the collector; a few flow out through the base
terminal.
• Variation of the base-emitter junction bias voltage alters the base, emitter and collector
currents.

2.3 BJT VOLTAGES AND CURRENTS

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Terminal Voltages:

The terminal voltage polarities for an npn transistor are shown in Fig. 2.3a. As well as conventional
current direction, the direction of the arrowhead indicates the transistor bias polarities.

For an npn transistor, the base is biased positive with respect to the emitter, and the arrowhead
points from the (positive) base to the (negative) emitter. The collector is then biased to a higher
positive voltage than the base.

Figure 2.3b shows that the voltage sources are usually connected to the transistor via resistors.

Figure 2.3 An npn BJT must have its base biased positive with respect to its emitter, and Its
collector must be biased more positive than the base.

The base bias voltage (VB) is connected via resistor RB, and the collector supply (VCC) is connected
via RC. The negative terminals of the two voltage sources are connected at the transistor emitter
terminal. VCC is always much larger than VB, and this ensures that the collector-base junction
remains reverse-biased: positive on the collector (n-side) and negative on the base (p-side).

Typical transistor base-emitter voltages are similar to diode forward voltages: 0.7 V for a silicon
transistor and 0.3 V for a germanium device. Typical collector voltages might be anything from 3 V
to 20 V for most types of transistors.

For a pnp device as shown in Figure 2.4a, the base is biased negative with respect to the emitter.
The arrowhead points from the (positive) emitter to the (negative) base, and the collector is made
more negative than the base.

Figure 2.4 A pnp BJT must have its base biased negative with respect to its emitter, and its
collector must be biased more negative than the base.
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Figure 2.4b shows the voltage sources connected via resistors, and the source positive terminals
connected at the emitter. With VCC larger than VB, the (p-type) collector is more negative than the
(n-type) base, and thus the collector-base junction is kept reverse-biased.

All BJTs (npn and pnp) are normally operated with the collector-base junction reverse-biased and
the base-emitter junction forward-biased.

Transistor Currents

The various current components that flow within a

transistor are illustrated in Fig. 2.5. The current flowing
into the emitter terminal is referred to as the emitter
current and is identified as IE. For the pnp device shown, IE
can be thought of as a flow of holes from the emitter to the
base and IE direction is the conventional current direction
from positive to negative. Base current IB and collector
current IC are also shown as conventional current
direction. Both IC and IB flow out of the transistor while IE
flows into the transistor. Therefore, Figure 2.5 Currents in a pnp BJT.
IE = IC + IB

Almost all of IC crosses to the collector and only a small portion flows out of the base terminal.
Typically 96% to 99.5% of IE flows across the collector-base junction to become the collector
current. As shown in Fig. 2.5,
IC = αdc IE

where αdc (alpha dc) is the emitter-to-collector current gain, or the ratio of collector current to
emitter current.
αdc = IC / IE

αdc is typically 0.96 to 0.995. So, the collector current is almost equal to the emitter current, and in
many circuits IC is assumed to be equal to IE. αdc termed the common-base dc current gain.

Because the collector-base junction is reverse-biased, a very small reverse saturation current (ICBO)
flows across the junction. ICBO is named the collector-to-base leakage current, and it is normally so
small that it can be ignored.

Substituting for IE,

IC = αdc (IC + IB)
which gives,
𝛼𝑑𝑐 𝐼𝐵
𝐼𝐶 =
1 − 𝛼𝑑𝑐
This can be rewritten as
IC = βdc IB

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Where
𝛼𝑑𝑐
𝛽𝑑𝑐 =
1 − 𝛼𝑑𝑐

βdc (beta dc) is the base-to-collector current gain, or the ratio of collector current to base current.
This is shown in Fig. 2.6.
βdc = IC / IB

Figure 2.6 Terminal currents for a pnp BJT.

Typically, βdc ranges from 25 to 300. It is also termed the collector-emitter dc current gain. Another
symbol for common-emitter dc current gain is hFE. This originates from the h-parameter circuit,
and is the symbol used on transistor data sheets.

Equations derived for a pnp device, they apply equally to npn transistors. One difference in the case
of an npn transistor is that IB and Ic are assumed to flow into the device and IE is taken as flowing
out. This is shown in Fig. 2.7. Electrons are the majority charge carriers in an npn transistor, and
they move in a direction opposite to conventional current direction.

Figure 2.7 Terminal currents for an npn BJT.

Typical collector and emitter currents for low-power transistors range from 1 mA to 25 mA, and
base currents are usually less than 100 µA.

Example: Calculate IC and IE for a transistor that has αdc = 0.98 and IB = 100 µA. Determine the
value of βdc (or hFE) for the transistor.

Solution:
𝛼𝑑𝑐 𝐼𝐵 0.98 X 100𝜇𝐴
𝐼𝐶 = =
1 − 𝛼𝑑𝑐 1 − 0.98

= 4.9 mA

𝐼𝐶 4.9𝑚𝐴
𝐼𝐸 = =
𝛼𝑑𝑐 0.98
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= 5 mA
𝛼𝑑𝑐 0.98
𝛽𝑑𝑐 = =
1 − 𝛼𝑑𝑐 1 − 0.98

= 49

2.3 BJT AMPLIFICATION

Current Amplification

The equations derived demonstrate that a transistor can be used for current amplification. A small
change in the base current (ΔIB) produces a large change in collector current (ΔIC) and a large
emitter current change (ΔIE) as shown in Figs 2.8a and b. The current gain from the base to
collector can be stated in terms of current level changes.
𝛥𝐼𝐶
𝛽𝑑𝑐 =
𝛥𝐼 𝐵
The increasing and decreasing levels of input and output currents may be defined as alternating
quantities. In this case, small (lower-case) letters are used for the subscripts. Thus, Ib is an ac base
current, Ic is an ac collector current, and Ie is an ac emitter current. The alternating current gain
from base to collector may now be stated as
𝐼𝑐
𝛽𝑎𝑐 =
𝐼𝑏

Figure 2.8 BJT current amplification. Increasing and decreasing the IB levels produces much
larger changes in IC and IE,

As in the case of dc current gain, two parameter symbols are available for common-emitter ac
current gain: βac and hfe. Either symbol may be used, but, hfe is the symbol employed on transistor
data sheet.

Voltage Amplification

Refer to the circuit in Fig. 2.9a, and assume that the transistor (Q1) has βdc = 50. Note that the 0.7
V dc voltage source (VB) forward biases the transistor base-emitter junction. An ac signal source

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(vi) in series with VB provides a ±20 m V input voltage. The transistor collector is connected to a
20 V dc voltage source (Vcc), via the 12 kΩ collector resistor (R1).

Figure 2.9 BJT voltage amplification.

If Q1 has the IB/ VBE characteristic as shown in Fig. 2.9b, the 0.7V level of VB produces a 20 µA base
current. This gives
IC = βdc IB = 50 X 20 µA

= 1 mA

The dc level of the transistor collector voltage can now be calculated as follows:

VC = VCC - (IC R1) = 20 V – (1 mA x 12 kΩ)

=8V

While the ac input voltage (vi) is zero, the transistor collector voltage remains at 8 V. When vi cause
a base voltage variation (ΔVB) of ±20 mV, the base current changes by ±5 µA, as shown in Fig. 2.9b.
The IB change produces a change in the collector current.

ΔIC = βdc ΔIB = 50 X (±5 µA)

= ±250 µA

The ΔIC causes a change in the voltage drop across R1 and thus produces a variation in the transistor
collector current.

ΔVC = ΔIc R1 = ±250 µA x 1112 kΩ

= ±3V

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The circuit ac input is the base voltage change (ΔVB), and the ac output is the collector voltage
change (ΔVc). Because the output is greater than the input, the circuit has a voltage gain: it is a
voltage amplifier.

Summary: Increasing and decreasing the (input) VB voltage (±ΔVB) produces IB changes. This
results in larger IC changes and (output) VC variations (±ΔVC) that are larger than the input voltage
changes.

The voltage gain (Av) is the ratio of the output voltage to the input voltage.
𝛥𝑉𝐶 ±3𝑉
𝐴𝑣 = = 𝛽𝑑𝑐 =
𝛥𝑉𝐵 ±20𝑚𝑉
= 150

Increasing and decreasing levels of voltage can be referred to as an ac quantities. The ac signal
voltage (vi) produces the ac base current (Ib), and this generates the ac collector current (vc), which
produces the ac voltage change across R1. The equation for ac voltage gain is
𝑣𝑜
𝐴𝑣 =
𝑣𝑖

2.4 COMMON-BASE CHARACTERISTICS

Common-Base Circuit

Transistor is a three-terminal device, there

are three possible connection
arrangements (configurations) for
investigating its characteristics.
Figure 2.10 Circuit for investigating BJT
Figure 2.10 shows a pnp transistor with its common-base characteristics.
base terminal common to both the input
(emitter-base) terminals and the output (collector-base) terminals. The transistor is said to be
connected in common-base configuration. Voltmeters and ammeters are included to measure the
input and output voltages and currents. Resistor R1 is to assist in controlling the emitter current.

Common-Base Input Characteristics

To investigate the input characteristics, the output voltage (VCB) is kept constant, and the input
voltage (VEB) is set at several convenient levels. At each input voltage, the corresponding input
current (IE) is recorded. The IE and VEB levels are then plotted to give the common-base input
characteristics as shown in Fig. 2.11. Because the emitter-base junction is forward-biased, the
characteristics are same as forward- biased pn-junction.

Figure 2.11 also shows that for a given input voltage (VEB), more input current flows when higher
levels of collector-base (VCB) voltage are used.

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Common-Base Output Characteristics

To plot the output characteristics, IE is held constant at

each of several fixed current levels, VCB is adjusted in
convenient steps, and the corresponding values of IC are
recorded. In Fig. 2.12, the corresponding IC and VCB levels
obtained when IE was held constant at 1 mA, 2 mA, 3mA,
and so on.

The common-base output characteristics in Fig. 2.12

show that for each fixed level of IE, IC is almost equal to IE,
and IC appears to remain constant when VCB is increased.
With IE held constant, the increase in IC is so small that it
is noticeable only for large chance in VCB. The slope on the Figure 2.11 The common-base
output characteristics is sometimes referred to as Early input characteristics for a BJT.
effect.

Figure 2.12 The common-base output characteristics (or collector characteristics) for a BJT

When VCB is reduced to zero, IC still flows. This is because, even when the externally applied voltage
is zero, there is still a barrier voltage existing at the collector-base junction, and this assists the flow
of IC. The charge carriers which constitute IC are minority carriers as they cross the collector-base
junction. To stop the flow of charge carriers, the collector-base junction has to be forward-biased.
As shown in Fig. 2.12, IC is reduced to zero only when VCB is increased positively.

The region of the graph for the forward-biased collector-base junction is known as the saturation
region. The region in which the junction is reverse-biased is named the active region; this is the
normal operating region for the transistor. If an excessive reverse-bias voltage is applied to the
collector-base junction, the device breakdown may occur.
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Breakdown, illustrated by the dashed lines in Fig.

2.12, can be caused by the zener or Avalanche
effect. Breakdown can also result from the
collector-base depletion region penetrating into
the base (as the reverse bias is increased) until it
makes contact with the emitter-base depletion
region as shown in Fig. 2.13. This condition is
known as punch-through or reach-through, and
very large currents can flow when it occurs,
possibly destroying the device.

Summary: The common-base output

characteristics (or collector characteristics) for a
BJT are a graph of (output) collector current IC
plotted versus (output) collector-base voltage VCB Figure 2.13 Excessive levels of (reverse
for various constant levels of (input) emitter bias) collector-base voltage (VCB) can
current IE. In the active region, IC remains cause the junction depletion regions to
substantially constant for each level of IE make contact, resulting in destructive
regardless of VCB, In the saturation region, IC is current levels.
reduced to zero when VCB is forward-biased.

Common-Base Current Gain Characteristics

The common-base current gain characteristics for a BJT are a graph of output current (IC) plotted
versus input current (IE) with the output voltage (VCB) held constant as shown in Fig. 2.14.

Figure 2.14 The common-base current gain characteristics for a BJT.

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The common-base current gain characteristics can be derived from the common-base output
characteristics. Because almost all of IE flows out of the collector terminal as IC, VCB has only a small
effect on the current gain characteristics.

2.5 COMMON EMITTER CHARACTERISTICS

Common-Emitter Circuit

Figure 2.15 shows a circuit for determining BJT common-

emitter characteristics. The input voltage is applied
between the base and emitter terminals, and the output
is taken at the collector and emitter terminals, so that the
emitter terminal is common to both input and output.
Resistor R1 is to assist in controlling the emitter current.
Figure 2.15 Circuit for investigating
Common-Emitter Input Characteristics BJT common-emitter characteristics.
To construct the common-emitter input characteristics,
VCE is held constant, VBE is set at convenient levels, and
the corresponding IB levels are recorded. IB is then
plotted versus VBE, as shown in Fig. 2.16. It is seen that
the common-emitter input characteristics are those of
a forward-biased pn-junction.

Figure 2.16 also shows that, for a given level of VBE, IB is

reduced when higher VCE levels are employed. This is
because the higher VCE produces greater depletion
region penetration into the base, reducing the distance
between the collector-base and emitter-base depletion
regions.

Consequently, more of the charge carriers from the Figure 2.16 The common-emitter
emitter flow across the collector-base junction, and input characteristics for a BJT.
fewer flow out through the base terminal.

Common-Emitter Output Characteristics

To plot the common-emitter output characteristics, IB is maintained constant at several convenient

levels as shown in Fig. 2.15. The common-emitter output characteristics (or collector
characteristics) for a BJT are a graph of (output) collector current IC plotted versus (output)
collector-emitter voltage VCE for various constant levels of (input) base current IB as shown in Fig.
2.17. Note that the VBE and VCE polarities are negative for the characteristics shown. This is because
of pnp transistor.

In Fig. 2.17 note that IC reduce to zero when VCE become zero. This is because the horizontal axis
voltage (VCE) equal VCB + VBE. At the knee of the characteristic, the collector-base junction voltage
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(VCB) has been reduced to zero. Further reduction in VCE causes the collector base junction to be
forward-biased, and this repels minority charge carriers, thus reducing IC to zero.

Figure 2.17 The common-emitter output characteristics (or collector characteristics) for a BJT.

The dashed lines in Fig. 2.17 show that, if VCE exceed a maximum safe voltage, IC increases rapidly
causing Breakdown. This is
due to punch-through, and it
could destroy the BJT.

Common-Emitter Current
Gain Characteristics

The common-emitter current

gain characteristics are
output current (IC) plotted
versus input current (IB) for
various fixed levels of VCE as
shown in Fig. 2.18. The
common-emitter current
gain characteristics, can be
obtained experimentally or
derived from the output
characteristics.
Figure 2.18 The common-emitter current gain characteristics
for a BJT
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2.6 COMMON-COLLECTOR CHARACTERISTICS

Common-Collector Circuit

The circuit arrangement in Fig. 2.19 shows the BJT

collector terminal common to both input base-
collector voltage (VBC) and output emitter-
collector voltage (VEC), and this is suitable for
determining the common-collector characteristics.

This circuit is difficult to use because IB changes

each time VEC is adjusted. VEC variations affect IB, Figure 2.19 Circuit for determining BJT
and when a set of readings for the output common-collector characteristics.
characteristics is being taken, IB has to be
readjusted to its required (constant) level each time VEC is adjusted.

Common-Collector Input Characteristics

The common-collector input characteristics shown in

Fig. 2.20 are different from either common-base or
common-emitter input characteristics.

The difference is due to the fact that the input voltage

(VBc) is determined by the output voltage (VEC).
Referring to Fig. 2.19,

VEC = VEB + VBC

Or VEB = VEC – VBC

Increasing the level of VBC with VEC held constant

reduces the base-emitter voltage (VEB) and thus
reduces IB. This explains the slope of the CC input Figure 2.20 The common-collector
characteristics. input characteristics.

Output and Current Gain Characteristics

Typical representations of BJT common-collector output and current gain characteristics are
shown in Fig. 2.21. The output characteristics are a plot of the emitter current (IE) versus the
emitter-collector voltage (VEC) for several constant levels of base current (IB). The current gain
characteristics are IE plotted versus IB at constant VEC voltages.

The common-collector output and current gain characteristics are practically same as the common-
emitter circuit.

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Figure 2.21 The common-collector output and current-gain characteristics.

2.7 BJT BIASING: INTRODUCTION

Transistors used in amplifier circuits must be biased into an on state with constant (direct) levels
of collector, base, and emitter current, and constant terminal voltages. The levels of IC and VCE
define the transistor dc operating point, or quiescent point. The circuit that provides this state is
known as a bias circuit.

In practical circuits these quantities are affected by the transistor current gain (hFE) and by
temperature changes. The best bias circuits have the greatest stability; they hold the currents and
voltages substantially constant regardless of the hFE and variations in temperature.

2.8 DC LOAD LINE

The dc load line for a transistor circuit is a straight line drawn on the transistor output
characteristics.

For a common-emitter (CE) circuit, the load line is a graph of collector current (IC) versus collector-
emitter voltage (VCE), for a given value of collector resistance (RC) and a given supply voltage (Vcc).

The load line shows all corresponding levels of IC and VCE that can exist in a particular circuit.

Consider the common-emitter circuit in Fig. 2.22. The normal bias polarities for the transistor
junctions, terminal voltages are such that the base-emitter junction is forward-biased and the
collector-base junction is reverse-biased.

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Figure 2.22 Transistor circuit with Figure 2.23 DC load line drawn upon transistor
collector resistor Rc. common-emitter output characteristics.
The dc load line for the circuit in Fig. 2.22 is drawn on the device common-emitter characteristics
in Fig. 2.23.

From Fig. 2.22, the collector-emitter voltage is

VCE = (supply voltage) - (voltage drop across Re)

or VCE = Vcc – IcRc

If the base-emitter voltage (VBE) is zero, the transistor is not conducting and IC = 0. Substituting
the Vcc and Rc values,
VCE = 20V – ( 0 X 10kΩ)
= 20V
Plot point A on the common-emitter characteristics in Fig. 2.23 at IC = 0 and VCE = 20 V. This is one
point on the dc load line.

Now assume a collector current of 2mA, and calculate the corresponding collector-emitter voltage
level.
VCE = Vcc – IcRc

Rearranging the above equation IC = VCC / RC at VCE = 0V thus IC = 2mA.

Plot point B on Fig. 2.23 at VCE = 0 and IC = 2 mA. The straight line drawn through points A and B
is the dc load line for Rc = 10 kΩ and Vcc = 20 V.
If either of these two quantities is changed, a new load line must be drawn.
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2.9 DC BIAS POINT (Q-POINT)

The dc bias point or quiescent point (Q-point) (also known as the dc operating point) identifies the
transistor collector current and collector-emitter voltage when there is no input signal at the base
terminal. Thus, it defines the dc conditions in the circuit.

When a signal is applied to the transistor base, IB varies according to the instantaneous amplitude
of the signal. This causes IC to vary and consequently produces a variation in VCE.

Figure 2.24 Transistor Circuit with Figure 2.25 DC load line for transistor with a
a bias point (Q-Point) at VCE =10 V bias point (Q-point) at VCE = 10V and IC = 1 mA.
and IC= 1 mA.
Consider the circuit in Fig. 2.24 and the 10kΩ load line drawn for the circuit in Fig. 2.25. Assume
that the bias conditions are as identified by the Q-point on the load line,

IB = 20 μA, IC = 1 mA, and VCE = 10 V

When IB is increased from 20 µA to 40 µA, IC becomes approximately 1.95 mA and VCE becomes
0.5V, as illustrated at point C on the load line. The VCE change from the Q-point is

Δ VCE = 10 V – 0.5 V

= 9.5 V

So, increasing IB by 20 µA (from 20 µA to 40 µA) caused VCE to decrease by 9.5 V (from 10 V to

0.5V).

When IB is reduced from 20 µA to zero, IC goes down to approximately 0.05 mA, and VCE goes up to
19.5 V (point D on the load line in Fig. 5-5). So, the VCE change is
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Δ VCE = 19 .5 – 10 V
= 9.5V

Decreasing IC by 20 µA (from 20 µA to zero) caused VCE to increase by 9.5 V (from 10 V to 19.5 V).
It is seen that with the Q-point at IC = 1 mA and VCE = 10 V, an IB variation of ±20 µA produces a
collector voltage swing of ±9.5 V.

2.10 FIELD EFFECT TRANSISTORS: INTRODUCTION

A field effect transistor (FET) is a voltage-operated device that can be used in amplifiers and
switching circuits. A FET requires virtually no input current. This gives it an extremely high input
resistance, which is its most important advantage over a BJT. There are two major categories of
field effect transistors: junction FET and MOSFET. These are further subdivided into p-channel and
n-channel devices.

2.11 JUNCTION FIELD EFFECT TRANSISTORS

n-Channel JFET

Construction: The operating principle of an n-channel junction field effect transistor (JFET) is
illustrated by the block representation in Fig. 2.26a. A piece of p-type semiconductor material,
referred to as the channel, is sandwiched between two smaller pieces of p-type (the gates). The
ends of the channel are designated the drain (D) and the source (s), and the two pieces of p-type
material are connected together and their terminal is named the gate (G).

Working: With the gate left unconnected and a drain-source voltage (VDS) applied (positive at the
drain, negative at the source), a drain current (ID) flows, as shown in Fig. 2.26a.

When a gate-source voltage (VGS) is applied with the gate negative with respect to the source as
shown in Fig.2.26b, the gate-channel pn-junctions are reverse biased. The channel is more lightly
doped than the gate material, so the depletion regions penetrate deep into the channel. Because
the depletion regions are regions depleted of charge carriers, they behave as insulators. The result
is that the channel is narrowed, its resistance is increased, and ID is reduced.

Figure 2.26 A n-channel JFET consists of an n-type channel with p-type gate regions on each side.
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When the negative gate-source bias voltage is further increased, the depletion regions meet at the
centre of the channel as shown in Fig. 2.26c, and ID is cut off.

The name field effect transistor is because, the depletion regions in the channel are produced by
the electric field at the reverse biased gate-channel junctions.

The term unipolar device is sometimes applied to a FET, because, the current consists of only one
type of charge carrier (majority charge carriers): electrons in the case of an n-channel device.

Circuit symbols for an n-channel JFET are shown in Fig. 2.27. As in the case of all semiconductor
device symbols, the arrowhead points from p-type to n-type. For an n-channel device, the
arrowhead points from the p-type gate to the n-type channel. This is the direction of current flow
if the junctions become forward biased. Some device manufacturers use the symbol in Fig. 2.27a
with the gate directly opposite the source terminal. Others show the gate centralized between the
drain and source (Fig. 2.27). This can sometimes make circuit diagrams confusing unless the drain
and source terminals are clearly identified. The symbol in Fig. 2.27c is used when the terminals of
the two gate regions are provided with separate connecting leads. In this case, the device is referred
to as a tetrode-connected FET.

Figure 2.27 Circuit symbols for an n-channel JFET.

p-Channel JFET

In a p-channel JFET, shown in block form in Fig. 2.28a, the channel is a p-type semiconductor, and
the gates are n-type. The drain-source voltage (VDS) is applied negative to the drain and positive to
the source, as illustrated, and the drain current flows (in the conventional direction) from source
to drain.

To reverse-bias the gate-channel junctions, the n-type gate regions must be made positive with
respect to the p-type channel. So the bias voltage is applied positive on the gate terminals and
negative on the source.

A positive-going signal at the gate terminal of a p-channel JFET increases the gate-channel junction
reverse bias, causing the depletion regions to penetrate further into the channel. This increases the
channel resistance and decreases the drain current. Conversely, a negative-going signal narrows
the depletion regions, reduces the channel resistance, and increases the drain current.

Circuit symbols for a p-channel JFET are shown in Fig. 2.28b. The arrow- heads again point from
the p-type material to the, n-type, in this case, from the p-type channel to the n-type gate.

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Figure 2.28 A p-channel JFET.

JFET Fabrication

Junction field-effect transistors are normally manufactured by the diffusion process. This type of
construction is illustrated in Fig. 2.29. Starting with a p-type substrate, an n-channel is diffused;
then, p-type impurities are diffused into the channel. Finally, metal terminal connections are
deposited through holes in the silicon dioxide surface, as illustrated.

The n-type region is the FET channel, and the two p-type regions constitute the gates. With this
symmetrical construction, the drain and source terminals are interchangeable.

Other fabrication techniques produce device geometry that is not symmetrical. In these cases,
interchanging the drain and source terminals would radically affect the performance of the device.

Figure 2.29 Cross-section and top view of n-channel JFET.

Depletion regions

An n-channel JFET block representation is shown in Fig. 2.30. With a drain-source voltage applied
as illustrated, ID flow in the direction shown, producing voltage drop along the channel. Consider
the voltage drops from the source (S) terminal to point A, B and C within the channel.
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Point A is positive with respect to the source; that is S is

negative with respect to A. Because the gate blocks are
connected to S, the gates are negative with respect to
point A by a voltage VA. This cause the depletion regions
to penetrate into the channel by an amount proportional
to VA.

The voltage drop between point B and the source is VB,

which is less than VA. Consequently, at point B on the
channel the gates are at –VB with respect to the channel,
and the depletion region penetration is less than at point
A.

From point C to the source terminal, the voltage drop (Vc)

is less than VB. Thus, the gate-channel reverse bias (at
point C) is VC volts, and the depletion region penetration
is less than at points A or B.
Figure 2.30 Drain current in an n-
The differing voltage drops along the channel, and the channel JFET causes voltage drops
resulting variation in gate-channel reverses bias, account along the channel which reverse-
for the shape of the depletion region penetration of the bias the gate channel junctions.
channel.

2.12 JFET CHARACTERISTICS

n-Channel JFET Characteristics

Drain Characteristics with VGS = 0

Figure 2.31 Circuit for obtaining

the ID/VDS characteristic for an n-
channel junction field effect
transistor with VGS = 0. Figure 2.32 ID/VDS characteristic for an n-channel JFET
with VGS = 0.

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• Figure 2.31 shows a circuit for determining the drain-current versus drain-source voltage
characteristic for an n-channel JFET with VGS = 0. VDS is increased in steps from zero, and ID is
measured at each VDS level. This produces ID/VDS values for plotting the characteristic shown
in Fig. 2.32.
• Referring to the characteristic, it is seen that when VDS = 0, ID = 0. There is no channel voltage
drop, and so the voltage between the gate and all points on the channel is zero, and there is no
depletion region penetration.
• When VDS is increased by a small amount (less than 1 V), a small drain current flows, producing
some voltage drop along the channel. This results in some depletion penetration of the channel,
but it is so small that it has no significant effect on the channel resistance.
• With further small increases in VDS, the drain current increase is linear and the channel behaves
as an almost constant-value resistance.
• The channel continues to behave as a fixed-value resistance until the voltage drops along it
become large enough to produce considerable depletion region penetration. At this stage the
channel resistance begins to be affected by the depletion regions.
• Further increases in VDS now produce smaller ID increases, as shown by the curved part of the
characteristic.
• The increased ID levels, in turn, cause more depletion region penetration and greater channel
resistance. Finally, a saturation level of ID is reached where further VDS increase seems to have
no effect on ID.
• At the point on the characteristic where ID levels off, the drain current is referred to as the
drain-source saturation current (IDSS) (10 mA in Fig. 2.32).
• The region of the characteristic where ID is constant is called the pinch-of region.
• The channel mostly behaves like a resistance between the points where VDS = 0 and VDS = Vp;
so this part of the characteristic is referred to as the channel ohmic region.
• If VDS is continuously increased (in the pinch-off region), a voltage is reached at which the
(reverse-biased) gate-channel junction break down.
When this happens, ID increases rapidly and the
device may be destroyed.
• The pinch-off region of the characteristic is the
normal operating region for the FET.

Drain Characteristics with External Bias

A circuit for obtaining the ID/ VDS characteristics for an n-

channel JFET when an external gate-source bias (VGS) is
applied is shown in Fig. 2.33. Figure 2.33 Circuit for obtaining
In this case, VGS is set to a convenient (negative) level the ID/ VDS characteristic for an n-
(such as –1 V). VDS is increased in steps, and the channel junction field effect
corresponding level of ID, is noted at each VDS step as transistor with various gate-source
illustrated in Fig. 2.34. bias voltages.
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Figure 2.34 ID/ VDS characteristic for VGS = 0 and VGS = – 1V for an n-channel JFET

When a –1 V external gate-source bias voltage is applied, the gate-channel junctions are reverse
biased even when ID = 0. So when VDS = 0, the depletion regions are already penetrating to some
depth into the channel.

Because of this, a smaller voltage drop along the channel will increase the depletion regions to the
point at which they produce channel pinch-off. Consequently, when VGS = – 1 V the pinch-off
voltage is reached at a lower ID level than when VGS = 0. The VGS =- 1 V characteristic in Fig. 2.34
has Vp = 3.5 V.

The drain characteristics can be

obtained for several level of
negative gate-source bias
voltage as shown in Fig. 2.35.

Figure 2.35 ID/ VDS

characteristics for an n-channel
JFET with various levels of VGS.

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When VGS = 0, ID saturates at IDss, and the characteristic shows Vp = 4.5 V. When a -1 V external
bias is applied, the gate-channel junctions require -3.5 V to achieve pinch-off. This means that a
drop of 3.5 V instead of 4.5 V is now required along the channel, and the lower voltage drop is
achieved with a lower ID. Similarly, when VGS = -2 V and -3 V, pinch-off is achieved with 2.5 V and
1.5 V respectively, along the channel.

The drain-source voltage at which breakdown occurs is reduced as the negative gate-source bias
voltage is increased. This is because – VGS adds to the reverse bias at the junctions.

If a positive VGS is used, a higher level of ID can be produced, as shown by the characteristic for VGS
= +0.5 V. However, VGS is normally kept negative to avoid the possibility of forward-biasing the
gate-channel junctions.

Transfer Characteristics

Figure 2.36 The transfer characteristics for a FET are a plot of IDS versus VGS.

The transfer characteristics for an n-channel JFET are a plot of IDS versus VGS. The gate-source
voltage of an FET control the levels of the drain current as shown in Fig. 2.36a.

Figure 2.36b shows a circuit for determining the transfer characteristics of a given FET. The drain
source voltage is maintained constant, VGS is adjusted in the corresponding level of VGS and ID are
recorded.

p-Channel JFET Characteristics

Figure 2.37 shows a circuit for obtaining the characteristics of a p-channel JFET. The direction of
the arrowhead in the FET symbol, and the drain current direction is reversed to the n-channel. The
drain terminal is negative with respect to the source, and the gate terminal is positive with respect
to the source.
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To obtain a table of quantities for plotting a drain

characteristic, VGS is maintained constant at the
desired (positive) level, – VDS is increased in steps
from zero, and the ID levels are noted at each step.

Typical p-channel JFET drain characteristics and

transfer characteristics are shown in Fig. 2.38.

Figure 2.37 Circuit for determining the

characteristics of a p-channel JFET.

Figure 2.38 Transfer and drain characteristics for ap-channel JFET.

When VGS = 0, IDSS = 15 mA, and more positive level of VGS reduce ID toward cutoff VGS(off) = +6 V.
Using VGS of –0.5 V produces a higher ID than when VGS = 0. Here, forward bias at the gate-channel
junction should be avoided.

2.13 ENHANCEMENT MOSFET

Figure 2.39 shows the construction of a metal oxide

semiconductor FET (MOSFET), also known as an insulated gate
FET. Starting with a high-resistive p-type substrate, two blocks
of heavily-doped n-type material are diffused into the
substrate, and then the surface is coated with a layer of silicon
dioxide. Holes are cut through the silicon dioxide to make
contact with the n-type blocks. Figure 9-29 Metal oxide
semiconductor FET
(MOSFET) construction.
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Metal is deposited through the holes for source and drain terminals, as illustrated, and a metal plate
is deposited on the surface area between drain and source, this plate functions as a gate.

Working: Consider the situation illustrated in Fig. 2.40a. The drain terminal of the MOSFET is
positive with respect to the source, and the gate is open-circuited.

Figure 2.40 Effect of +VDS on the MOSFET with the gate terminal open-circuited and with +VGS
applied to the gate.

The two n-type blocks and the p-type substrate form back-to-back pn-junctions connected by the
resistance of the p-type material, as illustrated. The pn-junction close to the drain terminal is
reverse biased, so that only a very small (reverse-leakage) current flows from D to S.

Now if the source terminal is connected to the substrate and that a positive gate voltage is applied,
as shown in Fig. 2.40b. Negative (minority) charge carriers within the substrate are attracted to
the (positive) plate that constitutes the gate. Since these charge carriers (electrons) cannot cross
the silicon dioxide to the gate, they accumulate close to the surface of the substrate, as shown. The
minority charge carriers constitute an n-type channel between drain and source, and as the gate-
source voltage is made more positive, more electrons are attracted into the channel, causing the
channel resistance to decrease. A drain current flows along the channel between the D and S
terminals, and because the channel resistance is controlled by the gate-source voltage (VGS), the
drain current is also controlled by VGS. The channel conductivity is said to be enhanced by the
positive gate-source voltage, and so the device is known as an enhancement mode MOSFET
(EMOSFET or EMOS transistor).

Characteristics: Typical drain and transfer characteristics for an n-channel EMOS device are shown
in Fig. 2.41. Note that on both characteristics the drain current increases as the positive gate-source
bias voltage is increased. Because the gate of the MOSFET is insulated from the channel, there is no
gate-source leakage current and the device has an extremely high (gate) input resistance: typically
1015 Ω or greater.

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Figure 2.41 Typical drain and transfer characteristics for an n-channel EMOS transistor.

Two graphic symbols for the n-channel EMOS transistor

are shown in Fig. 2.42. One symbol shows the source and
substrate connected internally, while the other has a
separate substrate terminal. The line representing the
device channel is broken into three sections to indicate
that the channel does not exist until an appropriate gate
voltage is applied. To show that the device has an
insulated gate, the gate symbol does not make direct Figure 2.42 Circuit symbols for an
contact with the channel. The arrowhead points from the n-channel EMOSFET.
p-type substrate to the n-type channel.

A p-channel EMOS transistor is constructed by starting with an n-type substrate and diffusing p-
type drain and source blocks, as illustrated in Fig. 2.43a. The device characteristics are similar as
n-channel EMOS transistor, except that all voltage polarities and current directions are reversed.
The drain-source voltage is negative, and a negative gate-source voltage is required to create the
p-type channel. The arrowheads in the circuit symbols are also reversed (see Fig. 2.43b).

Figure 2.43 Construction and circuit symbol for a p-channel EMOSFET.

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2.14 DEPLETION-ENHANCEMENT MOSFET

Construction: The device cross-section shown in Fig. 2.44a.

Starting with a high-resistive p-type substrate, two blocks of heavily-doped n-type material are
diffused into the substrate, and then the surface is coated with a layer of silicon dioxide. Holes are
cut through the silicon dioxide to make contact with the n-type blocks.

This has a lightly doped n-type channel between the drain and source blocks.

Metal is deposited through the holes for source and drain terminals, as illustrated, and a metal plate
is deposited on the surface area between drain and source, this plate functions as a gate.

Figure 2.44 n-Channel depletion-enhancement MOSFET

Working: When a positive drain-source voltage (VDS) is applied, a drain current (ID) flows even
when the gate-source voltage (VGS) is zero. If a negative VGS is applied, as shown in Fig. 2.44b, some
of the negative charge carriers are repelled from the gate and driven out of the n-type channel. This
creates a depletion region in the channel, as illustrated, causing an increase in channel resistance
and a decrease in drain current. The effect is similar to that in an n-channel JFET. Because of the
channel depletion regions, the device can be termed a depletion-mode MOSFET.

When a positive gate-source voltage is applied, additional n-type charge carriers are attracted from
the substrate into the channel, decreasing its resistance and increasing the drain current. So the
depletion-mode MOSFET can also be operated as an enhancement-mode device. Thus, these
devices can be referred to as depletion-enhancement MOSFETs or DE-MOSFETs; however, the term
DMOSFET is normally applied.

Characteristics: Typical drain and transfer characteristics for a DMOSFET are shown in Fig. 2.45.
The device operates in the depletion mode when VGS is negative, and in the enhancement mode
when positive levels of VGS are used.

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Figure 2.45 Drain and transfer characteristics for an n-channel depletion-enhancement MOSFET.

The circuit used for DMOSFETs has the line representing

the channel is made solid to show that a channel is
present when Substrate VGS = 0 as shown in Fig. 2.46.

Figure 2.46 Circuit symbols for an

n-channel depletion enhancement
MOSFET.

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