8085 MICROPROCESSOR

Short Notes — All Definitions

4-Mark Format | Two-Paragraph Prose Style

[Link]. 2nd Semester | MBB College | NEP-2020

Paper Code: MJDSC-IV / DSE-1202

Unit I + Unit II

36 Key Definitions • Exam-Ready • Flowing Paragraph Format

★ UNIT — I : Architecture, Registers, Instructions & Assembly
Language

#1 | 4 Marks Microprocessor

A microprocessor is a single integrated circuit (IC) that incorporates all the functions of a
central processing unit on a single silicon chip. It is capable of performing arithmetic, logical,
and control operations under the direction of a stored program. The Intel 8085 is an 8-bit
microprocessor introduced in 1977, equipped with a 16-bit address bus that allows it to
address up to 64 KB of memory, and it operates from a single +5V power supply.

The 8085 uses a multiplexed lower address and data bus on pins AD0–AD7 to reduce the
number of physical pins required on its 40-pin DIP package. It communicates with memory
and I/O devices through three buses — the address bus, data bus, and control bus — and it
contains an internal clock generator, interrupt control logic, and serial I/O capability, making it
a highly integrated and self-sufficient processing device for embedded and educational
applications.

#2 | 4 Marks Accumulator

The accumulator is a dedicated 8-bit high-speed register within the 8085 CPU, designated
as Register A, that stores intermediate arithmetic and logical results. It acts as a temporary
workspace for the Arithmetic Logic Unit (ALU); during a calculation, the accumulator typically
holds one operand, and once the operation is complete, it stores the final result.

This register is essential for efficiency because it reduces the need to constantly write data to
the slower main memory (RAM). In accumulator-based architectures like the 8085, the
destination for any calculation is implied, which allows for shorter and faster machine
instructions. By keeping the "running total" of operations in one place, the accumulator
streamlines complex tasks, and it also serves as the exclusive channel for all I/O operations
— data read via IN and sent via OUT passes through the accumulator — thus speeding up
overall processing.

#3 | 4 Marks General Purpose Registers

The general purpose registers of the 8085 microprocessor are six 8-bit registers — B, C, D,
E, H, and L — that are available to the programmer for temporary storage of data during
program execution. Unlike the accumulator, these registers do not participate directly in ALU
operations as primary operands, but they can be used as secondary sources or destinations
in data transfer and arithmetic instructions.

These six registers can also be organized into three 16-bit register pairs — BC, DE, and HL
— which are used by instructions that require a 16-bit operand or address. Among them, the
HL pair holds a special role as the primary memory pointer: whenever the symbol M appears
in an instruction, it refers to the memory location whose address is currently stored in the HL
pair. For instance, the instruction MOV A, M loads the accumulator with the byte stored at the
memory address pointed to by HL, making the HL pair indispensable for indirect memory
access.

#4 | 4 Marks Program Counter (PC)

The Program Counter (PC), also known as the instruction pointer, is a vital 16-bit register in
the 8085 CPU that tracks the memory address of the next instruction to be executed. It acts
as a "pointer" that guides the processor through a program's sequence. As soon as an
instruction is fetched from memory, the PC is automatically updated — usually by
incrementing its value — to point to the next instruction in the sequence, ensuring the CPU
always knows where to go next.

While it typically moves through memory linearly, the PC can be modified by jump or branch
instructions, allowing the program to skip sections or loop back to previous code. When a
CALL instruction is executed, the current value of PC is saved to the stack so that execution
can return to the correct location after the subroutine finishes. After a hardware reset, PC is
initialized to 0000H, so the processor always begins execution from memory address 0000H.
By managing this flow, the Program Counter is essential for the orderly execution of software
and the handling of complex logical structures within a computer system.

#5 | 4 Marks Stack Pointer (SP)

The Stack Pointer (SP) is a 16-bit special-purpose register in the 8085 microprocessor that
always holds the memory address of the current top of the stack. The stack is a reserved area
in RAM that operates on the Last In, First Out (LIFO) principle — the most recently stored
item is the first to be retrieved. The programmer must initialize the stack pointer before using
the stack, typically using an instruction such as LXI SP, 2500H.
The stack pointer is automatically adjusted with each PUSH and POP operation. During a
PUSH, the SP is first decremented by 2 and the register pair's contents are then stored at that
address. During a POP, the data is read from the address in SP and SP is subsequently
incremented by 2. Beyond explicit PUSH and POP instructions, the stack pointer is also used
implicitly by CALL and RET instructions to save and restore the Program Counter, making the
stack pointer central to subroutine management and interrupt handling in the 8085.

#6 | 4 Marks Instruction Register (IR)

The Instruction Register (IR) is an 8-bit internal register of the 8085 microprocessor that
temporarily holds the opcode of the instruction currently being executed. Unlike general
purpose or special purpose registers, the instruction register is not directly accessible by the
programmer — it is entirely managed by the CPU's internal control logic.

When the CPU fetches an instruction from memory, the opcode byte is automatically loaded
into the instruction register. The Instruction Decoder, which is connected to the output of IR,
reads and interprets this opcode and generates the corresponding control signals that direct
the ALU, register file, and buses to carry out the required operation. This separation between
fetching (loading IR) and decoding (reading IR) forms the foundation of the
fetch-decode-execute cycle, which governs the sequential execution of every instruction in the
8085.

#7 | 4 Marks Flag Register / Status Flags

The flag register, also called the condition code register or status register, is an 8-bit register
in the 8085 that contains five condition flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity
(P), and Carry (CY). These flags are automatically set to 1 or reset to 0 by the ALU after
executing arithmetic and logical instructions, reflecting specific characteristics of the result.

Each flag serves a distinct purpose: the Sign flag indicates whether the result is negative
(MSB = 1); the Zero flag is set when the result is exactly 00H; the Auxiliary Carry flag records
a carry from bit 3 to bit 4, used primarily for BCD arithmetic with the DAA instruction; the Parity
flag is set when the result contains an even number of 1-bits; and the Carry flag is set when
there is a carry out of or a borrow into bit 7. These flags are directly used by conditional jump
instructions such as JZ, JC, and JP to control the flow of the program.

#8 | 4 Marks Parity Flag

The Parity flag is bit D2 of the 8085 flag register. It is automatically set to 1 when the result of
an arithmetic or logical operation contains an even number of 1-bits (even parity), and it is
reset to 0 when the result contains an odd number of 1-bits. For example, if the result is
11000011B, which contains four 1-bits, the parity is even and therefore P = 1.

The parity flag has its origins in communication systems, where parity checking is a basic
error-detection technique — a sender and receiver agree on an even or odd parity convention,
and if the received data violates that parity, a transmission error is assumed. In the context of
the 8085, the parity flag allows the programmer to use conditional branch instructions like JPE
(Jump if Parity Even) and JPO (Jump if Parity Odd) to take different program paths based on
the parity of a computed result.

#9 | 4 Marks Assembly Language

Assembly language is a low-level symbolic programming language that uses

human-readable mnemonics to represent the machine-level instruction set of a specific
processor. Each mnemonic corresponds directly to one machine instruction — for example,
MOV represents a data copy operation, ADD represents addition, and JMP causes an
unconditional jump in program flow. Unlike machine language, which consists of raw binary or
hexadecimal codes, assembly language makes programs significantly easier for humans to
read and write.

Despite being more readable than machine code, assembly language remains
machine-dependent, meaning a program written for the 8085 cannot be directly run on an
ARM or x86 processor without rewriting. A program called an assembler is used to translate
the assembly source code into executable machine code. The primary advantages of
assembly language are its direct hardware access, minimal memory footprint, and fast
execution speed, which is why it is used in time-critical embedded applications, device
drivers, and boot-level code.

#10 | 4 Marks Assembler

An assembler is a system software program that translates an assembly language source

program — written using mnemonics, labels, and directives — into the equivalent machine
language (binary or hexadecimal opcodes) that the CPU can directly fetch and execute. The
assembler performs a one-to-one mapping between each mnemonic and its corresponding
opcode, distinguishing it from a compiler, which translates high-level language code into many
machine instructions.
In addition to translating mnemonics, the assembler resolves symbolic addresses (labels) to
actual numeric memory locations, evaluates constant expressions, and handles assembler
directives such as ORG (set origin address), EQU (define constant), DB (define byte), and
END (end of program). The output of the assembler is an object file or a hex file that can be
loaded into the microprocessor's memory. Common assemblers include NASM, MASM, and
TASM for x86, and dedicated assemblers for 8085-based educational systems.

#11 | 4 Marks Opcode and Operand

An opcode, short for operation code, is the portion of a machine instruction that specifies the
exact operation the CPU must perform. In the 8085, every instruction begins with a 1-byte
opcode — for example, 3AH is the opcode for the LDA (Load Accumulator Direct) instruction,
and 76H is the opcode for MOV M, A. The opcode is always placed in the first byte of the
instruction and is decoded by the Instruction Decoder to generate control signals.

An operand is the data, register, or memory address on which the operation specified by the
opcode is performed. An instruction may have zero operands (e.g., HLT, NOP), one operand
(e.g., MVI A, 25H — where 25H is the operand), or two operands (e.g., MOV A, B — where
both A and B are operands). Together, the opcode and its operands form a complete
instruction. Understanding both terms is fundamental to reading machine code listings and
writing assembly language programs.

#12 | 4 Marks Addressing Modes

An addressing mode defines the method by which the operand of an instruction is accessed
during execution. The 8085 microprocessor supports five addressing modes, each offering a
different trade-off between speed, flexibility, and code size. The Immediate mode includes the
data directly within the instruction (e.g., MVI A, 25H); the Register mode specifies a register
as the operand (e.g., MOV A, B); and the Direct mode includes the full 16-bit memory address
in the instruction (e.g., LDA 2050H).

The Register Indirect mode uses a register pair as a pointer to the actual memory location
containing the operand (e.g., MOV A, M uses HL as the address pointer), which is highly
useful for accessing arrays or data structures in memory. Finally, the Implicit or Inherent mode
does not need any specified operand because it is defined by the instruction itself (e.g., CMA
complements the accumulator; HLT stops the CPU). Each of these addressing modes plays a
role in determining the length of the instruction (1, 2, or 3 bytes) and the number of memory
accesses required during execution.
#13 | 4 Marks Instruction Format / Word Size Classification

The instruction format of the 8085 defines how an instruction is structured in memory,
consisting of an opcode byte followed by zero, one, or two operand bytes. Based on the total
number of bytes an instruction occupies, 8085 instructions are classified into three categories.
A 1-byte instruction contains only the opcode, with the source and destination registers
encoded within that single byte (e.g., MOV A, B = 78H; HLT = 76H).

A 2-byte instruction consists of the opcode in byte 1 and an 8-bit immediate value or I/O port
address in byte 2 (e.g., MVI A, 25H = 3E 25H; IN 07H = DB 07H). A 3-byte instruction uses
byte 1 for the opcode and bytes 2 and 3 for a 16-bit memory address or 16-bit data, stored in
little-endian order — low byte first, high byte second (e.g., LDA 2050H = 3A 50 20H; JMP
1500H = C3 00 15H). This classification directly determines how many memory cycles the
CPU requires to fully fetch the instruction.

#14 | 4 Marks MOV Instruction

The MOV instruction is a 1-byte data transfer instruction in the 8085 that copies the content
of a source register into a destination register, leaving the source unchanged. Its general
syntax is MOV r1, r2, where r1 is the destination and r2 is the source. The MOV instruction
does not affect any of the five status flags, and because both source and destination are
encoded within the single opcode byte, no additional bytes are required.

The MOV instruction also has two important variants involving memory. MOV r, M reads the
byte stored at the memory address currently held in the HL register pair and places it into
register r; for example, MOV A, M loads the accumulator with the byte at address HL.
Conversely, MOV M, r stores the content of register r into the memory location pointed to by
HL; for example, MOV M, B stores the value in B at address HL. The combination MOV M, M
is not a valid instruction. In total, the 8085 has 63 valid MOV instruction combinations covering
all register-to-register and register-to-memory transfers.

#15 | 4 Marks MVI Instruction

The MVI (Move Immediate) instruction is a 2-byte instruction in the 8085 that loads an 8-bit
constant value directly into a specified register or into the memory location pointed to by the
HL pair. The first byte is the opcode and the second byte is the 8-bit immediate data. Like
MOV, the MVI instruction does not affect any status flags. For example, MVI A, 25H has the
machine code 3E 25H and loads the value 25H into the accumulator.
MVI is primarily used to initialize registers with known constant values at the start of a
computation — for instance, MVI B, 30H sets up a counter or operand in register B, and MVI
M, 50H stores the value 50H at the memory address currently in HL without disturbing any
register. Its use of immediate addressing mode makes it one of the most common instructions
in 8085 programs, as programmers frequently need to load registers with fixed values before
performing arithmetic, loop control, or I/O operations.

#16 | 4 Marks LXI Instruction

The LXI (Load Register Pair Immediate) instruction is a 3-byte instruction in the 8085 that
loads a 16-bit immediate value directly into a register pair or the Stack Pointer. The first byte
is the opcode, the second byte is the low byte of the 16-bit data, and the third byte is the high
byte — following the little-endian storage convention. The available register pairs are B (for
BC), D (for DE), H (for HL), and SP (for the Stack Pointer). No flags are affected.

LXI is one of the most important 3-byte instructions because it is used to set up memory
pointers and initialize the Stack Pointer before a program begins using subroutines or the
stack. For example, LXI H, 2000H sets HL to 2000H (H = 20H, L = 00H), allowing subsequent
MOV M or LDAX-style instructions to access memory starting at 2000H; and LXI SP, 2500H
initializes the Stack Pointer to 2500H so that PUSH, POP, CALL, and RET instructions
function correctly. Its machine code for LXI H, 2000H is 21 00 20H.
★ UNIT — II : Interfacing, Interrupts, DMA, Data Transfer &
Advanced Architectures

#17 | 4 Marks Cache Memory

Cache memory is a small, extremely high-speed memory placed between the CPU and the
main memory (RAM) with the purpose of reducing the effective memory access time. It stores
copies of the data and instructions that have been recently or frequently accessed, based on
the principle of locality — programs tend to reuse recently accessed data (temporal locality)
and tend to access memory locations that are near previously accessed locations (spatial
locality).

When the CPU needs a piece of data, it first checks the cache. If the data is found — called a
cache hit — it is served at high speed without accessing the slower RAM. If the data is not in
the cache — a cache miss — the CPU fetches it from RAM and simultaneously stores a copy
in the cache for future use. Modern processors organize cache into levels: L1 cache is the
smallest and fastest and sits directly on the processor core; L2 cache is larger and slightly
slower; and L3 cache is the largest and shared among all cores. This hierarchy significantly
improves overall system performance at relatively low cost.

#18 | 4 Marks Interrupt

An interrupt is an asynchronous signal sent to the CPU by either hardware or software,

requesting the processor to temporarily suspend its current program and transfer control to a
special routine called the Interrupt Service Routine (ISR) or interrupt handler. Once the ISR
has finished handling the event, the CPU restores its saved state and resumes the interrupted
program exactly from where it left off. Interrupts are fundamental to responsive computing
because they eliminate the need for the CPU to continuously check (poll) peripheral devices.

The 8085 microprocessor supports five hardware interrupt pins in order of priority: TRAP
(highest, non-maskable), RST 7.5, RST 6.5, RST 5.5, and INTR (lowest, fully maskable).
Each maskable interrupt can be individually enabled or disabled using the SIM (Set Interrupt
Mask) instruction. When an interrupt is acknowledged, the CPU automatically pushes the
Program Counter to the stack and jumps to a predetermined vector address associated with
that interrupt, where the ISR is stored. This mechanism allows multiple I/O devices to share
the CPU efficiently without requiring dedicated polling loops.
#19 | 4 Marks TRAP Interrupt

The TRAP interrupt is the highest priority and only truly non-maskable hardware interrupt in
the 8085 microprocessor. It cannot be disabled by the programmer under any circumstances
— neither the DI (Disable Interrupt) instruction nor the SIM (Set Interrupt Mask) instruction
has any effect on it. This ensures that TRAP will always be acknowledged regardless of the
current state of the interrupt system, making it the most reliable emergency interrupt.

When the TRAP pin is activated, the CPU completes its current machine cycle, saves the
Program Counter to the stack, and unconditionally jumps to its fixed vector address at 0024H,
where the ISR for the TRAP condition must be stored. TRAP is both edge-triggered and
level-triggered, meaning it requires a rising edge followed by a sustained high level to be
recognized, which prevents spurious triggering from glitches. It is typically used to handle
catastrophic events such as power failure detection, where the system must immediately save
critical data regardless of what the CPU was doing.

#20 | 4 Marks RST 7.5, RST 6.5, RST 5.5 Interrupts

RST 7.5, RST 6.5, and RST 5.5 are three maskable hardware interrupt pins in the 8085,
ranked in priority order just below TRAP. RST 7.5 is the highest of the three (priority 2) and is
unique in being edge-triggered — it has an internal flip-flop that latches the interrupt request
even if the signal is removed before the CPU can acknowledge it, and it directs execution to
vector address 003CH. RST 6.5 (priority 3) and RST 5.5 (priority 4) are both level-triggered,
requiring the pin to remain HIGH until acknowledged; they jump to 0034H and 002CH
respectively.

All three interrupts can be individually masked or unmasked using the SIM instruction, and
they can all be globally disabled using the DI instruction and re-enabled with EI. Because RST
7.5 is edge-triggered, a pending RST 7.5 request can be cleared explicitly using the SIM
instruction (by setting the RST 7.5 reset bit), whereas RST 6.5 and RST 5.5 automatically
clear when their input signals go low. This distinction makes RST 7.5 more suitable for events
that occur as brief pulses, while RST 6.5 and RST 5.5 are better suited for sustained signal
conditions.

#21 | 4 Marks INTR Interrupt

The INTR (Interrupt Request) is the lowest priority and most flexible of the five hardware
interrupts in the 8085 microprocessor. It is a level-triggered, maskable interrupt that can be
enabled by the EI (Enable Interrupt) instruction and disabled by the DI (Disable Interrupt)
instruction. Unlike the RST-type interrupts, INTR does not have a fixed vector address built
into the 8085.

Instead, when INTR is asserted and acknowledged, the CPU sends an active-low INTA
(Interrupt Acknowledge) signal to the external device. In response, the external hardware —
typically a Programmable Interrupt Controller like the 8259A — places a RST instruction or a
CALL instruction on the data bus, which directs the CPU to the appropriate ISR address. This
external configuration mechanism makes INTR highly versatile, allowing it to serve up to 8
different interrupt sources when combined with an 8259A, or a single device in simpler
configurations. Because the CPU automatically disables further interrupts upon
acknowledgment, the ISR must include an EI instruction if nested interrupts are needed.

#22 | 4 Marks Software Interrupt

A software interrupt is an interrupt generated by the execution of a special instruction within

the program itself, rather than by an external hardware signal. In the 8085, software interrupts
are implemented through the RST (Restart) instructions: RST 0 through RST 7. Each RST
instruction causes the CPU to behave like an internal CALL instruction — it pushes the
current Program Counter value onto the stack and then jumps to a fixed vector address
specific to that RST number.

The vector addresses for the 8 RST instructions are spaced exactly 8 bytes apart in memory:
RST 0 → 0000H, RST 1 → 0008H, RST 2 → 0010H, and so on up to RST 7 → 0038H. Each
of these 8-byte blocks can either hold a short ISR directly or contain a JMP instruction that
redirects to a longer ISR elsewhere in memory. Software interrupts are frequently used to call
fixed monitor-program routines, implement system calls in operating systems, and create
breakpoints for debugging — they provide a structured way to jump to known locations
without hardcoding absolute addresses into the program.

#23 | 4 Marks SID and SOD

SID (Serial Input Data) is pin 5 of the 8085 microprocessor, dedicated to receiving serial data
one bit at a time from an external device. The level on the SID pin is read into bit D7 (the most
significant bit) of the accumulator when the programmer executes the RIM (Read Interrupt
Mask) instruction. By repeatedly executing RIM and reading D7, software can reconstruct a
complete byte from a serial bit stream.

SOD (Serial Output Data) is pin 4 of the 8085, used to send serial data one bit at a time to an
external device. To transmit a bit, the programmer loads the desired bit value into the D7
position of the accumulator, sets bit D6 (SOE — SOD Output Enable) to 1, and then executes
the SIM (Set Interrupt Mask) instruction, which transfers D7 to the SOD pin. Both SID and
SOD together provide a simple, software-controlled serial communication interface, commonly
used to communicate with terminals, serial keyboards, or other TTL-level serial devices at low
baud rates.

#24 | 4 Marks Address Bus

The address bus is a group of 16 unidirectional signal lines (A0–A15) in the 8085 system that
carry the memory address or I/O port address from the microprocessor to memory chips and
I/O devices. Being unidirectional, information travels only outward from the CPU — the CPU
places an address on the bus and memory or I/O devices respond accordingly. With 16
address lines, the 8085 can uniquely address 2 to the power 16, which equals 65,536 distinct
memory locations, spanning from 0000H to FFFFH — a total of 64 KB.

In the 8085, the address bus is partially multiplexed: the upper 8 lines (A15–A8) are dedicated
address lines, but the lower 8 lines share their pins with the data bus (AD0–AD7). At the
beginning of each machine cycle, when the ALE (Address Latch Enable) signal is HIGH, the
AD0–AD7 lines carry the lower 8 bits of the address, which must be captured by an external
latch such as the 74LS373. Once ALE goes LOW, these same lines switch to carrying 8-bit
data. This multiplexing reduces the physical pin count of the IC while still providing full 16-bit
address capability.

#25 | 4 Marks Data Bus

The data bus is a group of 8 bidirectional signal lines (D0–D7) in the 8085 system that carry
data between the microprocessor, memory, and I/O devices. Being bidirectional, the data bus
allows information to flow in both directions: the CPU can read data from memory (memory →
CPU) during a fetch or load operation, and write data to memory or an I/O device (CPU →
memory/IO) during a store or output operation.
In the 8085, the lower 8 bits of the address are time-multiplexed with the data bus on pins
AD0–AD7. During the first phase of every machine cycle, when ALE is HIGH, these pins carry
the lower address byte (A7–A0). Once ALE goes LOW and the address has been latched
externally, the same pins switch role to carry the 8-bit data. The control signals RD (active
LOW — read) and WR (active LOW — write) indicate the direction of data flow on the bus for
each operation, and the IO/M signal distinguishes whether the transfer is with memory (IO/M
= LOW) or an I/O port (IO/M = HIGH).

#26 | 4 Marks READY and HOLD Signals

READY is an input signal to the 8085 microprocessor used to synchronize the CPU with slow
memory or I/O devices. When the READY line is held LOW by an external device, it signals to
the CPU that the memory or I/O is not yet prepared to complete the data transfer. In
response, the CPU automatically inserts one or more wait states (T-wait) — additional clock
cycles during which the buses are held stable — until READY goes HIGH, at which point the
transfer proceeds normally.

HOLD is an input signal used by a DMA controller or another bus master to request temporary
control of the system buses. When the HOLD pin is asserted HIGH, the CPU finishes its
current machine cycle and then responds by asserting HLDA (Hold Acknowledge) and
placing its address bus, data bus, and control bus in a high-impedance (tri-state) condition,
effectively disconnecting itself from the buses. The DMA controller then takes over these
buses to perform its direct memory transfers. Once the DMA operation is complete, it releases
HOLD, and the CPU reclaims control of all buses and resumes normal execution.

#27 | 4 Marks Synchronous Data Transfer

Synchronous data transfer is a method of communication between the CPU and an I/O
device in which data is exchanged at fixed, predetermined time intervals governed by a
common clock signal shared between the sender and the receiver. Because both devices are
clocked identically, no handshaking or status-checking signals are required — the transfer is
assumed to happen successfully at every defined clock interval.
This method is simple to implement and achieves high data transfer rates, but it depends
critically on both devices always being ready at the scheduled time. If the I/O device is slower
than the CPU and cannot keep up with the clock, data will be lost without any error indication.
For this reason, synchronous transfer is suitable only for high-speed devices that can
guarantee readiness at every clock cycle, such as synchronous DRAM (SDRAM), SPI (Serial
Peripheral Interface), and I2C buses. In the 8085 context, bus timing is inherently
synchronous — each machine cycle is precisely defined in terms of clock periods (T-states).

#28 | 4 Marks Asynchronous Data Transfer

Asynchronous data transfer is a method of communication between the CPU and an I/O
device that uses a handshaking protocol to coordinate each individual data transfer. Rather
than relying on a shared clock, the sender and receiver exchange control signals to confirm
readiness before every transaction. Typically, the I/O device asserts a STB (Strobe) signal to
indicate that data is ready, and the receiving side responds with an ACK (Acknowledge)
signal after successfully reading the data.

This approach allows devices of different speeds to communicate reliably without losing data,
since neither side proceeds until both sides are confirmed ready. However, asynchronous
transfer implemented via software polling — where the CPU repeatedly reads a status flag
(such as IBF — Input Buffer Full) to check device readiness — is inefficient because the CPU
is kept busy waiting and cannot perform other useful work during this time. This wasted CPU
time is known as busy-waiting or polling overhead, and it is the primary disadvantage of the
asynchronous polling method compared to interrupt-driven transfer.

#29 | 4 Marks Interrupt-Driven Data Transfer

In interrupt-driven data transfer, the CPU initiates an I/O operation and then immediately
continues executing its main program without waiting for the I/O device to become ready.
When the I/O device completes its operation or has data available, it sends an interrupt signal
to the CPU. The CPU then suspends its current task, saves its state (including registers and
the Program Counter) onto the stack, and jumps to the Interrupt Service Routine (ISR) to
perform the actual data transfer.
After the ISR completes the transfer and executes a RET instruction, the CPU restores its
saved state from the stack and resumes the main program exactly where it was interrupted.
This method is significantly more efficient than polling because the CPU is never idle — it
performs useful work between I/O events. However, each interrupt incurs an overhead of
saving and restoring context (typically several clock cycles), which makes interrupt-driven
transfer unsuitable for very high-speed transfers where the I/O events occur faster than the
CPU can handle the context-switching overhead. In such cases, DMA is preferred.

#30 | 4 Marks DMA (Direct Memory Access)

DMA (Direct Memory Access) is the fastest available method of transferring data between
an I/O device and memory, distinguished by the fact that it completely bypasses the CPU for
each byte of data transferred. Instead, a dedicated hardware chip called the DMA Controller
(DMAC) — the Intel 8237 in 8085-based systems — takes control of the system buses and
transfers data directly between the I/O device and memory without requiring the CPU to read
each byte and write it back.

The DMA process begins when the I/O device signals the DMAC that it is ready. The DMAC
then asserts the HOLD signal to the CPU; the CPU responds with HLDA and releases the
buses into a high-impedance state. The DMAC then drives the address bus, data bus, and
control bus to perform the transfer — reading from the I/O device and writing directly to
memory (or vice versa) at the full bus speed. Once all bytes have been transferred, the DMAC
releases HOLD, the CPU regains bus control, and resumes execution. DMA is essential for
high-throughput applications such as disk I/O, video frame buffering, and network packet
reception.

#31 | 4 Marks Intel 8237 — Programmable DMA Controller

The Intel 8237 is a Programmable DMA Controller (DMAC) designed to interface with the
8085 and 8086 microprocessors for high-speed data transfer between memory and I/O
devices without CPU intervention. It contains four independent DMA channels (Channel 0
through Channel 3), each with its own 16-bit Current Address Register, 16-bit Current Word
Count Register, Mode Register, and Request Register. This allows four separate devices to
be managed for DMA transfer simultaneously.
The 8237 supports four transfer modes: Single Transfer mode transfers one byte per DMA
cycle and releases the bus back to the CPU after each byte, allowing interleaved CPU and
DMA activity; Block Transfer mode transfers the entire programmed block without releasing
the bus until completion, offering maximum throughput; Demand Transfer mode continues
transferring as long as the device asserts DREQ and pauses whenever DREQ goes inactive;
and Cascade mode allows multiple 8237 chips to be cascaded together, expanding the
number of available DMA channels beyond four. The CPU programs the 8237 with the source
address, destination address, and byte count before initiating a DMA session.

#32 | 4 Marks CISC Architecture

CISC (Complex Instruction Set Computer) is a processor design philosophy in which the
CPU is equipped with a large and varied instruction set, where individual instructions can
perform multiple low-level operations — such as loading from memory, performing arithmetic,
and storing back to memory — all in a single instruction. CISC instructions are of variable
length and are implemented internally through a layer of microcode, which breaks each
complex instruction into simpler micro-operations.

The primary motivation for CISC was to reduce the number of lines a programmer needed to
write and to minimize the program size stored in memory, which was extremely expensive in
the early decades of computing. However, the variable instruction length and microcode
overhead make CISC processors difficult to pipeline efficiently, as the hardware cannot easily
predict instruction boundaries or execution times. Classic CISC examples include the Intel
8085, 8086, and the entire x86 family (Pentium, Core i-series, AMD Ryzen), all of which
maintain backward compatibility with thousands of instructions accumulated over decades.

#33 | 4 Marks RISC Architecture

RISC (Reduced Instruction Set Computer) is a processor design philosophy that prioritizes
simplicity and speed by using a small set of simple, uniform instructions that each execute in
exactly one clock cycle. All RISC instructions are fixed in length (typically 32 bits), which
makes it easy for the hardware to fetch, decode, and pipeline them efficiently. RISC
processors follow a load/store architecture, meaning only LOAD and STORE instructions
access memory, while all arithmetic and logical operations work exclusively on registers.
Because RISC instructions are simple and uniform, RISC CPUs can use a hardwired control
unit instead of microcode, which eliminates the decoding overhead and results in faster
execution. RISC processors also typically include a large register file (32 or more
general-purpose registers) to reduce the need for memory accesses. Although RISC
programs require more instructions than CISC programs to perform complex tasks, the
individual instructions execute faster and the deep pipelining more than compensates.
Prominent RISC examples include ARM (used in virtually all smartphones), MIPS (used in
routers and embedded systems), SPARC, PowerPC, and RISC-V.

#34 | 4 Marks Superscalar Architecture

Superscalar architecture is an advanced CPU design in which the processor contains

multiple independent functional units — such as integer ALUs, floating-point units, load/store
units, and branch units — that operate in parallel, enabling the CPU to execute more than
one instruction per clock cycle. This is achieved by exploiting Instruction-Level
Parallelism (ILP): the hardware dynamically identifies instructions that are independent of
each other and dispatches them simultaneously to different execution units.

A superscalar processor requires sophisticated hardware mechanisms to function correctly,

including an instruction fetch unit that can fetch multiple instructions per cycle, a dependency
checker that detects data hazards, an out-of-order execution engine that reorders
independent instructions, a register renaming unit to eliminate false dependencies, and a
branch predictor to speculatively fetch instructions beyond conditional branches. The Intel
Pentium was one of the first widely used superscalar processors with its dual integer
pipelines. Modern processors like Intel Core and AMD Ryzen are highly superscalar,
executing four to six instructions per clock cycle under ideal conditions.

#35 | 4 Marks Multicore Architecture

Multicore architecture is a processor design in which two or more independent and

complete CPU cores are fabricated on a single silicon chip. Each core is a fully functional
processor capable of fetching, decoding, and executing its own instruction stream
independently of the other cores, enabling true simultaneous parallel execution of multiple
software threads or processes. This is distinct from superscalar execution, which parallelizes
instructions within a single program stream.
In a multicore processor, each core typically has its own private L1 cache (and often L2
cache) for fast local access, while a larger L3 cache is shared among all cores to facilitate
efficient data sharing between threads. Multicore designs offer better performance per unit of
power consumption than a single very high-frequency core, because the power required by a
CPU scales roughly as the cube of its clock frequency, making moderate-speed multi-core
designs far more energy-efficient. Examples include Intel Core i7 (up to 24 cores), AMD
Ryzen 9 (16 cores), Apple M-series chips (8 heterogeneous cores), and Qualcomm
Snapdragon (heterogeneous [Link] cores for performance and efficiency).

#36 | 4 Marks Instruction Cycle

An instruction cycle is the complete sequence of operations that the CPU performs to fetch
one instruction from memory, decode it, and execute it. It is the fundamental repeating unit of
CPU operation — the processor continuously cycles through instruction cycles from the
moment it powers on until it halts. The instruction cycle is composed of a fetch phase, in
which the CPU places the Program Counter's address on the address bus, reads the opcode
from memory into the Instruction Register, and increments the PC; a decode phase, in which
the Instruction Decoder interprets the opcode; and an execute phase, in which the ALU or
registers carry out the specified operation.

The duration of an instruction cycle is measured in T-states, where one T-state equals one
period of the CPU's clock. Different instructions take different numbers of T-states: simple
register operations like MOV A, B take 4 T-states, while memory-accessing instructions like
LDA take 13 T-states. Each instruction cycle is further divided into machine cycles: a fetch
machine cycle retrieves the opcode, and additional memory read or write machine cycles
follow if the instruction has operands or requires memory access. The total execution time in
seconds = (number of T-states) × (clock period = 1 / clock frequency).