Mod N counter and freq
divider: h ps://[Link]/watch?v=KkvIuCcqydE&list=PLb2wGSuEdR
G8Aagvz-hdVUs-eYu0-n8Hu
QucikSilicon Verilog 21 Days of RTL: h ps://[Link]/course/21daysofrtl
They provide Solu on as well as the testbench.
I missed out to men on:
->For Asic Physical Design (VLSI) roles, they also check STA (Most imp), CMOS
Transfer curve, Short channel effects, transistor sizing, etc. VLSI syllabus of
Btech Sem 5 seemed good enough to prepare for it. So unless explicitly
specified that CMOS won't be tested in the interview, one cannot afford to not
brush it up.
Interview ques ons of Btech students :(Prathmesh Borse from Batch 24 had PD
type of ques ons) Google (Batch 25) asked CMOS to few students and RTL
Design to others.
->Fifo and comp arch ques ons were asked in each google RTL based
interview,
Vedan was asked Asynch FIFO depth calcula on ques on which is again a very
popular interview ques on: h ps://[Link]/watch?v= -lznkZN5Q
There are 2-3 more videos on depth calcula on in this playlist.
->Shreya Nahta was asked CMOS based ques ons, her interview exp document
seems very useful for ques ons on the CMOS side.
Feel free to reach out to me on my E-mail ID:
pujaradhyanik@[Link]
All the best!