Design of Basic Computer By Zaid Nashwan Computer Architecture 1

Instruction Register (IR)

CPU & Memory

IR OUTR TR
Read

3x8 Memory
ALU
Write
E
Decoder 4K x 16
Address LD LD LD
7 ... 2 1 15 0
D0 Bus System INR CLR CLK
AC
Clock CLK
D1 IR
D7 CONTROL MEMORY
L I C
Combinational Control UNIT 4096X16
I Control Logic Signals DR IR 15 0
T15
T1 L I C L
R T1
P B10
R T0 DR
T0

DR DR PC
PC TR
15 0
15 . . . 2 1
L I C L I C
4 x 16 TR
Decoder AR
OUTR LD INR LD INR CLR LD INR CLR ALU 11 0
CLR Clock Clock
Control Unit L I C L Clock 7 0 7 0
AR
OUTR INPR
4-bit Increment 7 1 2 3 4 5 6
11 0
Sequence T1 R
Clear
Counter D6 T5 R T0
PC
16-bit Common Bus
D5 T4
(SC) S0 S1 S2 15 0
Clock
Flag Unit
AC
T4 D4 T5 D5

DR(0)
P
T4 D0 T4 D1 T4 D2 T4 D6 T0 R T2 R
R’ i
M
D Q D Q FGO
AND T8' B10
C(0) D-FF D-FF
r B2 R’ T r B2 r B2 r B2 r B1 P B9 P B8
ADD
FA Clock Clock

C(0+1)
DR
LD

Notes
T0'

MEMORY
J Q AC(0)
INPR
INPR BIT(0)
T1'
T2' r D Q S
JK-FF J Q R
B0
p = D7 I T3
IEN
COM K FGi
FGO
JK-FF D-FF
R WR RD
CLOCK

r = D7 I T3
T1
SHR R
K Clock WR RD m
AC(0+1) T2

D3 R

m = D7 I T3
Clock T4
SHL T1
AC(0-1)
D5 D0

R = T0, T1, T2
P
P J Q IEN D Q FGI T4
T4
DR(1) B11
B7

JK-FF D-FF

R’ = T0, T1, T2
D6
T6 D1
AND B6

K Clock T4

‘ mean complement
C(1) R

T2 D2
ADD
FA Clock
T4

C(1+1)
DR
LD
r
B10
CLR
E
D3

T4
L= l , I = i
J Q AC(1) B8
CMP
INPR
INPR BIT(1) JK-FF

Flag Unit

sc
K
COM B7
Register Control Unit
CLOCK
B6
SHR LD
AC(1+1) D1 INR CLR
T5 Clock

SHL

AC
Clock
Bus Selection Truth Table
AC(1-1)
r
ALU
p
X1 S2
T5 T6
X2 S1
D2 D6
LD INR CLR
Encoder Bus T5 T5
D1 D5
Selection Bus Selection Unit
T5 T4
X7 S0 D4
D0
Clock
T2 T4
D5 R D3
DR(1)
T5 R’
T1
X1 r B11
AND r B5
D4 D7' AND
SHL
C(1) T4 D3 I ADD
T5 D0 SHR
T4 T3 DR
ADD COM
FA X4
R’ INPR
B10 D0
T0
p AND CMP SHR
C(1+1) P T4 X7 r m ADD INPR SHL
DR
DR
LD R D1
X2
AC(1) T0
J Q
INPR T4
INPR BIT(1) JK-FF R’
D5 X5
T2 D2
K T4
COM T4
R
CLOCK X6
D2 D6
T1 r
SHR T5
T4 D2 T5 B11 P B9 r B7 r B6
AC(1+1)
X3 i’ D7 T3 i D7 T3 i D7 T3
D0 T5 D1 T5
D6
SHL
T6
AC(1-1)