Silicon University

Silicon Hills, Patia, Bhubaneswar, Odisha

National Institute of Science and Technology

(Autonomous)
Computer Organization &
Architecture
Institute Park, Pallur Hills, Berhampur, Odisha
24/04/2026 Ranjit
Dr. Ranjit Kumar
Kumar Behera
Behera
[Link] 1
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Fundamental Concepts
• Processor fetches one instruction at a time and perform the
operation specified.

• Instructions are fetched from successive memory locations

until a branch or a jump instruction is encountered.

• Processor keeps track of the address of the memory

location containing the next instruction to be fetched using
Program Counter (PC).

• Fetched instructions are kept in Instruction Register (IR)

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Executing an Instruction
• Fetch the contents of the memory location pointed to by the
PC. The contents of this location are loaded into the IR
(fetch phase).
IR ← [[PC]]

• Assuming that the memory is byte addressable, increment

the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4

• Carry out the actions specified by the instruction in the IR

(execution phase).

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Executing an Instruction

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Processor Organization : Single Bus

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Executing an Instruction means
• Transfer a word of data from one processor register to
another or to the ALU. ( R1R0 or ALUR0 )

• Perform an arithmetic or a logic operation and store the

result in a processor register. ( ZALU )

• Fetch the contents of a given memory location and load

them into a processor register. (Memory Read)

• Store a word of data from a processor register into a given

memory location. (Memory Write)

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Register Transfers Internal processor
bus
R iin

Ri
When Riin=1, the data on the
bus are loaded into Ri R iout

Y in

When Riout=1, the content of Ri Y

are placed on the bus Constant 4

Select MUX

A B

1. Riin ,Riout
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
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Performing an Arithmetic or Logic Operation
• The ALU is a combinational circuit that has no internal
storage.

• ALU gets the two operands from MUX and bus. The result is
temporarily stored in register Z.

• What is the sequence of operations to add the contents

of register R1 to those of R2 and store the result in R3?

• R1out, Yin
• R2out, SelectY, Add, Zin
• Zout, R3in

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Fetching a Word from Memory (Read)
Address into MAR; issue Read operation; data into MDR.
Memory -bus
data lines MDRoutE

MDR inE
MDR
MDRout

MDRin

Figure 7.4. Connection and control signals for

Internal processor

gister
bus

re MDR.

• Move R2, (R1)

• MAR ← [R1]
• Start a Read operation on the
memory bus
• Wait for the MFC response from the
memory
• Load MDR from the memory bus
• R2 ← [MDR]

• Control Steps
• R1out,MARin,Read
• WMFC,MDRinE
• MDRout,R2in

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Writing a Word in Memory (write)
Address into MAR; issue Read operation; data into MDR.
Memory -bus
data lines MDRoutE

MDR inE
MDR
MDRout

MDRin

Figure 7.4. Connection and control signals for

Internal processor

gister
bus

re MDR.

• Move (R1),R2

• Control Steps
• R1out,MARin
• R2out,MDRin,Write
• MDRoutE,WMFC

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Execution of a Complete Instruction
• Add R1, (R3)

• Fetch the instruction

• Fetch the first operand (the contents of the memory location
pointed to by R3)
• Perform the addition
• Load the result into R1

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 MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R( n - 1)
control ALU
lines

Execution of a Complete Instruction

Carry -in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

Add R1, [R3]

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Multiple-Bus Organization

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Multiple-Bus Organization (cont.)
• A 3-bus organization is a CPU internal data transfer structure that
uses three separate buses (Bus A, Bus B, and Bus C) to allow
simultaneous transfer of two operands to the ALU and one result
back to registers. This improves speed compared to single or two-
bus systems.

• Bus A and Bus B (Input buses):

These buses carry two different operands from the register file (or
other sources like PC, constants, etc.) to the ALU inputs (A and B).
The register file typically has two read ports, enabling two registers
to be accessed at the same time.

• Bus C (Output bus):

This bus carries the result produced by the ALU back to the
register file or special registers (like PC, MAR, MDR). The register
file has a write port to store this result.

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Multiple-Bus Organization (cont.)
• ALU (Arithmetic Logic Unit):
Performs arithmetic or logical operations on the two inputs received from
Bus A and Bus B. The output is placed on Bus C.
• MUX (Multiplexer):
Selects between multiple sources (e.g., register value or constant like 4) to
feed into the ALU. This is useful for operations like PC increment (PC + 4).
• Register File:
A collection of general-purpose registers. It supports:
Two simultaneous reads (to Bus A and Bus B)
One write (from Bus C)
• PC (Program Counter) and Incrementor:
The PC holds the address of the next instruction. The incrementer
increases the PC (usually by 4), and the updated value can be sent via
buses.
• MAR (Memory Address Register) & MDR (Memory Data Register):
MAR holds the memory address for read/write operations.
MDR holds data being transferred to/from memory.

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Add R4, R5, R6

Control Sequences

Step Action

1 PC out
, R=B, MAR in
, Read, IncPC

2 WMF C

3 MDR outB
, R=B, IR in

4 R4 outA , R5 outB , SelectA, Add, R6 in , End

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Hardwired Control
Overview
• To execute instructions, the processor must have some
means of generating the control signals needed in the proper
sequence.

• Two categories: hardwired control and microprogrammed

control.

• Hardwired system can operate at high speed; but with little

flexibility.

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Control Unit Organization
CLK Control step
Clock
counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals
Hardwire Control Unit

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 CLK
Reset

Detailed Block Diagram

Clock Control step
counter

Step decoder

T 1 T2 Tn

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

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Generating Zin
Zin = T1 + T6 • ADD + T4 • BR + …

Branch Add

T4 T
6

T 1

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Microprogrammed Control
Overview: Microprogrammed Control

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Important Terms
• Control Word (CW):
✓ A control word is a word whose individual bits represents the various
control signals.
✓ Each of control steps in the control sequence of an instruction defines a
unique combination of 1’s and 0’s in the control word.

• Micro routine:
✓ A sequence of control words corresponding to the control sequence of an
machine instruction constitutes the micro routine for that instruction.

• Microinstruction:
✓ Individual control words in a micro routine are called microinstructions.

• Control Store/Control Memory

✓ The micro routines for all instruction in the instruction set of a computer
are stored in a special memory called control store/control memory.

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 Starting

Basic Organization of Microprogrammed Control

IR address
generator

Clock PC

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

One function cannot be carried

out by this simple organization.

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Organization of the control unit that allow conditional
branching in microprogram
External
inputs

Starting and
branch address Condition
IR codes
generator

The previous organization cannot

handle the situation when the
control unit is required to check the
Clock  PC status of the condition codes or
external inputs to choose between
alternative courses of action.

Control
store CW

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 THANK YOU

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