CAO – Module 3

Instruction Sets: Characteristics, Functions,

Addressing Modes & Formats

Computer Architecture & Organization · Complete Study Notes

■ TABLE OF CONTENTS
1. Machine Instruction Characteristics
2. Instruction Representation & Types
3. Types of Operands
4. Types of Operations
5. Transfer of Control (Branch / Skip / Procedure)
6. x86 & ARM Data Types and Operations
7. Addressing Modes
8. Datapath & Pipeline
9. Hardwired vs Microprogrammed Control
10. 8086 Assembly Language Programming

1. Machine Instruction Characteristics

The operation of the processor is determined by the machine instructions it executes. The complete set of
instructions a processor can execute is called its instruction set.

Elements of a Machine Instruction

Operation Code (Opcode) Specifies the operation to be performed (e.g., ADD, LOAD, STORE).

Source Operand The input(s) to the operation — can be in registers, memory, I/O, or immediate.
Reference

Result Operand Reference Where the result of the operation is stored.

Next Instruction Reference Tells the processor where to fetch the next instruction (usually implicit via PC).
Operand Locations
• Processor Register: Fast internal storage; each register has a unique name/number.
• Main / Virtual Memory: Address supplied in the instruction.
• I/O Device: Module + device specified; with memory-mapped I/O, treated as a memory address.
• Immediate: The operand value is embedded directly in the instruction field.

2. Instruction Representation & Types

Each instruction is a sequence of bits divided into fields matching its elements. Opcodes use symbolic
mnemonics in assembly language.

Common Mnemonics
ADD / SUB Add / Subtract two operands

MUL / DIV Multiply / Divide

LOAD Transfer data from memory to a register

STOR Transfer data from a register to memory

Number of Address Fields

Instructions can have 0 – 3 (or more) address fields. Fewer addresses mean longer programs but shorter
instructions.
• 3-address: opcode src1 src2 dest
• 2-address: opcode src dest (dest also used as one source)
• 1-address: opcode operand (accumulator implied as dest)
• 0-address: opcode only (stack machine — top of stack used)

3. Types of Operands

Numbers
• Binary Integer (Fixed-Point): Standard two's-complement integers.
• Binary Floating-Point: IEEE 754; limited precision and range.
• Packed Decimal (BCD): Each decimal digit stored in 4 bits; two digits per byte. Numbers built by stringing
4-bit codes, usually in multiples of 8 bits.

Characters
• IRA / ASCII: 7-bit code, most common worldwide (American Standard Code for Information Interchange).
• EBCDIC: Extended Binary Coded Decimal Interchange Code, used on IBM mainframes.
■ Text cannot be directly processed by binary-only circuits, hence encoding standards are essential.

Logical Data
An n-bit unit holding n 1-bit items. Each bit is independently 0 (false) or 1 (true).
• Efficient for storing Boolean arrays.
 • Used to manipulate individual bits (shift, mask, extract).
• Needed for software floating-point (shift significant bits) and IRA→packed decimal conversion.

4. Types of Operations

Data Transfer
Move data between registers, memory, and I/O. Must specify source, destination, and amount. Examples:
MOVE, LOAD, STORE, PUSH, POP, XCHG.

Arithmetic
ADD, SUB, MUL, DIV (signed integers; sometimes floating-point and decimal). Single-operand variants: ABS
(absolute value), NEG (negate), INC (+1), DEC (−1).

Logical
Bitwise AND, OR, NOT, XOR, and shift/rotate operations. Used for masking, setting/clearing bits, and testing
conditions.

Conversion
Change data type or representation — e.g., BCD↔binary, integer↔float.

Input / Output
Isolated programmed I/O, memory-mapped I/O, DMA, or I/O processor. Often only a few instructions; specific
actions set by parameters or command words.

System Control
Privileged instructions executed only in kernel mode: CPU reset, read/write control registers, halt.

Transfer of Control
Branch, skip, and procedure call — covered in detail in Section 5.

5. Transfer of Control
Transfer-of-control instructions are needed because:
• Each instruction may need to execute more than once (loops).
• Programs require decision making (conditional branches).
• Large programs are broken into reusable sub-routines (modularity).

Branch Instructions
A branch (or jump) instruction loads a new address into the PC. It can be unconditional (always branch) or
conditional (branch only if a flag is set, e.g., JZ — jump if zero, JC — jump if carry).

Skip Instructions
A skip increments the PC by an extra amount, causing the processor to skip the next instruction. Useful for short
conditionals without a separate label.

Procedure Call Instructions

A procedure (subroutine / function) is a self-contained block called from many places. Two instructions are
involved:
• CALL: Saves the return address (onto the stack or in a link register), then branches to the procedure.
• RETURN (RET): Restores the saved return address into the PC, resuming execution after the CALL.

■ Economy: one copy of code reused many times. Modularity: code broken into independent pieces.

x86 Procedure Support

CALL Pushes return address onto stack, then jumps to procedure.

ENTER Sets up a stack frame for the new procedure (pushes frame pointer, adjusts SP).

LEAVE Reverses ENTER — restores frame pointer and stack pointer.

RETURN Pops return address from stack and jumps to it.

6. x86 & ARM Data Types and Operations

x86 Data Types

• Byte (8-bit), Word (16-bit), Doubleword (32-bit), Quadword (64-bit).
• BCD and packed BCD formats for decimal arithmetic.
• Single-precision (32-bit) and double-precision (64-bit) IEEE 754 floating-point.

SIMD Extensions (MMX / SSE)

Introduced for multimedia performance. Operate on multiple data elements in parallel within wide registers.
• Packed byte / word / doubleword / quadword integer types.
• Packed single-precision and double-precision floating-point.
■ SIMD = Single Instruction, Multiple Data — one instruction processes several operands simultaneously.

x86 Register Set (8086)

CS — Code Segment Points to the memory segment holding program instructions.

DS — Data Segment Points to the segment holding frequently used data.

ES — Extra Segment Additional data segment, often used for string operations.

SS — Stack Segment Points to the stack segment used for function calls and local variables.

General Purpose 16-bit registers; each splits into high (AH,BH,…) and low (AL,BL,…) 8-bit halves.
AX,BX,CX,DX

Index Registers SI, DI Source Index and Destination Index; used in string and indexed addressing.

Pointer Registers SP, BP Stack Pointer and Base Pointer; used for stack frame management.

ARM Data Types

• ARM is a RISC architecture with load/store design — data processing only between registers.
• Supports 8-bit (byte), 16-bit (halfword), 32-bit (word) data.
 • Thumb and Thumb-2 instruction sets provide 16-bit compressed instructions for code density.

7. Addressing Modes
An addressing mode defines how the operand (or its address) is specified within an instruction.
Notation used: A = address field in instruction, R = register field, EA = effective address, (X) = contents of X.

Immediate
Effective Address EA = literal (operand IS the value)

Advantage No memory access for operand.

Disadvantage Value size limited by field width.

Example:
MOV AL, 25H ; AL ← 25H MOV BX, 1234H ; BX ← 1234H

Direct / Absolute
Effective Address EA = A (field holds address)

Advantage Simple, single memory access.

Disadvantage Limited address space.

Example:
MOV AX, [1234H] ; AX ← mem[1234H] MOV [2000H], DL ; mem[2000H] ← DL

Indirect
Effective Address EA = (A) (field→address of address)

Advantage Large address space (2^N).

Disadvantage Two memory accesses needed.

Example:
MOV SI, 2000H MOV AL, [SI] ; AL ← mem[mem[SI]]

Register
Effective Address EA = R (operand in register)

Advantage No memory access, very fast.

Disadvantage Limited number of registers.

Example:
MOV AX, BX ; AX ← BX SUB AX, BX
Register Indirect
Effective Address EA = (R) (register holds address)

Advantage One less memory ref than indirect.

Disadvantage Indirect via register, not memory.

Example:
MOV CL, [BX] ; CL ← mem[BX]

Displacement (Base + Offset)

Effective Address EA = A + (R)

Advantage Flexible; supports arrays, structs, segments.

Disadvantage Instruction must encode two fields.

Example:
MOV AL, [BX + 05H] ; base-register MOV AL, [SI + 10H] ; indexed

Based-Indexed
Effective Address EA = (BX) + (SI/DI)

Advantage Two registers combined — 2D data.

Disadvantage Complex calculation.

Example:
MOV AL, [BX + SI] ; EA = BX + SI

Implied
Effective Address Operand fixed by instruction

Advantage Very compact encoding.

Disadvantage No operand flexibility.

Example:
CLC ; clear carry flag HLT ; halt processor

Quick-Reference: Addressing Mode Summary

EA
Mode Example Instruction
Formula

operand =
Immediate MOV AL, 25H
A

Direct EA = A MOV AX, [1234H]

Indirect EA = (A) MOV AL, [SI] (after MOV SI, addr)

Register EA = R MOV AX, BX

Reg. Indirect EA = (R) MOV CL, [BX]

 EA = A +
Base + Offset MOV AL, [BX + 05H]
(R)

EA = A +
Indexed MOV AL, [SI + 10H]
(SI/DI)

EA = (BX)+
Based-Indexed MOV AL, [BX + SI]
(SI/DI)

fixed by
Implied CLC, HLT
opcode

8. Datapath & Pipeline

The hardware is organised into a 5-stage pipeline, each stage completing in one clock cycle:

Stage 1 — Fetch Instruction fetched from memory; placed in the Instruction Register (IR).

Stage 2 — Decode / Read IR decoded; source registers read from the Register File into RA and RB.

Stage 3 — Execute (ALU) ALU computes result (or effective address); output stored in RZ.

Stage 4 — Memory Memory accessed for Load/Store. MuxY selects data for RY.

Stage 5 — Write-Back Result in RY written to destination register in Register File.

Key Datapath Components

• RA, RB — Inter-stage registers holding source operand values.
• MuxB — Selects between register RB or immediate value for ALU input InB.
• RZ — Holds ALU result or computed effective address.
• RM — Holds data to be written to memory (Store instructions).
• RY — Final inter-stage register before write-back to register file.
• MuxY — Selects between RZ (ALU result) and memory data (Load) for RY.
• MuxC — Selects destination register address.
■ The Register File appears in both Stage 2 (as source) and Stage 5 (as destination).

9. Hardwired vs Microprogrammed Control

Hardwired Control
Control signals generated directly by combinational logic circuits. A step counter tracks which pipeline stage is
active (T1–T5). An instruction decoder interprets the opcode and asserts the corresponding INSi signal.
• Inputs to control signal generator: step counter output · IR opcode · ALU condition flags · external
interrupts.
• Advantage: Very fast — purely combinational logic.
• Disadvantage: Inflexible — changing the instruction set requires redesigning the hardware.

Microprogrammed Control
Control signals come from microinstructions stored in a Control Store (ROM/RAM). More flexible but slower
than hardwired.

Control Word A word whose individual bits represent the control signals for one step.

Microinstruction One control word — specifies all control signals for one clock cycle.

Micro-routine A sequence of microinstructions that implements one machine instruction.

Microprogram The complete collection of all micro-routines.

Control Store (CM) Special memory (ROM or RAM) holding the microprogram.

■ Key distinction: hardwired = fast, inflexible; microprogrammed = slower, easy to modify/extend.

10. 8086 Assembly Language Programming

Worked Examples
Example 1 — Compute A × B + C (A=4, B=3, C=5)
MOV AX, 4H ; AX = 4 (A) MOV BX, 3H ; BX = 3 (B) MUL BX ; AX = AX × BX = 12 ADD AX, 5H ; AX =
12 + 5 = 17 (C=5) MOV [1000H], AX ; store result at address 1000H

Example 2 — Compute (A + B) ÷ C (A=10, B=6, C=4)

MOV AX, 10D ; AX = 10 (A) ADD AX, 06D ; AX = 16 (A+B) MOV BX, 04D ; BX = 4 (C) DIV BX ; AX =
16 / 4 = 4 MOV [200H], AX ; store result

Example 3 — Compute A² + B² (A=3, B=4)

; ---- Compute A² ---- MOV AX, 3H MOV BX, 3H MUL BX ; AX = 9 MOV CX, AX ; save A² in CX ;
---- Compute B² ---- MOV AX, 4H MOV BX, 4H MUL BX ; AX = 16 ADD AX, CX ; AX = 9 + 16 = 25 MOV
[5000H], AX ; store result

Example 4 — Compute A − B + C × D (A=20, B=5, C=2, D=3)

; ---- Compute C × D ---- MOV AX, C ; AX = 2 MOV BX, D ; BX = 3 MUL BX ; AX = 6 MOV CX, AX ;
save C×D ; ---- Compute A − B ---- MOV AX, A ; AX = 20 SUB AX, B ; AX = 15 ; ---- Final sum
---- ADD AX, CX ; AX = 15 + 6 = 21 MOV [DI], AX ; store result

Data Transfer Instructions

MOV dst, src Copy src into dst. E.g. MOV AX, BX

XCHG dst, src Exchange values of dst and src.

PUSH src Decrement SP by 2, then write src to [SS:SP].

POP dst Read [SS:SP] into dst, then increment SP by 2.

Identify Addressing Mode — Practice List

Use the table below to identify the addressing mode for each instruction:

Instruction Mode Reasoning

MOV AX, 1234H Immediate Literal value in instruction

MOV AX, [1234H] Direct Explicit memory address

Register
MOV AL, [SI] EA = contents of SI
Indirect

Base+Displ
MOV AL, [BX+05H] EA = BX + 5
acement

MOV AL, [SI+10H] Indexed EA = SI + 10H

Based-Inde
MOV AL, [BX+SI] EA = BX + SI
xed

MOV AX, BX Register Both operands are registers

CLC Implied Operand fixed by opcode

■ Key Takeaways
Instruction Set Complete list of operations a CPU supports. Determines processor behaviour.

Operand Sources Registers (fastest) > Cache > Main Memory > I/O devices > Immediate.

Addressing Modes 8 main modes — trade-off between flexibility, code size, and speed.

Data Types Integer, floating-point, BCD, character (ASCII/EBCDIC), logical bits.

Control Transfer Branch (conditional/unconditional), Skip, Procedure Call/Return.

Datapath Stages Fetch → Decode → Execute → Memory → Write-Back (5-stage pipeline).

Hardwired Control Fast, inflexible combinational logic.

Microprogrammed Control Flexible, slower; microinstructions in Control Store.

SIMD MMX/SSE extensions process multiple data items with one instruction.