Bangalore Institute of Technology

(Affiliated to Visvesvaraya Technological University – VTU)

K. R. Road, V.V. Pura, Bengaluru – 560 004, India.

Dept. of Electronics Engineering (VLSI Design and Technology)

BVL613A-Low Power VLSI

Design

Dr Jalaja S
Associate Professor/EE (VDT)
Associate Dean, BIT
 COURSE OUTCOMES

Sl. Description Blooms

No. Level

CO1 Understand the impact of low power on system performance L2

CO2 Identify the mechanisms of power dissipation in digital IC systems. L3

CO3 Apply different circuit techniques to manage the low power L3

CO4 Analyze the functionality of Low- voltage low -power memories L4

Text Books:
1. Gray Yeap, Practical low power digital VLSI design, Springer, 1998
2. Kaushik Roy, Sharat C Prasad, Low power CMOS VLSI circuit design, Wiley India, 2000
3. P Rashinkar, Paterson and L. Singh, ―Low Power Design Methodologies‖, Kluwer Academic,
2002

REFERENCE BOOKS:
1. [Link] and J.H Lou, ―Low voltage CMOS VLSI Circuits‖, Wiley, 1999.
2. [Link] and [Link], ―Low power digital CMOS design‖, Kluwer,1995
3. Abdellatif Bellaouar, Mohamed I Elmasry, Low power digital VLSI design, Kluwer Academic,
1995
4. Anatha P Chandrakasan, Robert W Brodersen, Low power digital CMOS Design, Kluwer
Academic, 1995
5. Christian Piguet, Low power CMOS circuits, Taylor & Francis, 2006
6. Kiat Seng Yeo, Kaushik Roy, Low voltage, low power VLSI sub systems, Tata McGraw Hill, 2004
 Introduction
• Design for low power has become nowadays one of the major
concerns for complex, very-large-scale-integration (VLSI) circuits.
• Deep submicron technology, from 130 nm onwards, poses a new
set of design problems related to the power consumption of
the chip.
• Tens of millions of gates are nowadays being implemented on a
relatively small die, leading to a power density and total power
dissipation that are at the limits of what packaging, cooling,
and other infrastructure can support.
• As technology has shrunk to 90 nm and below, the leakage current
has increased dramatically, and in some 65-nm designs, leakage
power is nearly as large as dynamic power.
 Introduction
• So it is becoming impossible to increase the clock speed of
high-performance chips as technology shrinks and the chip
density increases, because the peak power consumption of
these chips is already at the limit and cannot be
increased further.
• Also, the power density leads to reliability problems
because the mean time to failure decreases with
temperature.
• Besides, the timing degrades and the leakage currents
increase with temperature.
 Introduction
• For battery-powered devices also, this high on- chip
power density has become a significant problem, and
techniques are being used in these devices from
software to architecture to implementation level to
alleviate this problem as much as possible like power
gating and multi- threshold libraries.

• Some other techniques being used nowadays are using

different supply voltages at different blocks of the design
according to the performance requirements, or voltage
scaling techniques
 Introduction
• Moreover, aggressive device size scaling used to achieve high
performance leads to increased variability due to short-channel
and other effects.
• This, in turn, leads to variations in process parameters such as, Leff,
Nch, W, Tox, Vt, etc.
• Performance parameters such as power and delay are
significantly affected due to the variations in process
parameters and environmental/ operational ( Vdd,
temperature, input values, etc.) conditions.
• For designs, due to variability, the design methodology in the
future nanometer VLSI circuit designs will essentially require a
paradigm shift from deterministic to probabilistic and statistical
design approach.
 Historical Background
• Moore’s law based on his famous prediction
 Historical Background
• Again after 30 years, Moore compared the actual performance
of two kinds of devices—random- access memories (RAM)
and microprocessors.
• Amazingly, it was observed that both kinds traced the slope
fairly closely to the revised 1975 projection.
• Moore’s law acted as a driving force for the spectacular
development of IC technology leading to different types of products
 Historical Background
• Evolution of IC Technology
 Historical Background
• Evolution tree of microprocessor. RISC reduced instruction set
computer, DSP digital signal processor
 INTRODUCTION
The VLSI low power design problems can be broadly classified into
two:
1) Analysis 2) Optimization
• Analysis problems are concerned about the accurate estimation
of the power or energy dissipation at different phases of the
design process.
• The purpose is to increase confidence of the design with the
assurance that the power consumption specifications are not
violated.
• Analysis techniques differ in their accuracy and efficiency.
 Why Low Power?
• Performance of a processor has been synonymous with circuit speed or
processing power, e.g., million instructions per second (MIPS) or million
floating point operations per second (MFLOPS).
• Power consumption was of secondary concern in designing ICs.
• However, in nanometer technology, power has become the most important issue
because of:
Increasing transistor count
Higher speed of operation Greater device
leakage currents
• Increased process parameter variability due to aggressive device
size scaling has created problems in yield, reliability, and testing.
• Power consumption is now considered one of the most important design parameters.
 Why Low Power?
• To remove the heat generated by the device, it is
necessary to provide suitable packaging and cooling
mechanism.
• There is an escalation in the cost of packaging and
cooling as the power dissipation increases.
• To make a chip commercially viable, it is necessary to
reduce the cost of packaging and cooling, which in turn
demands lower power consumption.
 Why Low Power?
• Increased customer demand has resulted in proliferation of hand- held, battery
operated devices such as cell phone, personal digital assistant (PDA), palmtop,
laptop, etc.
• The growth rate of the portable equipment is very high.
• Moreover, users of cell phones strive for increased functionality (as provided by smart
phones) along with long battery life.
• As these devices are battery operated, battery life is of primary concern.
• Unfortunately, the battery technology has not kept up with the energy
requirement of the portable equipment.
• Commercial success of these products depends on size, weight, cost, computing
power, and above all on battery life.
• Lower power consumption is essential to make these products commercially
viable.
 Why Low Power?
• It has been observed that reliability is closely related to the power
consumption of a device.
• As power dissipation increases, the failure rate of the device
increases because temperature-related failures start occurring
with the increase in temperature
 Why Low Power?
• It has been found that every 10 ºC rise in temperature roughly doubles the
failure rate.
• Lower power dissipation of a device is essential for reliable operation.
• According to an estimate of the US Environmental Protection Agency
(EPA), 80 % of the power consumption by office equipment is due to
computing equipment and a large part from unused equipment.
• Power is dissipated mostly in the form of heat.
• The cooling techniques, such as air conditioner, transfer the heat to the
environment.
• To reduce adverse effect on environment, efforts such as EPA’s Energy Star
program leading to power management standard for desktops and laptops has
emerged.
Sources of Power Dissipations
• POWER and ENERGY

• Power dissipation is measured commonly in terms of two

types of metrics:
• Types of Power Dissipations
• Static Power Dissipation
• Dynamic Power Dissipation
• Switching Power Dissipation
• Short-Circuit Power Dissipation
• Glitching Power Dissipation
 Power
Power is current times voltage – iV
There are two types of current that need to be considered
• Static
- Current caused by a resistor between the supply - nMOS style
circuits
- Current easy to estimate, V/R
• Dynamic
- Current used to charge and discharge capacitors
- Current depends on how often the capacitor changes state
- Dominant current in CMOS chips (sometimes only current)
 Sources of Power Dissipations
• Power Vs Energy

• Although power and energy are used interchangeably in many

situations.
• These two have different meanings and it is essential to
understand the difference between the two, especially in the case
of battery-operated devices.
• Power is the instantaneous power in the device, while energy is
the integration of power with time.
 Sources of Power Dissipations
• Power Vs Energy
 Sources of Power Dissipations
• Power dissipation is measured commonly in terms of two types of
metrics:
• 1. Peak power: Peak power consumed by a particular device is the
highest amount of power it can consume at any time. The high value
of peak power is generally related to failures like melting of some
interconnections and power-line glitches.
• 2. Average power: Average power consumed by a device is the mean
of the amount of power it consumes over a time period. High values
of average power lead to problems in packaging and cooling of VLSI
chips.
Sources of Power Dissipations
 Sources of Power Dissipations

Dynamic Power
• Dynamic power is the power consumed when the device is
active, that is, when the signals of the design are changing
values.
• It is generally categorized into three types: switching
power, short-circuit power, and glitching power
 Sources of Power Dissipations
• Dynamic Power-Switching Power
• The power required to charge and discharge the output
capacitance on a gate.
SWITCHING POWER FOR CHARGING A CAPACITOR.

Dynamic (Switching) Power.

GND-Ground
 Sources of Power Dissipations
• Dynamic Power-Switching Power
• The energy per transition is given by

Where CL is the load capacitance and Vdd is the supply voltage

Sources of Power Dissipations
• Dynamic Power-Switching Power
• Switching power is therefore expressed as:

where f is the frequency of transitions, Ptrans is the probability of an

output transition, and fclock is the frequency of the system clock.
 Sources of Power Dissipations
• Dynamic Power-Switching Power
The switching power dissipation for charging and discharging the
load capacitance, switching power dissipation also occurs for
charging and discharging of the internal node capacitance.
Thus, total switching power dissipation is given by

where αi and Ci are the transition

probability and capacitance,
respectively, for an internal node i.
Sources of Power Dissipations
• Dynamic Power-Short-Circuit Power
Short-circuit current or crowbar current.
• Short-circuit currents occur when both
the negative metal–oxide–
semiconductor (NMOS) and positive
metal–oxide–semiconductor (PMOS)
transistors are ON.
 Sources of Power Dissipations
• Dynamic Power-Glitching Power Dissipation
➢ The third type of dynamic power dissipation is the glitching power which arises due
to finite delay of the gates.
➢ Since the dynamic power is directly proportional to the number of output
transitions of a logic gate, glitching can be a significant source of signal activity and
deserves mention here.
➢ Glitches often occur when paths with unequal propagation delays converge at the
same point in the circuit.
➢ Glitches occur because the input signals to a particular logic block arrive at
different times, causing a number of intermediate transitions to occur before
the output of the logic block stabilizes.
➢ These additional transitions result in power dissipation, which is categorized as the
glitching power.
 Sources of Power Dissipations
• Static Power
• Static power dissipation takes place as long as the device is
powered ON, even when there are no signal changes.
• Normally in CMOS circuits, in the steady state, there is no direct path
from Vdd to GND and so there should be no static power
dissipation, but there are various leakage current mechanisms
which are responsible for static power dissipation.
• Since the MOS transistors are not perfect switches, there will be
leakage currents and substrate injection currents, which will give rise
to static power dissipation in CMOS.
 Sources of Power Dissipations
• Static Power
• Since the substrate current reaches its maximum for gate voltages
near 0.4Vdd and gate voltages are only transiently in this range
when the devices switch, the actual power contribution of
substrate currents is negligible as compared to other sources of
power dissipation.
• Leakage currents are also normally negligible, in the order of
nano-amps, compared to dynamic power dissipation.
• But with deep submicron technologies, the leakage currents are
increasing drastically to the extent that in 90-nm technology and
thereby leakage power also has become comparable to dynamic
power dissipation.
 Sources of Power Dissipations
❖ I1 is the reverse-bias p–n
• Static Power junction diode leakage current
Leakage currents in an MOS ❖ I2 is the reverse-biased p–n
Inverter- Several leakage junction current due to
mechanisms that are tunneling of electrons from the
responsible for static valence band of the p region to
power dissipation. the conduction band of the n
region
❖ I3 is the subthreshold leakage
current between the source and
the drain when the gate voltage
is less than the threshold
voltage ( Vth)
 Sources of Power Dissipations
❖ I4 is the oxide tunneling current
• Static Power due to reduction in the oxide
Leakage currents in an MOS Inverter- thickness
Several leakage mechanisms that are ❖ I5 is the gate current due to hot
responsible for static power carrier injection of electrons (I4 and
dissipation. I5 are commonly known as IGATE
leakage current)
❖ I6 is the gate-induced drain
leakage current due to high field
effect in the drain junction
❖ I7 is the channel punch through
current due to close proximity of the
drain and the source in short-
channel devices
Sources of Power Dissipations
These are generally categorized into
• Static Power four major types:
Leakage currents in an MOS Inverter- ❖ Subthreshold leakage
Several leakage mechanisms that are
❖ Gate leakage
responsible for static power
dissipation. ❖ Gate-induced drain leakage
❖ Junction leakage
Apart from these four primary
leakages, there are few other
leakage currents which also
contribute to static power
dissipation, namely,
❖ Reverse-bias p–n junction diode
leakage current
❖ Hot carrier injection gate current
❖ Channel punch through current
Dynamic Power Dissipations
• The most significant source of dynamic power
dissipation in CMOS circuits is the charging and
discharging of capacitance.
• The capacitance forms due to parasitic effects of
interconnection wires and transistors.
• Such parasitic capacitance cannot be avoided and it
has a significant impact on the power dissipation of the
circuits.
 Cont..

Fig: Equivalent circuit for charging

and discharging a capacitor.
Cont..
Cont..
• P = CL V2f
• During charging,
• CL V2 energy is drawn from the energy source, half of which is dissipated in
the charging resistance Rc and the other half is stored in the capacitor.
• During discharge,
• The energy stored in the capacitor is dissipated as heat in the discharging
resistor Rd.
• Only a few assumptions are made in our derivation:
1. The capacitance CL is constant.
2. The voltage V is constant.
3. The capacitor is fully charged and discharged, i.e., v/to) = 0, v /t]) = V, v c(t2) = 0
Cont..
 Low-Power Design Methodologies
• Low-power design methodology needs to be applied
throughout the design process starting from system level to
physical or device level to get effective reduction of power
dissipation in digital circuits based on MOS technology.
• Starting with the specifications the following steps are
performed to get layout:
• System Specification -SYSTEM-LEVEL Design
• Behavioral Description -HIGH-LEVEL Synthesis
• Structural RTL Description for Logic Synthesis
• Logic Level Net List used that for Layout Synthesis and finally, you will
get the layout for fabrication.
• So, throughout this design process you have to adopt low-
power design methodology .
 Low-Power Design Methodologies
• As the most dominant component has quadratic dependence and other
components have linear dependence on the supply voltage
• Reducing the supply voltage is the most effective means to reduce
dynamic power consumption.
• Unfortunately, this reduction in power dissipation comes at the expense of
performance.
• It is essential to devise suitable mechanism to contain this loss in performance due
to supply voltage scaling for the realization of low- power high-performance
circuits.
• The loss in performance can be compensated by using suitable techniques at the
different levels of design hierarchy; that is physical level, logic level, architectural
level, and system level.
• Techniques like device feature size scaling, parallelism and
pipelining, architectural-level transformations, dynamic voltage,
and frequency scaling.
 Low-Power Design Methodologies
• Apart from scaling the supply voltage to reduce dynamic power,
another alternative approach is to minimize the switched capacitance
comprising the intrinsic capacitances and switching activity.
• Choosing which functions to implement in hardware and which in
software is a major engineering challenge that involves issues such as
cost complexity, performance, and power consumption.
• From the behavioral description, it is necessary to perform
hardware/software partitioning in a judicious manner such that the
area, cost, performance, and power requirements are satisfied.
• Transmeta’s Crusoe processor is an interesting example that
demonstrated that processors of high performance with remarkably low
power consumption can be implemented as hardware–software hybrids.
• The approach is fundamentally software based, which replaces complex
hardware with software, thereby achieving large power savings.
 Low-Power Design Methodologies
• Although the reduction in supply voltage and gate capacitances
with device size scaling has led to the reduction in dynamic power
dissipation, the leakage power dissipation has increased at an
alarming rate because of the reduction of threshold voltage to
maintain performance.
• As the technology is scaling down from submicron to nanometer, the
leakage power is becoming a dominant component of total
power dissipation.
• This has led to vigorous research for the reduction of leakage
power dissipation.
 Low-Power Design Methodologies
• Aggressive device size scaling used to achieve high performance leads
to increased variability due to short-channel and other effects.
• Performance parameters such as power and delay are significantly
affected due to the variations in process parameters and
environmental/operational ( Vdd, temperature, input values,
conditions.
• For designs, due to variability, the design methodology in the
future nanometer VLSI circuit designs will essentially require a
paradigm shift from deterministic to probabilistic and statistical
design approach.
• The impact of process variations has been investigated and several
techniques have been proposed to optimize the performance and
power in the presence of process variations
Need for Low Power VLSI Chips
Power dissipation was neglected due to
– Low device density
– Low operating frequency
• Now it is important issue due to
– High device density
– High operating frequency
– Proliferation of portable consumer electronics
– Concerns on Environments and energy sources
 Needs for Low Power VLSI Chips
Power dissipation of VLSI chips is traditionally a neglected subject.
• In the past, the device density and operating frequency were low
enough that it was not a constraining factor in the chips.
• As the scale of integration improves, more transistors, faster and
smaller than their predecessors, are being packed into a chip.
• This leads to the steady growth of the operating frequency and
processing capacity per chip, resulting in increased power dissipation.
Physics of CMOS Power Dissipation

• Derivation of sub-threshold current & swing

• Deviations of Submicron MOSFET VT from predictions
• Short-Channel and Narrow-Gate-Width Effects
• Drain-Induced Barrier Lowering
• Gate-Induced Drain Leakage
• Summary
Metal-Insulator-Semiconductor (MIS) Structure
Motivation for Transistor Review
• Reformulate MOSFET models and equations to:
• Obtain better VT computation
• Obtain critical subthreshold current
• Obtain critical subthreshold swing
• Calculate drain induced barrier lowering (DIBL)
• Allows correct estimation and understanding of low-
power currents
❖ Figure 1 shows the MIS structure. A layer of thickness d of insulating material is
sandwiched between a metal plate and the semiconductor substrate.
❖ Let us assume the semiconductor be of p -type. A voltage V is applied between
the metal plate and the substrate. Let us first consider the case when V = 0. As we are
considering an ideal MIS diode, the energy difference , between the metal work
function and the semi- conductor work function is zero, that is,

❖ 'The work function is defined as the minimum energy necessary for a metal electron
in a metal—vacuum system to escape into the vacuum from an initial energy at the
Fermi level.
❖ The electron affinity of a semiconductor is the difference in potential between
an electron at the vacuum level and an electron at the bottom of the conduction
band
❖ In an ideal MIS diode the insulator has infinite
resistance and does not have either mobile charge carriers Intrinsic Fermi level
or charge centers. ❖ In intrinsic semiconductor
❖ As a result, the Fermi level in the metal lines up with the , the number of holes in
Fermi level in the semiconductor. valence band is equal to
❖ The Fermi level in the metal itself is same throughout the number of electrons in
(consequence of the assumption of uniform doping). the conduction band.
This is called the flat-band condition as in the energy
band diagram, the energy levels and , appear as straight ❖ Hence, the probability of
lines (Figure 2) occupation of energy
levels in conduction band
and valence band are
equal.
❖ Therefore, the Fermi
level for
the intrinsic semiconducto
r lies in the middle of
band gap.

Figure 2 Energy bands in an unbiased MIS diode.

Ideal MIS Diode
• Type p semiconductor
• At V = 0,
• ms = energy
difference between
metal & semiconductor
•  = semiconductor
electron affinity E
g
• ms = m – ( + 2q + B ) = 0
• Flat-band condition – usually have to apply VFB (flat-band
voltage) to cause this to happen
Definitions
• m – Work function for metal material
• s – Work function for semiconductor material
• B – Potential difference between Ei and EF
• Eg – Bandgap energy for semiconductor material
• Ei – Intrinsic energy level for semiconductor material (undoped)
• EF – Average energy level for doped semiconductor material
❖ When the voltage V is negative, the holes in the p-type semiconductor are attracted
to and accumulate at the semiconductor surface in contact with the insulator layer.
Therefore this condition is called accumulation.
❖ In the absence of a current flow, the carriers in the semiconductor are in a state of
equilibrium and the Fermi level appears as a straight line. The Maxwell—
Boltzmann statistics relates the equilibrium hole concentration to the intrinsic
Fermi level:

❖ So the intrinsic Fermi level has a higher value at the surface than at a
point deep in the substrate and the energy levels and , bend upward near
the surface (Figure 3). The Fermi level EF in the semiconductor is now
— qV below the Fermi level in the metal gate.

Figure 3 Energy bands

when a negative bias is applied.
 Accumulation
• p0 = ni e (Ei – EF) / kT
• Energy bands when a negative voltage is applied:

March 7, 2026 58
• When the applied voltage V is positive but small, the holes in the p-type
semiconductor are repelled away from the surface and leave negatively charged
acceptor ions behind.
• A depletion region, extending from the surface into the semiconductor, is created.
This is the depletion condition. Besides repelling the holes, the positive voltage on
the gate attracts electrons in the semiconductor to the surface. The surface is said
to have begun to get inserted from the original p-type to n-type.
• While V is small, the concentration of holes is still larger than the concentration of
electrons. This is the weak-inversion condition and is important to the study of
power dissipation in MOSFET circuits. The bands at this stage bend downward
near the surface (Figure 4).

Figure 4Energy bands when a small positive bias is applied.

Weak Inversion
• Energy bands when small positive bias voltage is applied:

March 7, 2026 60
❖If the applied voltage is increased sufficiently, the bands bend far enough that
level
Ei ; at the surface crosses over to the other side of level EF .
❖When V is increased to the extent that the electron density at the surface n,
becomes greater than the hole density in the bulk, onset of strong inversion
is said to have occurred. This condition is depicted in Figure 5.

Figure 5 Energy bands in strong inversion

Strong Inversion

• Ei at surface now below EF by 2 B

• B = potential difference between EF and Ei in bulk
• VT = voltage necessary to cause strong inversion
March 7, 2026 62
❖ The various modes depending upon the applied voltage can be summarized
as,

❖ V=0, flat band condition

❖ V= -ve, Accumulation
❖ V=small +ve, weak inversion
❖ V=large +ve, stronger inversion
Surface Space Charge and VT
• Charge sheet model
• Poisson equation:
D =  (x, y, z)

• D = s E (disp. Vect.)
•  (x, y, z) = total electric charge density
• Neglect fringing fields at edge of transistor, so E is normal
to SiO2 insulator

March 7, 2026 64
Derivation of Bulk Charge

Ey = Ez = 0

March 7, 2026 65
 Problem
• Next slides introduce the conventional VT derivation and
model
• Problem: Simply does not work any more for  < 0.35 m due
to:
• Much greater sub-threshold current, which is due to carriers diffusing
in the channel before VGS exceeds VT
• VT no longer behaves the way the conventional model predicts
• Less susceptible to body effect
• Much more susceptible to VD (drain voltage) due to drain-induced barrier
lowering (DIBL)
• Much more susceptible to gate-induced drain leakage (GIDL)
• Forced the adoption of a radically different transistor model
• Will give a new, corrected model later
• Models DIBL, GIDL, VT correctly using curve-fitting to
measurements

March 7, 2026 66
Conventional VT Derivation
• From Gauss’s Law, total charge in semiconductor is:

• Note: s = surface potential = 2 B at strong inv.

•  = q / kT, d = SiO2 insulator thickness

March 7, 2026 67
Depletion Region Depth
• Depletion assumption – regard depletion layer as totally devoid of
mobile charges
• One-sided abrupt-junction assumption – carrier concentrations
abruptly change to their intrinsic values at distance W (= depletion
region depth) beneath surface
• QT = total trapped charge at semiconductor-insulator boundary

March 7, 2026 68
Flat-Band Voltage And Depletion Layer Depth

• Poisson equation (used to compute depletion layer

depth):

March 7, 2026 69
Depletion Layer Depth Wm at Strong Inversion

March 7, 2026 70
What is Inversion Layer?
• The traditional metal–oxide–semiconductor (MOS) structure is obtained by
growing a layer of silicon dioxide (SiO2) on top of a silicon substrate and
depositing a layer of metal or polycrystalline silicon (the latter is commonly
used).
• As the silicon dioxide is a dielectric material, its structure is equivalent to a
planar capacitor, with one of the electrodes replaced by a semiconductor.
• When a voltage is applied across a MOS structure, it modifies the distribution
of charges in the semiconductor.
• If we consider a p-type semiconductor (with the density of acceptors, p the
density of holes; p = NA in neutral bulk), a positive voltage, , from gate to body
(see figure) creates a depletion layer by forcing the positively charged holes
away from the gate-insulator/semiconductor interface, leaving exposed a
carrier-free region of immobile, negatively charged acceptor ions (see doping
(semiconductor)).
What is Inversion Layer?

• If Vg is high enough, a high concentration of negative charge carriers forms a inversion layer
located as a thin layer next to the interface between the semiconductor and the insulator.
• Unlike the MOSFET, where the inversion layer electrons are supplied rapidly from the
source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal
generation through carrier generation and recombination centers in the depletion region.
• Let us derive a approximation for the thickness of the inversion layer.
• This is done by assuming that the charge density in the inversion layer is much higher than the
density of the ionic charge in the bulk layer and that the inversion layer is very thin.
• Thus in the inversion layer is much greater than in the bulk.

• Here can be approximated by considering the value of the electric field at the bottom
edge of the inversion layer to be zero.
•
Inversion Layer Charge
• Qi = inversion layer, Qd = depletion layer charge

March 7, 2026 73
Inversion Layer Thickness ti

March 7, 2026 74
 Long-Channel MOSFET
Body Effect
• VGS = VGB – VBS
• Surface potential was s, becomes S + VBS relative to source
• VT now becomes:

March 7, 2026 75
 Subthreshold Current – New
Problem

• Weak inversion – variation of minority carrier

concentration along channel

March 7, 2026 76
Subthreshold Current (cont’d)


• Consider grounded nFET source, VGS < VT, |V DS| 0.1 V
• Weak inversion – VDS drop almost entirely across reverse-biased
substrate-drain p-n junction
• Small variation of s along semiconductor surface
• y component Ey =  / y is small
• Due to few mobile carriersand small Ey, drift component of
subthreshold ID,st negligible

March 7, 2026 Analog and Low-Power Design Lecture 2 (c) 2003 77

Subthreshold Current
• Long channel allows (cont’d)
the gradual channel approximation
to be used

• np = ni2e s
NA exponentially on s, np (y)/ y can be large
• np depends

• Diffusion current proportional to carrier 
concentration
gradient – varies along y (distance along channel)

March 7, 2026 78
Terminology
• A = channel cross-sectional area
• Dn = electron diffusion coefficient
• Z = channel width
• ti = inversion layer thickness
• Qi = ti q n (y) (per-unit inversion layer area charge)
• Equilibrium electron concentration:

• Charge in inversion layer (weak inversion):

March 7, 2026 79
Derivation Continued

Source:

Drain:

March 7, 2026 80
Observation

• Different situation from MIS diode – potential gradient along y axis,

must consider effect of VDS
• ID,st is the subthreshold component of drain current

March 7, 2026 81
Subthreshold Current
• For long-channel MOSFET, subthreshold drain-source
current remains independent of drain-source voltage
• s (y = 0) varies exponentially with applied gate voltage,
so the drain-source current also does
• Independence of ID,st from VDS ceases when L is as large
as 2 m when VDS is large enough to merge source and
drain depletion regions (punchthrough)
• Must prevent punchthrough, as it makes ID,st independent
of gate control voltage
• Must keep punchthrough current smaller than ID,st using
implants
March 7, 2026 82
 Subthreshold Swing
• Subthreshold swing is inverse of slope of log ID,st vs. VGS

• Cd = gate depletion layer capacitance

• CI = insulator layer capacitance
• s = permittivity of semiconductor
• i = permittivity of insulator
• d = insulator thickness
• W = depletion layer thickness
• Sst shows how effectively we can stop device drain current flow
when VGS goes below VT

March 7, 2026 Analog and Low-Power Design Lecture 2 (c) 2003 83

Subthreshold Swing (cont’d)
• Subthreshold swing (mV/decade) limits how small a
power supply we can use
• For d 0, Sst = 60 mV/decade (100 in practice)
• Due to non-zero oxide thickness and other factors
• Sst = 100 reduces ID,st from 1 A/m at VGS = VT = 0.6 V to
1 pA/m at VGS = 0 V
• Ways to make Sst smaller:
• Thinner oxide layer to reduce d
• Lower substrate doping (larger W)
• Lower temperature
• Lower substrate bias

March 7, 2026 Analog and Low-Power Design Lecture 2 (c) 2003 84

Submicron MOSFET
• Number of circuits on chip and their speed grow
exponentially
• Make faster devices – Increase ID,st (now drain current in
saturation) to charge/discharge parasitic C’s faster
• Was predicted
 that:
• L 2 m, VT would be independent of L, Z, VDS
• Instead, decreases with L, varies with Z, decreases as VDS increases
• Instead, VT increases less rapidly with VBS than with longer channels
• Need to understand these effects with small dimension
MOSFETs – need to use curve-fitting to model SPICE
parameters

March 7, 2026 85
Submicron Effects effect:
• Short-channel-length on VT
• VT decreases with decreasing L and increasing VDS
• Causes excessive leakage currents
• Can only achieve VT in 0.6 to 0.8 V range with lightly doped substrate
by using VT adjust implants to increase surface doping
• Lowers carrier mobility, subthreshold current, etc.
• When L same order of magnitude as width of drain-substrate
or substrate-source depletion region:
• Ionic charge in these depletion regions reduces charge needed by
gate bias (added to total space charge) to cause inversion
• Smaller VGS turns on device
• Drain depletion area goes deeper into substrate, making turn-on VT
even smaller when drain–substrate reverse bias increases

March 7, 2026 86
Modeling Problems
• To understand this, must numerically solve 2-dimensional Poisson
equation
• Charge-sharing model: considers channel charge to be shared among
source, gate, and drain, didn’t work
• Drain-induced barrier lowering (DIBL): VT decreases due to depletion
region changes in potential energy barrier between source and
semiconductor surface.
 Poisson
• Reduces 2-dimensional  equation to 1-D by approximating 2
/ x2 as a constant. Works for L = 0.8 m and VDS as large as 3 V

March 7, 2026 87
Liu Model for DIBL
• Predicts short-channel threshold voltage shift VT,sc for deep
submicron devices
• Quasi-2D solution of 2D Poisson equation
• E has a horizontal component Ey (drain field) and vertical component
Ex (due to gate charge)
• Ex maximal at source and decreases with y to a minimum value at
drain
• Ex (x, y) value at insulator-semiconductor surface is Ex (0,y) and goes
to 0 at bottom edge of depletion region
(Ex (W, y) = 0)

March 7, 2026 88
DIBL Model
 
• Replace Ex/ x at each point (x,y) with its average of values at (0, y) and (W,
y)

• Use depletion approximation, so depletion region charge is simply the ionic

charge ( (x, y) = qNA)

March 7, 2026 89
DIBL (cont’d)

March 7, 2026 90
DIBL (cont’d)
•  is empirical fudge factor and W = Wm at onset of strong
inversion
• VsL = VGS – VT Effective gate voltage
• Vbi is built-in potential at drain-substrate and substrate-source
p-n junctions

• Characteristic
length:
• Find VT,sc by subtracting long-channel s value at VT from
minimum of s(y), using plotting and curve fitting
• Note that surface potential is never constant for L = 0.35 m

March 7, 2026 91
Surface Potential Along Channel

March 7, 2026 92
Finding VT
• Subtract minimum value of s(y) from RHS of Eq. (2.39) to get
VT,sc
• If l > 5L,

• Simplification:

• Problem:  makes it hard to find l (the characteristic length)

March 7, 2026 93
Relating l to
• l can be Lminto minimum channel length Lmin needed
related
in a MOSFET to make it have long-channel characteristics

• If Lmin = 4l, then

• Leads to VT:

March 7, 2026 94
Significant
• Need: Changes in VT

• Then, for nFET with n+ poly gate:

• For nFET with p+ poly gate:

• Old VT equation:

March 7, 2026 95
DIBL Concluded

-2s-VBS
•Dropped e term as being negligibly small
•For shorter channel lengths and higher drain biases,
VT less sensitive to VBS than (2.49) indicates
•Instead, VT becomes completely independent of VBS when
L = 0.7 m and for large values of VBS in all cases

March 7, 2026 96
Narrow-Gate-Width Effects
• Have less effect on VT than short-channel effects
• View channel as rectangle in horizontal cross section.
• First two effects caused by MOSFETs with raised field-oxide isolation
or semi-recessed local oxidation (LOCOS)
• 1st effect:
• Parallel edges border drain and source, and therefore are on depletion
regions.
• Other two edges have no depletion region under them
• Charges under first 2 edges decrease charge needed from gate voltage, so
absence of depletion region under other 2 edges increases VGS needed to
invert channel (increased VT)

March 7, 2026 97
Narrow-Gate-Width Effects
• 2nd Effect:
• Higher channel doping along edges along width dimension (due to channel
stop dopants (n) or oxidation of piled-up phosphorous (p) under gate)
• Need a higher VT to invert channel
• 3rd Effect:
• Reverse short-channel effect: As channel length reduces from L = 3 m, VT
initially increases until L = 0.7 m. Below that, VT decreases faster than
predicted by theory
• Caused by trench or fully-recessed isolation – when gate biased, field lines
from gate region overlapping channel are focused by edge geometry, and
make it easier to invert the channel

March 7, 2026 98
 Overlapping Depletion Regions (or
Punchthrough)
• As L decreases, separation between source and drain depletion
regions decreases
• Increased reverse bias pushes boundaries further from junction and
closer to each other
• Deep submicron MOSFET has a VT adjust implant only at the surface.
Causes greater expansion in depletion regions below the surface, so
punchthrough first happens below the surface

March 7, 2026 99
 • Any drain voltage (concluded)
Punchthrough increase after punchthrough happens lowers
potential energy barrier for majority carriers in the source
• More of these enter the substrate, but some collected by drain
• Increases subthreshold current ID,st
• Slope of Sst curve flatter if subsurface punchthrough occurred
• Use VPT (punchthrough voltage) defined as value of VDS where ID,st
reaches some specific value with VGS = 0

• NB = bulk doping
• Very bad for low-power devices:
• Fix with extra implants (cannot fix by changing dopings alone)

March 7, 2026 100

Gate-Induced Drain Leakage
• Large field exists in oxide where n+ drain of MOSFET lies under the
gate and the drain is at VDD, and the gate is at VSS
• Causes a charge Qs = ox Eox (Gauss’s Law) to be induced in drain,
sweeps any minority carriers that are under the drain laterally to the
substrate
• Enables tunneling in drain via a near-surface trap, completes a path
for a gate-induced drain leakage (GIDL) current
• Contributes to standby power, so must control this by increasing
oxide thickness, increasing drain doping, or eliminating traps

March 7, 2026 101

Gate-Induced Drain Leakage

March 7, 2026 102

 Summary
• Derivation of sub-threshold current & swing important for low-
power design
• Submicron MOSFET VT and subthreshold current deviate from
predictions
• Short-Channel and Narrow-Gate-Width Effects
• Drain-Induced Barrier Lowering is important
• Gate-Induced Drain Leakage is important

March 7, 2026 103

 Threshold Voltage
❖ n-type MOS: Majority carriers are electrons.
❖ p-type MOS: Majority carriers are holes.
❖ Positive/negative voltage applied to the gate (with respect to substrate)
❖ enhances the number of electrons/holes in the channel and increases conductivity
between source and drain.
❖ Vt defines the voltage at which a MOS transistor begins to conduct.
❖ For voltages less than Vt (threshold voltage), the channel is cut off.
❖ In normal operation, a positive voltage applied between source and drain (Vds).
❖ No current flows between source and drain (Ids = 0) with Vgs = 0 because of back to
back pn junctions.
❖ For n-MOS, with Vgs > Vtn, electric fi eld attracts electrons creating channel.
❖ Channel is p-type silicon which is inverted to n-type by the electrons attracted by the
electric field.
• Three modes based on the magnitude of Vgs: accumulation,
depletion and inversion.
 Operating regions
What are the parameters that effect the magnitude of Ids?
❖
The distance between source and drain (channel length).
✓
The channel width.
✓
✓ The threshold voltage.
✓ The thickness of the gate oxide layer.
✓ The dielectric constant of the gate insulator.
✓ The carrier (electron or hole) mobility.

❖ The important regions of operation of M O S F E T are:

✓ Cut-off: accumulation, Ids is essentially zero.
✓ Nonsaturated: weak inversion, Ids dependent on both V gs
and Vds.
✓ Saturated: strong inversion, Ids is ideally independent of
Vds.
 T h r e s h o l d Vo l t a g e
❖ Vt is also an important parameter. What effects its value?

❖ The parameters that effect Vt include:

✓ The gate conductor material (poly vs. metal).
✓ The gate insulation material (SiO2).
✓ The thickness of the gate material.
✓ The channel doping concentration.

❖ However, Vt is also dependent on

✓ Vsb (the voltage between source and substrate), which is normally 0 in digital devices.
✓ Temperature: changes by -2mV/degree C for low substrate doping levels.
 ❖
Body effect ❖ Assume that Vs=Vd=0 and Vg<Vth, so that a
depletion region is formed under the gate as shown
in fig. (a).
❖ When, Vb more –ve, more holes will be attracted
by the bulk potential (Vb), leaving behind large
negative charge behind.
❖ As a result the depletion region becomes wider as
shown in fig. (b).
❖ Threshold voltage is a function of total charge in
the depletion region
❖ The gate charge must mirror the depletion charge
Qd.
❖ So as Qd increases, the gate charge should increase
and for that the gate potential has to be increased.
This results in increase in threshold voltage.
❖ This phenomenon is known as body effect.
❖ With body effect,
❖ =+γ
❖ The body effect coefficient, γ = /
❖ is the source –bulk surface potential
 Short channel effects
❖ The main drives for reducing the size of the transistors, i.e.,
their lengths, is increasing speed and reducing cost.
❖ When we make circuits smaller, their capacitance reduces,
thereby increasing operating speed.
❖ However, when the device size is reduced further, it may result
in unwanted side effects and these are called short channel
effects. These effects are
❖ Surface scattering,
❖ Punch through,
❖ Velocity saturation,
❖ Impact ionization
❖ Hot electron effects,
❖ Drain induced barrier lowering,
❖ Narrow width effects
 Surface scattering
❖ The velocity of the charge carriers is defined by the mobility of that carrier
times the electric field along the channel. That is.
v= μE
❖ When the carriers travel along the channel, they are attracted to the surface by
the electric field created by the gate voltage.
❖ As a result, they keep crashing and bouncing against the surface, during their
travel, following a zig-zagging path.
❖ This effectively reduces the surface mobility of the carriers, in comparison with
their bulk mobility.
❖ The change in carrier mobility impacts the current-voltage relationship of
the transistor
❖ As the length of the channel becomes shorter, the lateral electric field
created by becomes stronger.
❖ To compensate that, the vertical electric field created by the gate voltage
needs to increase proportionally, which can be achieved by reducing the
oxide thickness.
❖ As a side effect, surface scattering becomes heavier, reducing the effective
mobility in comparison with longer channel technology nodes.
 DIBL (Drain Induced Barrier Lowering)
❖ Drain-induced barrier lowering (DIBL) is a short-channel
effect in MOSFETs referring originally to a reduction of threshold voltage of
the transistor at higher drain voltages.
❖ The source and drain depletion regions can intrude into the channel even
without bias, as these junctions are brought closer together in short channel
devices.
❖ This effect is called charge sharing since the source and drain in effect take
part of the channel charge, which would otherwise be controlled by the gate.
❖ As the drain depletion region continues to increase with the bias, it can
actually interact with the source to channel junction and hence lowers the
potential barrier.
❖ This problem is known as Drain Induced Barrier Lowering (DIBL).
❖ When the source junction barrier is reduced, electrons are easily injected into
the channel and the gate voltage has no longer any control over the drain
current.
As channel length decreases, the barrier φB to be surmounted by an
electron from the source on its way to the drain reduces
 Drain Punch Through
❖ When the drain is at high enough voltage with respect to the source, the
depletion region around the drain may extend to the source, causing current
to flow irrespective of gate voltage (i.e. even if gate voltage is zero).
❖ This is known as Drain Punch Through condition and the punch through
voltage VPT given by:

❖ So when channel length L decreases (i.e. short channel length case), punch
through voltage rapidly decreases.
 Impact ionization
❖ In short channel devices, the effect of electric field will be higher.
❖ High electric field increases the velocity of electrons.
❖ These electrons impact the drain, and electron –hole pairs will be generated.
 Hot electron effect
❖ The hot electron effect is due to the shrinking of technology.
❖ If we go on reducing the length of the gate, the electric field at the drain of
the transistor increases (for a fixed drain voltage).
❖ The field may become so high that electrons are imparted with enough
energy to become what is termed as "hot".
❖ These electrons impact the drain, and electron–hole pairs will be generated.
❖ The electrons enter gate oxide, it will cause gate current.
❖ This may lead to the degradation of device parameters like threshold
current, subthreshold current, and transconductance.
❖ The holes enter the substrate and they will cause a substrate current
❖ The deposition of negative charge on the gate may increase threshold
voltage by increasing flat band voltage.
❖ This effect is usually limited to n-channel devices as holes have much
lower mobility than electrons and the barrier between the valence band of
oxide and silicon is higher at about 5eV compared to 3 eV between the
conduction band of silicon and oxide

❖ Methods to reduce the hot electron effect

1. Reduce the supply voltage.

2. Use STI(Shallow trench isolation).
3. Hot carrier effects are less problematic for holes in p-MOSFETs.
4. LDD (lightly doped drain) can be a solution for the stress of the
hot carrier effect.
5. Use a long-channel device.
 Velocity Saturation
❖ Velocity saturation occurs in any general solid state device when charged
carriers move in a solid under the force of an electric field, they acquire a
velocity proportional to the magnitude of this electric field.
❖ This applied electric field (E) and the carrier velocity (v) are related through
the mobility parameter μ.
v= μE
❖ For small electric field, μ is constant and independent of the applied electric
field.
μ= (constant)
❖ As a result when carrier velocity is plotted versus the applied electric field,
the result is a straight line
❖ Both the electron and hole drift velocities saturate at applied electric fields
in excess of about 100 kV/cm.
❖ In short-channel devices, the electric field near the drain can attain values in
excess to 400kV/cm.
Figure :Electric field versus Carrier velocity in a solid
❖ Where EC is the critical electric field, EY is the channel field, α has a value
close to 2 for electrons and 1 for holes.
❖ Velocity saturation will yield an Ids(sat) value smaller than that predicted is
ideal relation ,and it will yield a smaller Vds(sat) value that predicted .
❖ In a short channel MOSFET before attaining pinch off carrier drift velocity
saturates and thus the current saturation occurs at a low value of Vds.
❖ Ids will be linear with Vgs.
❖ Thus the short-channel devices therefore experience an extended saturation
region, and tend to operate more often in saturation conditions than their long-
channel counterparts.
 Narrow width effect
❖ Another related effect in MOSFETs is the narrow width effect, where the VT goes up as the
channel width Z is reduced for very narrow devices.
❖ This can be understood from Fig. given below, where some of the depletion charges
under the LOCOS isolation regions have field lines electrically terminating on the
gate.
❖ Unlike the SCE(Short channel effect), where the effective depletion charge is reduced
due to charge sharing with the source/drain, here the depletion charge belonging to the
gate is increased.
❖ The effect is not important for very wide devices, but becomes quite important as the widths
are reduced below 1μm.
 Deep submicron devices design issues
❖ Scaling down feature size is an important issue for high-performance and
high-density circuits.
❖ However, some second order effects become serious for short-channel
devices.
❖ The reduction of short channel effect (SCE), has become a major challenge in
deep sub-micrometer devices and circuits.

❖ The important SCE includes,

✓ Threshold voltage roll-off and
✓ Drain induced barrier lowering (DIBL),
Short-channel threshold voltage roll-off
Fig.6 shows a schematic of a MOS transistor. Here L is the channel length and Xj
is the source and drain junction depth

Fig.6 A schematic of a MOS transistor.

The surface potentials of short channel and long channel
devices before strong inversion are shown in fig.7. The drain,
source and body voltages are all zero.

Fig.7 The surface potentials of short channel and long channel devices (Vd=0V)
❖ For a long channel transistor, the barrier is constant.
❖ As for a short channel device, the barrier is reduced along with the scaling
of the channel length.
❖ Therefore, the smaller the channel length, the lower the threshold voltage.
❖ The relationship between threshold voltage and transistor channel length is
shown in fig. 8

Fig.8 Threshold voltage versus channel length. In order to make the device work properly,
dVth/dL cannot be too large. This will determine the minimum channel length (Lmin)
 Drain-induced barrier lowering
• Fig. 9 shows the surface potentials of long-channel and short-channel
devices at a large drain voltage (Vd).
• For a long-channel device, the barrier is not sensitive to Vd. However, the
barrier of a short-channel device will reduce along with the increase of
drain voltage, which will cause a higher subthreshold current and lower
threshold voltage.

Fig. 9 The surface potentials of short channel and long channel devices (Vd > 0V)
 Minimizing short channel effect
• In order to minimize a short-channel effect, a sufficient large aspect ratio (AR) of the
device is required. AR is defined as,

AR=DIMENSION lateral/ DIMENSION vertical (1)

For a MOSFET, AR can be expressed as

Where and are the silicon and oxide permittivities

• L, , d, are channel length, gate oxide thickness, depletion depth and junction depth
respectively.
• From the above equation, we can see that reducing d and will reduce the SCE of a
MOSFET. In order to minimize SCE, a modified MOSFET structure can be used.
• Fig. 10 shows the low-impurity channel shallow-junction MOSFET
 Fig.10 Low-impurity channel shallow-junction MOSFET

❖ The small SCE of this transistor is because of the small depletion depth and
junction depth.
❖ The AR of a single gate silicon-on-insulator (SOI) MOSFET is shown in
fig.11.
• Since d , the AR is given by

Fig.11 A single-gate SOI MOSFET

 ❖ Fig. 12 shows a double-gate silicon-on-insulator (DGSOI) MOSFET. The AR of
DGSOI MOSFET is

Fig.12 A DGSOI MOSFET

❖ It is clear that the effective junction depth and the depletion width are reduced to half of
that of a bulk MOSFET.
❖ Therefore, the SCE of a DGSOI MOSFET is much smaller than a bilk silicon MOSFET,
which makes it a good candidate for deep sub micrometer applications.
❖ Short channel threshold voltage roll-off and DIBL are two short-channel effects, which will
complicate the transistor