Bangalore Institute of Technology, Bangalore
BVL613A-Low Power VLSI
Design
Module - 4
Dr Jalaja S
Associate Professor/EE (VDT)
Logic Synthesis for Low Power
• To address the challenge to reduce power, the semiconductor
industry has adopted a multifaceted approach, attacking the problem
on four fronts:
• Reducing chip and package capacitance: This can be achieved
through process development such as SOl with fully depleted wells,
process scaling to submicron device sizes, and advanced interconnect
substrates such as Multi-Chip Modules (MCM). This approach can be
very effective but is expensive.
• Scaling the supply voltage: This approach can be very effective in
reducing the power dissipation, but often requires new IC
fabrication processing. Supply voltage scaling also requires
support circuitry for low-voltage operation including level-
converters and DC-DC converters as well as detailed
consideration of issues such as signal-to-noise.
• Using power management strategies: The power savings that
can be achieved by various static and dynamic power
management techniques are very application dependent, but can
be significant.
• Employing better design techniques: This approach promises to
be very successful because the investment to reduce power by
design is relatively small in comparison to the other two
approaches and because it is relatively untapped in potential.
The ASIC design flow
Cont..
1) estimate power dissipation during the design
process to meet the power budget without having
to go through a costly redesign effort
2) enable efficient design and characterization of the
design libraries and
3) reduce the power dissipation using various
transformations and optimizations.
Power Estimation Techniques
1. Sources of Power Dissipation
Power dissipation in CMOS circuits is caused by three sources:
1) the leakage current which consists of reverse bias current in the
parasitic diodes formed between source and drain diffusions and
the bulk region in a MOS transistor as well as the subthreshold
current that arises from the inversion charge that exists at the gate
voltages below the threshold voltage,
2) the short-circuit (rush-through) current which is due to the DC
path between the supply rails during output transitions and
3) the charging and discharging of capacitive loads during logic
changes.
Cont..
• Source of power dissipation is thus the charging and discharging of
the node capacitances (also referred to as the dynamic power
dissipation) and is given by:
• where Vdd is the supply voltage, TCycle is the clock cycle time, Cg is the
capacitance seen by gate g and Eg(sw) (referred as the switching
activity) is the expected g number of transitions at the output of g
per clock cycle.
• The product of Cg and Eg(sw) is often referred as the switched
capacitance.
• At the logic level, we assume that Vdd and Tcycle are fixed, and thus,
minimize the total switched capacitance of the circuit.
Physical Capacitance
• Power dissipation is dependent on the physical capacitances seen
by individual gates in the circuit.
• Estimating this capacitance at the technology independent phase
of logic synthesis is difficult and imprecise as it requires
estimation of the load capacitances from structures which are
not yet mapped to gates in a cell library; this calculation can
however be done easily after technology mapping by using the
logic and delay information from the library.
• Interconnect plays an increasing role in determining the total
chip area, delay and power dissipation,
Circuit Structure
• The major difficulty in computing the switching
activities is the reconvergent nodes.
• For networks with reconvergent fanout, the problem
is much more challenging as internal signals may
become strongly correlated and exact consideration of
these correlations cannot be performed with
reasonable computational effort or memory usage.
Input Pattern Dependence
• Switching activity at the output of a gate depends not
only on the switching activities at the inputs and the logic
function of the gate, but also on the spatial and temporal
dependencies among the gate inputs.
• Alternatively, exhaustive simulation may be replaced by
Monte-Carlo simulation with well-defined stopping
criterion for specified relative or absolute error in power
estimates for a given confidence level
Delay Model
• Based on the delay model used, the power
estimation techniques could account for steady-state
transitions (which consume power, but are necessary
to perform a computational task) and/or hazards and
glitches (which dissipate power without doing any
useful computation).
• Sometimes, the first component of power
consumption is referred as the functional activity
while the latter is referred as the spurious activity.
Cont..
• In the first model, it is assumed that all changes at the circuit inputs
propagate through the internal gates of the circuits instantaneously
• The latter model assigns each gate in the circuit a finite delay and can
thus account for the hazards in the circuit (see Figure).
• A real delay model significantly increases the computational
requirements of the power estimation techniques while improving
the accuracy of the estimates.
Figure: Effect of the delay model
Statistical Variation of Circuit Parameters
• In real networks, statistical perturbations of circuit parameters
may change the propagation delays and produce changes in the
number of transitions because of the appearance or
disappearance of hazards.
• it is expected that the hazardous component of power
dissipation is more sensitive to IC parameter fluctuations than
the power required to perform the transition between the initial
and final state of each node.
• These techniques are divided into two general categories:
simulation based and probabilistic.
Simulation-Based Techniques
• Circuit simulation based techniques simulate the circuit with
a representative set of input vectors.
• They are accurate and capable of handling various device
models, different circuit design styles, single and multi-phase
clocking methodologies, tristate drives, etc.
• However, they suffer from memory and execution time
constraints and are not suitable for large, cell-based designs.
• The size of such a vector set is dependent on the application
and the system environment
Cont..
• Monte-Carlo program, thus trading accuracy for higher
efficiency. The convergence time for this approach is fast
when estimating the total power consumption of the circuit.
• Switch-level simulation techniques are in general much faster
than circuit level simulation techniques, but are not as
accurate or versatile.
• Standard switch-level simulators can be easily modified to
report the switched capacitance (and thus dynamic power
dissipation) during a simulation run.
Cont..
• PowerMill is a transistor-level power simulator and analyzer
which applies an event-driven timing simulation algorithm
(based on simplified table-driven device models, circuit
partitioning and single-step nonlinear iteration) to increase
the speed by two to three orders of magnitude over SPICE.
• PowerMill gives detailed power information (instantaneous,
average and arms current values) as well as the total power
consumption (due to steady-state transitions, hazards and
glitches, transient short circuit currents, and leakage currents).
Power Minimization Techniques
• Logic synthesis fits between the register transfer level and the netlist of
gates specification.
• It provides the automatic synthesis of netlists minimizing some objective
function subject to various constraints.
• Depending on the input specification (combinational versus sequential,
synchronous versus asynchronous), the target implementation (two-level
versus multi-level, unmapped versus mapped, ASICs versus FPGAs), the
objective function (area, delay. power, testability) and the delay models
used (zero-delay, unit-delay, unit-fanout delay, or library delay models),
different techniques are applied to transform and optimize the original RTL
description.
Cont..
Both the switching activity and the capacitive loading can
be optimized during logic synthesis.
Research in this area is focusing on the following:
(1) Developing low power version of various logic
optimization and restructuring techniques and doing this
in such a way that the timing and/or area constraints are
met.
(2) Developing more accurate, yet simple, computational
models for estimating the parasitic wiring capacitances,
signal correlations, short circuit currents, etc.
Precomputation Logic
• The basic idea is to selectively precompute the output logic values
of the circuits one clock cycle before they are required, and then use
the precomputed values to reduce internal switching activity in the
succeeding clock cycle.
• A precomputation architecture is shown in Figure.
• The inputs to block A have been partitioned into two sets,
corresponding to registers R 1 and R2
• The output of the logic block A feeds register R3. Two Boolean
functions gl and g2 are the predictor functions. It is required that:
• During clock cycle t if either gl or g2 evaluates to 1, set the load
enable signal of register R2 to O.
• This implies that the outputs of R2 during clock cycle t+ 1 do not
change. However, since the outputs of R 1 are updated, function/will
be calculated correctly.
• Power reduction is achieved because only a subset of the inputs to
block A change, implying reduced switching activity in block A.
Figure: A precomputation architecture
Retiming
• Retiming is the process of re-positioning the flip-flops in a
pipelined circuit so as to either minimize the number of flip-
flops or minimize the delay through the longest pipeline stage.
• A flip-flop output makes at most one transition when the clock
is asserted (Figure).
• a circuit retiming technique targeting low power dissipation.
• The idea is to identify circuit nodes with high hazard activity
and high load capacitance as candidates for adding a flip-flop.
• The technique does not produce the optimal retiming solution
as the retiming of a single node can dramatically change the
switching activity of many other nodes in the circuit.
Cont..
Figure: Flip-flop insertion to minimize hazard activity
State Assignment
• State assignment of a finite state machine (which is
the process of assigning binary codes to the states)
has a significant impact on the area of its final logic
implementation.
• The encoding problem for minimum area of two-level
or multi-level logic implementations.
• These techniques can be modified to minimize the
power dissipation.
Multi-Level Network Optimization
• Network don't cares can be used for minimizing
the intermediate nodes in a Boolean network .
• The new cost function minimizes a linear
combination of the number of product terms
and the weighted switching activity.
Common Sub-expression Extraction
• The major issue in decomposition is the identification of
common sub-expressions.
• Sharing of such expressions across the design reduces
the complexity of the synthesized network and its
implementation cost.
• Extraction based on algebraic division (using cube-free
primary divisors or kernels) has proven to be very
successful in creating an area-optimzed multi-level
Boolean network.
Figure: Logic decomposition for low power
Path Balancing
• Balancing path delays reduces hazards/glitches in the circuit
which in turn reduces the average power dissipation in the
circuit.
• This can be achieved before technology mapping by
selective collapsing and logic decomposition or after
technology mapping by delay insertion and pin reordering.
• Logic decomposition and extraction can be performed so as
to minimize the level difference between the inputs of
nodes which are driving high capacitive nodes.
Technology Decomposition
• This is the problem of converting a set of Boolean equations
(or a Boolean network) to another set (or another network)
consisting of only two-input NAND and inverter gates.
• It is difficult to come up with a NAND decomposed network
which will lead to a minimum power implementation after
technology mapping since gate loading and mapping
information are unknown at this stage.
• a decomposition scheme which minimizes the sum of the
switching activities at the internal nodes of the network
Cont
Figure Technology decomposition for low power
Technology Mapping
• Binding a set of logic equations (or a Boolean net work) to the
gates in some target cell library.
• The idea is to reduce technology mapping to DAG covering
and to approximate DAG covering by a sequence of tree
coverings which can be performed optimally using dynamic
programming.
• The general principle is to hide nodes with high switching
activity inside the gates where they drive smaller load
capacitances (see Figure).
Cont.. 13,37,46,51,409,
Figure Technology mapping for low power
Gate Resizing
• The treatment of gate sizing problem is closely related
to finding a macro-model which captures the main
features of a complex gate (area, delay, power
consumption) through a small number of parameters
(typically, width or transconductance).
PLA Minimization
• High speed PLAs are built by transforming the SOP
representation of a two level logic to the NOR-NOR structure
with inverting inputs and outputs and implementing it with
two NOR arrays.
• Two common types of implementing the NOR arrays are
pseudo-NMOS NOR gates and dynamic CMOS NOR gate.
• The primary source of power consumption for a pseudo-
NMOS NOR gate is the static power dissipation (see Figure)
Cont..
Figure : NOR-NOR PLAs
Signal-to-Pin Assignment
• library gates have pins that are functionally equivalent which
means that inputs can be permuted on those pins without
changing function of the gate output.
• These equivalent pins may have different input pin loads and pin
dependent delays.
• It is well known that the signal to pin assignment in a CMOS logic
gate has a sizable impact on the propagation delay through the
gate.
• To find the minimum power pin assignment for a gate g, one must
solve a difficult optimization problem
Low Power Arithmetic Components
• Low Power and High Speed in VLSI Circuits
• Minimizing power consumption is important due to higher integration
levels and portable devices.
• Arithmetic units often limit the overall system performance.
• Therefore, high-speed operation is also essential.
• Designers must balance low power dissipation and high speed.
• The optimal circuit architecture helps achieve this power–performance
trade-off.
Circuit Design Style
•CMOS circuits use static and dynamic design styles for digital circuit
implementation.
•Different design styles are analyzed for low power and high
performance arithmetic units.
•The full adder is a fundamental component used in arithmetic units
such as adders and ALUs.
•Seven different full adder circuits are designed using different CMOS
design styles.
•Each circuit is explained with circuit diagrams and basic operation.
•Performance of the full adders is evaluated individually.
•Further analysis is done by implementing them in a 16-bit Ripple Carry
Adder (RCA) to compare power, speed, and efficiency.
Static CMOS Full Adder
Full Adder Designs
1. Static Complementary CMOS Logic
• Uses both P-type and N-type logic trees.
• P-network charges the output high, N-network discharges
to ground.
• Requires both complemented and uncomplemented
inputs.
• Produces true and complemented Sum and Carry
outputs.
• Sum and Carry computed independently.
• Transistor count: 30.
NO RAce dynamic CMOS logic (NORA) Full Adder
2. NORA Dynamic CMOS Logic
• Uses alternating P-type and N-type logic stages.
• Carry output is dynamically precharged high.
• Sum output is dynamically pre-discharged low.
• Requires two-phase clock (ϕ and ϕ′).
• Does not require complemented inputs.
• Transistor count: 22.
Cascode Voltage Switch Logic (CVSL) Full Adder
3. Cascode Voltage Switch Logic (CVSL)
• A dynamic logic family using differential N-type
transistor trees.
• Requires two-phase clock, but no clock complement
needed.
• Outputs and complements are precharged high when
clock is low.
• When clock becomes high, one output is pulled low.
• Sum and Carry computed independently.
Differential Cascode Voltage Switch Logic (DCVSL) Full Adder
•DCVS logic is a static version of CVSL logic.
•Obtained by replacing P-type transistors with cross-
coupled P transistor pair.
•The cross-coupled P transistors act as a differential
pair.
•When one output is pulled low, the opposite P
transistor turns ON.
•This action pulls the other output high
automatically.
•Provides complementary outputs with stable
operation.
CMOS Non Threshold Logic (CNTL) Full Adder
•CNTL logic uses the same binary decision trees and cross-coupled
P transistors as DCVS.
•Additional N-type transistors are added to reduce output voltage
swing.
•Two N transistors placed between cross-coupled P transistors and
output to lower the high output voltage level.
•Two N transistors placed between N transistor tree and ground to
raise the low output voltage level.
•Shunt capacitors are added to reduce negative feedback.
•Reduced voltage swing → faster switching speed compared to
DCVS.
•Transistor count: 30, Capacitors: 4.
Enable / Disable CMOS Differential Logic (ECDL) Full Adder
•ECDL is an extension of the DCVS full adder.
•Uses a self-timing completion signal (DONE).
•When DONE = High, sum and carry outputs are pre-discharged.
•DONE becomes Low after the previous stage completes
computation.
•After DONE goes Low, the circuit operates like a normal DCVS
full adder.
•Improves timing control and synchronization between stages.
•Transistor count: 35.
Enhancement Source Coupled Logic (ESCL) Full Adder
• ESCL is a variation of the DCVS full adder.
• P-type transistors are replaced with biased N-type
transistors.
• Cross-coupled P transistors replaced by two N-type
transistors with bias voltage Vb.
• Bias voltage (Vb) ≈ Vdd − diode drop.
• A constant current source is inserted between the N-
transistor tree and ground.
• Inputs steer current between different branches of the
circuit.
• Current source implemented using a 2-transistor current
mirror.
Adders
• Power Dissipation Analysis of CMOS Adders
• In static CMOS, dynamic power mainly depends on the number of logic transitions.
• Fewer logic transitions → lower dynamic power consumption.
• Power also depends on switching speed, fan-in, fan-out, and output load.
• Methods Used for Power Estimation
• Gate-Level Simulation
• Adders built using AND, OR, NOT gates.
• Tested with 50,000 pseudo-random inputs.
• Average logic transitions per addition calculated.
• Circuit-Level Simulation
• 16-bit adders designed in 2-µm CMOS using MAGIC.
• Simulated using CAzM (similar to SPICE).
• Tested with 1,000 pseudo-random inputs.
• Physical Chip Measurement
• Chip fabricated with six 16-bit adders.
• Each adder has separate power pins to measure dynamic power directly.
• Chip size: 6400 × 4800 µm, 65 pins.
Adder Types
Full Adder
16 Bit Ripple Carry Adder
• Adders Analyzed
• Ripple Carry Adder (RCA)
• Carry Lookahead Adder (CLA)
• Carry Select Adder (CSA)
• Carry Skip Adder (CSK)
• Conditional Sum Adder
• Variable Block Width Carry Skip Adder
• Ripple Carry Adder
• Consists of N full adders connected in series.
• Carry propagates from LSB to MSB.
• Smallest and simplest design, but slowest due to carry delay.
16-Bit Carry
Lookahead
Adder
• Carry Lookahead Adder (CLA)
• Carry Lookahead Adder improves speed by reducing carry
propagation delay.
• The OR gate used for carry generation in the full adder is
removed.
• The adder uses only eight gates in the basic structure.
• Carry inputs are generated using lookahead logic blocks.
• Each block receives propagate (p) and generate (g) signals
from full adders.
• Four-bit lookahead modules are used to compute carries.
• Each lookahead module contains about 14 gates.
16-Bit Carry Select
Adder (CSA)
• Carry Select Adder (CSA)
• The Carry Select Adder is divided into k-bit blocks.
• Each block uses two Ripple Carry Adders.
• One adder assumes carry input = 0, the other assumes
carry input = 1.
• A multiplexer selects the correct output based on the
actual carry input.
• This method reduces carry propagation delay and
improves speed.
• Carry generation uses carry lookahead modules similar to
the Carry Lookahead Adder.
16 Bit Constant Block Width Carry Skip Adder
• Carry Skip Adder (CSK)
• Carry Skip Adder allows the carry to skip a block of bits when
propagate condition is satisfied.
• If corresponding input bits are different, the carry is passed to the
next stage.
• Uses blocks of bits with skip logic to improve speed.
• In Constant Block Width Carry Skip Adder, block size is determined
by a formula based on adder size.
• Uses single-level skip logic.
• For a 16-bit adder, the optimal block size is 3 bits.
16 Bit Variable Block Width Carry Skip Adder
• Variable Block Width Carry Skip Adder
• Uses variable block sizes to improve speed.
• Employs multiple levels of skip logic (2 or 3 levels).
• Turrini algorithm is used to determine optimal block grouping.
• Algorithm may produce an adder larger than required.
• Extra full adders and skip logic at MSB can be removed without
affecting delay.
• Provides faster performance than constant block width carry skip
adder.
8-Bit Conditional
Sum Adder
• Conditional Sum Adder (CSUM)
• Conditional Sum Adder uses 2:1 multiplexers.
• Combines larger blocks of conditional sum and carry bits recursively.
• Based on the Sklansky “H” cell structure.
• Inputs: two bits to be added.
• Produces four outputs:
• Sum and Carry for Carry-in = 0
• Sum and Carry for Carry-in = 1.
Number of Gates
Gate Level Simulation
16-Bit Adder Logic Transition Histogram 64-Bit Adder Logic Transition Diagram
• Gate-Level Simulation of Adders
• Gate-level simulator used to estimate average gate switching activity.
• Circuits are implemented in C subroutines and tested with pseudo-random
inputs.
• 50,000 input patterns are applied to each adder.
• For each addition, the number of gate transitions is counted.
• Ripple Carry, Carry Skip, and Carry Lookahead adders show similar
transition distributions.
• Carry Select Adder shows about twice the switching activity of
Ripple Carry.
• Conditional Sum Adder shows about three times the switching
activity.
• Higher switching activity → higher dynamic power consumption.
Circuit Simulation
• Circuit-Level Simulation Results (CAzM)
• 16-bit versions of six adders were designed in 2 µm CMOS using MAGIC.
• Netlists extracted from layout and simulated using CAzM (similar to
SPICE).
• Used to estimate worst-case delay and average power dissipation.
• Delay Analysis
• Worst-case delay measured by changing inputs from 0 to all 1s.
• Carry Skip Adder delay ≈ 15% faster than unit delay model estimate.
• Carry Lookahead & Carry Select Adders delay ≈ 20–25% slower due to
larger fan-in and fan-out.
• Conditional Sum Adder delay increases due to long signal paths.
Circuit Simulation
• Area and Gate Count
• Layout area varies about 6:1 across adders.
• Ripple Carry Adder uses single-row layout, others require multiple rows
and routing space.
• Power Dissipation
• Average power calculated using 1,000 pseudo-random inputs.
• Carry Skip Adder shows lower average power than Ripple Carry due to
faster current drop.
• Power vs. time curves are obtained by averaging current waveforms for
all additions.
Circuit Simulation
Size of 16·Bit Adders
Multipliers
• Power and Delay in Multipliers
• The impact of multiplier algorithms on power and delay.
• Most earlier research focused mainly on adders, with limited work on
multipliers.
• Chau and Powell studied power dissipation in VLSI processor arrays for
matrix multiplication.
• Their work focuses on efficient partitioning of algorithms across
processing elements.
• Power dissipation of adders has also been previously analyzed using
similar methods.
• Lemonds and Shetti showed that using latches to prevent glitches can
significantly reduce power in a 16×16 array multiplier.
One Cell of an Array
Multiplier
8-Bit Array Multiplier
Multiplier Types
• Array Multiplier and Modified Array Multiplier
• Multiplication can be implemented as repeated shift and add operations.
• Simple implementation uses an adder, shift register, and control logic.
• Advantage: small circuit size.
• Disadvantage: slow operation due to serial processing.
• Array Multiplier
• Forms partial products in parallel.
• Uses an N × N array of full adders to sum partial products.
• Cells include AND gates, full adders (FA), and half adders (HA).
• Has a regular structure and local interconnections, enabling dense layout.
• Delay increases with operand size due to diagonal carry propagation.
• Array Multiplier – Advantages
• Regular and simple structure
• Uses local interconnections (neighbor-to-neighbor)
• Easy to design and implement
• Produces compact and dense layout
• Array Multiplier – Disadvantages
• Long delay path (diagonal + ripple carry adder)
• Delay increases with operand size (N × N)
• Not suitable for high-speed applications
• Improvement Technique
• Replace ripple carry adder with Carry Lookahead Adder (CLA)
• Reduces propagation delay significantly
• Modified Array Multiplier
• Uses CLA instead of ripple carry adder
• Faster performance with slight increase in hardware
Performance Comparison
• 8-bit multiplier
• Delay reduced by ~10%
• Gate count increased by ~6%
• 32-bit multiplier
• Delay reduced by ~20%
• Gate count increased by ~1%
Modified Array Multiplier – Key Points
• Uses Carry Lookahead Adder (CLA) instead of ripple carry adder
• Power consumption ≈ same as ripple carry adder
• Only slight increase in gate count
• Significant reduction in delay
• Preferred over basic array multiplier
Why Modified Array Multiplier?
• Better speed performance
• Minimal hardware overhead
• Efficient trade-off between speed and area
Figure : 8-Bit Wallace
Tree Multiplier
Pseudo-Adder Concept
• Consists of N full adders (no carry chain)
• Adds 3 operands → produces 2 outputs
• Delay = only one full adder delay
Working of Wallace Tree
• Partial products are grouped in sets of 3
• Use pseudo-adders to reduce them step-by-step
• Forms a tree structure
• Final two outputs are added using a fast carry propagate adder
Advantages of Wallace Tree
• Very high speed (logarithmic delay)
• Efficient reduction of partial products
• Suitable for high-performance applications
Figure : 8-Bit
Dadda Multiplier
Dadda Multiplier
• Proposed by Dadda
• Improvement over Wallace tree multiplier
• Uses counters (full adders) to reduce partial products
• Key Idea
• Full adder acts as a counter (counts number of 1s)
• Outputs result in 2-bit binary form
• Matrix height reduced gradually (not aggressively)
• Reduction Strategy
• Height reduced by maximum factor ≈ 1.5 per stage
• Uses sequence:
2, 3, 4, 6, 9, 13, 19, 28, 42, 63
• At each stage → perform minimum required reduction
• Example: 8 × 8 Multiplier
• Reduction stages:
8→6→4→3→2
• Final 2 rows are added using Carry Propagate Adder (CPA)
• Dadda Structure
• Uses dot diagram representation
• Dots → partial product bits
• Ovals → inputs to half/full adders
• Lines → sum and carry outputs
• Comparison with Wallace Multiplier
• Uses fewer adders (area efficient)
• Slightly wider final CPA required
• Same worst-case delay as Wallace
• Disadvantages
• Less regular structure than Wallace
• More complex for VLSI layout design