0% found this document useful (0 votes)
3 views33 pages

Lecture 9 Routing Trace Width

Uploaded by

gopikarthi2005
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
3 views33 pages

Lecture 9 Routing Trace Width

Uploaded by

gopikarthi2005
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

PCB Design Process

Unit II
PCB Design Process
Introduction to ESDM

Progress Through Quality Education


PCB Design Process

Progress Through Quality Education 2


PCB Design Process
• Board type: Single-layer / 2-layer / 4-layer / Multilayer
• Electrical constraints:
o Voltage levels
o Current capacity
o Controlled impedance (if any)
• Mechanical constraints:
o Board size and shape
o Mounting holes
o Connector locations

Progress Through Quality Education 3


PCB Design Process
• Manufacturing constraints:
oMinimum trace width/spacing
oDrill sizes
oStack-up (FR4, copper thickness)
• Compliance:
oIPC class (Class 2 / Class 3)
oEMI/EMC considerations

Progress Through Quality Education 4


PCB Design Process
Schematic Capture (Cadence OrCAD Capture)
Create a New Project
[Link] OrCAD Capture
[Link] → New → Project
[Link] PCB Design project
[Link] project directory and name
[Link] Blank Project or Template
Create / Verify Libraries
•Symbol libraries (.olb)
•Footprint libraries (.dra / .psm)

Progress Through Quality Education 5


PCB Design Process
2.3 Schematic Entry
•Place components (Place → Part)
•Draw nets (Place → Wire)
•Use net aliases for clarity
•Add:
Power symbols
o

Ground symbols
o

Test points (recommended)


o

Progress Through Quality Education 6


PCB Design Process

Electrical Rule Check (ERC)


Tools → Electrical Rules Check
[Link]:
o Unconnected pins
o Missing power pins
o Multiple drivers
[Link] schematic

Progress Through Quality Education 7


PCB Design Process
Netlist Generation for Allegro • Select:
• Annotate Design Allegro
o

• Tools → Annotate • Configure:


• Ensure reference designators are unique Output directory
o

• Create Allegro Netlist Netlist format


o

• In Allegro PCB design software, Create Netlist generates a text- [Link] netlist
based file, typically used to export connectivity data from a
schematic (such as OrCAD Capture) into the PCB Editor Output files:
• Tools → Create Netlist •.brd (board file – if board creation is enabled)
•.[Link]
•Constraint data (optional)

Progress Through Quality Education 8


PCB Design Process

Key Functions of "Create Netlist" in Allegro:


•Transfer Schematic to Layout: It converts schematic drawings into a format the PCB editor
understands, creating a list of components and nets.
•Initial Board Setup: Acts as the starting point for PCB layout by defining all electrical
connections between component pins.
•Design Synchronization: It updates existing PCB designs (.brd files) with changes made in the
schematic (e.g., adding components, changing connections).
•Error Checking: The process verifies the schematic for, or highlights, inconsistencies or errors in
connectivity before generating the final netlist file.
•Format Flexibility: It can generate different formats, such as Allegro's native format or industry-
standard formats, and is crucial for creating the "package" required for board layout.

Progress Through Quality Education 9


PCB Design Process
Board Creation in Allegro PCB Editor
Open Allegro PCB Editor
•Launch Allegro PCB Editor
•Open the generated .brd file
(or create a new board and import netlist)
Define Board Outline
[Link] → Design Parameters → Design Outline
[Link] board shape using:
Line / Arc tools
o

[Link]:
Origin
o

Datum points
o

Progress Through Quality Education 10


PCB Design Process
Stack-Up Definition
5.1 Define Cross-Section
[Link] → Cross Section
[Link]:
o Number of layers
o Copper layers (TOP, BOTTOM, INNER)
o Dielectric thickness
o Copper thickness
[Link] layer types:
o SIGNAL
o PLANE
o DIELECTRIC
Mandatory before routing

Progress Through Quality Education 11


PCB Design Process
Footprint Placement
6.1 Import Components
• Components appear outside the board outline initially
6.2 Placement Process
[Link] → Manually
[Link]:
o Connectors first
o Large ICs
o Power components
o Sensitive analog parts
[Link]:
o Orientation consistency
o Assembly clearances
o Thermal considerations

Progress Through Quality Education 12


PCB Design Process
Constraint Setup (DRC Rules)
7.1 Physical Constraints
[Link] → Constraints → Physical
[Link]:
o Trace width
o Spacing
o Via sizes
7.2 Electrical Constraints (Optional)
• Differential pairs
• Impedance control
• Length matching
7.3 Manufacturing Constraints
• Solder mask expansion
• Minimum annular ring
• Drill tolerances

Progress Through Quality Education 13


PCB Design Process

Routing
Track Width in PCB Design (IPC-2221A)
Why Track Width Matters
A PCB track is a flat copper conductor. Its width governs:
. Current capacity: how much continuous current it can carry for a chosen
temperature rise.
. Voltage drop & power loss: resistance depends on cross-sectional area.
. Reliability: undersized traces overheat → delamination, darkening, electromigration.
. Manufacturability: very ne tracks increase cost and fabrication difficulty.

Progress Through Quality Education 14


PCB Design Process

Parameters Affecting Track Width


1. Copper thickness (t): specified in oz/ft2. 1 oz ≈ 35 μm ≈ 1.37 mil.
Thicker copper → higher current for same width.
2. Current (I): continuous (RMS) current for thermal sizing.
3. Temperature rise (ΔT): allowable rise, typically 10 – 30 deg ºC.
4. Layer position: external traces (top/bottom) cool better than internal ones

Progress Through Quality Education 15


PCB Design Process

Progress Through Quality Education 16


PCB Design Process

Progress Through Quality Education 17


PCB Design Process

Progress Through Quality Education 18


PCB Design Process

Progress Through Quality Education 19


PCB Design Process

Progress Through Quality Education 20


PCB Design Process

Progress Through Quality Education 21


PCB Design Process

Progress Through Quality Education 22


PCB Design Process

Progress Through Quality Education 23


PCB Design Process
Key points:
. External layers require more clearance (risk of arcing in air).
. Internal layers can be tighter (dielectric provides isolation).
Additional Considerations
. Creepage distance: along a surface, spacing may need to increase with contamination or
pollution degree.
. Environment: harsh conditions (humidity, altitude, pollution) demand larger clearances.
. Manufacturability: even if IPC allows small spacing, PCB fabricators often limit to 56 mil in low-
cost processes.
. Safety standards: stricter rules apply for medical, automotive, or aerospace designs (IEC-60950,
UL, ISO).
Example
For a 48 V DC power stage on an external layer:
. IPC-2221A requires 0.6 mm spacing.
. On an internal layer, only 0.1 mm spacing is required.
Progress Through Quality Education 24
PCB Design Process

IPC-2221A vs IPC-2221B / IPC-2222


. IPC-2221A is a legacy standard.
. IPC-2221B and IPC-2222 move toward performance-based rules and
reference
IPC-9592B for power electronics.
. Modern designs often cross-check IPC with IEC-60664 or UL-60950.

Progress Through Quality Education 25


PCB Design Process
Routing
8.1 Manual / Auto Routing
• Manual routing:
o Route → Connect
• Auto routing (if used):
o Route → Automatic
Recommended:
• Power & ground first
• High-speed signals next
• Remaining signals last
• 8.2 Via Optimization
• Reduce via count
• Avoid stubs
• Maintain return paths

Progress Through Quality Education 26


PCB Design Process

Guidelines for Component Placement


Derived from industry standards (IPC-2221A, IPC-7351) and good design practices

1. Start with Constraints


. Place connectors and mechanical components first, based on chassis or enclosure
requirements.
. Ensure mounting holes, heatsinks, displays, and external ports align with the product
housing.

Progress Through Quality Education 27


PCB Design Process

2. Functional Grouping
. Place components in functional blocks (power, analog, digital, RF).
. Keep related parts close together to minimize trace lengths.
. Arrange blocks in a logical order to match signal flow.

Progress Through Quality Education 28


PCB Design Process

3. Power Supply Placement


. Place power regulators, SMPS ICs, and associated passives near the input connector.
. Minimize the loop area of switching nodes (hot loop).
. Keep decoupling capacitors as close as possible to IC power pins .

Progress Through Quality Education 29


PCB Design Process
Design Rule Check (DRC)
9.1 Run DRC
[Link] → Design Rule Check
[Link]: Spacing violations, Unrouted nets, Short circuits

Progress Through Quality Education 30


PCB Design Process
10. Pre-Manufacturing Checks
10.1 Artwork Review
• Silkscreen overlaps
• Polarity markings
• Reference designator visibility
10.2 Drill Check
• Tool sizes
• Plated vs Non-plated holes
10.3 Copper Balance
• Plane fill
• Acid traps
• Thermal reliefs

Progress Through Quality Education 31


PCB Design Process
Gerber File Generation 11.2 Generate Gerbers
11.1 Setup Artwork Parameters [Link] format:
[Link] → Artwork o RS-274X (Extended Gerber)
[Link]:
[Link]:
Line width
Film control
o

o Units (mm / inch)


o Layers to output:
o Polarity
Top Copper

[Link] Create Artwork
Bottom Copper

Generated files:
Inner layers
▪ .GTL – Top Copper

Solder mask

.GBL – Bottom Copper
.GTS – Top Solder Mask
Silkscreen

.GBS – Bottom Solder Mask


.GTO – Top Silkscreen

Progress Through Quality Education 32


PCB Design Process
NC Drill File Generation Final Manufacturing Outputs 14. Gerber Verification (Highly
12.1 Generate Drill Data 13.1 Complete Fabrication Recommended)
[Link] → NC → NC Drill Package Tools:
[Link]: •Gerber files • Gerbv
o Plated / Non-plated • NC Drill files • ViewMate
o Tool sizes • IPC-356 Netlist • CAM350
[Link]: • Readme / Fab notes • Online Gerber viewers
o .drl, Drill report • Stack-up drawing Check:
• BOM (from Capture) • Layer alignment
• Missing features
• Correct polarity

Progress Through Quality Education 33

You might also like