1 Number Systems

Classroom Practice Questions (CPQs) Q.8 Find the value of x.

Q.1 The decimal equivalent of binary number (135) x + (144 )8 = ( 214 ) x+ 2

10110.11 is _____. Q.9 What is the base or radix for the following
Q.2 Convert the octal number 0.4051 into its expression? ( 224 )r = (13)r
equivalent decimal number.
Q.10 What are the values respectively, of R1 and
(A) 0.5100098 (B) 0.2096
R2 in the expression ( 235) R1 = ( 565)10
(C) 0.52 (D) 0.4192
Q.3 The decimal equivalent of hexadecimal = (1065 ) R 2
number of 2A0F is _______ (A) 8, 16 (B) 16, 8
Q.4 If 73x (in base-x number system) is equal (C) 6, 16 (D) 12, 8
to 54 y (in base-y number system), the Q.11 The binary representation of the decimal
possible values x and y are? number 1.375 is,

(A) 8, 16 (B) 1, 12 (A) 1.111 (B) 1.010

(C) 9, 13 (D) 8, 11 (C) 1.011 (D) 1.001

Q.12 The representation of the decimal number
Q.5 Consider the equation (123 )5 = ( x8 ) y with
( 27.625)10 in base-2 number system is
x and y as unknown. The Number of
possible solutions is ____? (A) 11011.110 (B) 11101.101
(C) 11011.101 (D) 10111.110
Q.6 If (1235 ) x = ( 3033) y where x and y
Q.13 If (11x1y )8 = (12C 9 )16 then the values x
indicate bases of the corresponding
numbers, then and y are
(A) x = 7 and y = 5 (A) 3 and 1 (B) 5 and 7
(C) 7 and 5 (D) 1 and 5
(B) x = 8 and y = 6
Q.14 What is the base of the numbers for the
(C) x = 6 and y = 4 following operation to be correct?
(D) x = 9 and y = 7 (54)b
= (13)b
Q.7 For radix r, decimal value of (110 )r is 4r (4)b

then r is ______ and decimal value of (A) 2 (C) 4

( 010 )r is __? (D) 8 (C) 16

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Digital Electronics [SSC-JE & All State AE/JE] 2 GATE ACADEMY®
Q.15 How many 1’s are present in the binary (A) 25, 9 and 57 respectively
representation of (B) – 6, – 6 and – 6 respectively
( 4 × 4096) + ( 9 × 256) + ( 7 ×16) + 5 ? (C) – 7, – 7 and – 7 respectively
(D) – 25, – 9 and – 57 respectively
(A) 8 (B) 9
Q.23 A number in 4-bit two’s complement
(C) 10 (D) 11
representation is X 3 X 2 X 1 X 0 .This number
Q.16 The hexadecimal representation of ( 657 )8
when stored using 8 – bits will be
is:
(A) 0000X 3 X 2 X 1 X 0
(A) 1AFH (B) D78H
(B) 1111X 3 X 2 X 1 X 0
(C) D71H (D) 32FH
Q.17 The BCD code for a decimal number (C) X 3 X 3 X 3 X 3 X 3 X 2 X 1 X 0

(874)10 is (D) X 3 X 3 X 3 X 3 X 3 X 2 X 1 X 0

(A) (100001110100 ) BCD Q.24 The two numbers represented in signed 2’s
implement form are
(B) ( 010001111000 ) BCD P = 11101101 and Q = 11100110
(C) (100001000111) BCD If Q is subtracted from P, the value obtained
in signed 2’s complement form is
(D) ( 011110000100 ) BCD (A) 100000111 (B) 00000111
Q.18 The result of ( 45)10 − ( 45)16 expressed in (C) 11111001 (D) 111111001
2’s complement representation is Q.25 X = 01110 and Y = 11001 are two 5 - bit
binary numbers represented in two’s
(A) 011000 (B) 100111
complement format. The sum of X and Y
(C) 101000 (D) 101001 represented in 2’s complement format
Q.19 The 2’s complement representation of –17 using 6 - bit is
is [UPSC ESE 2019] (A) 100111 (B) 001000
(A) 101110 (B) 101111 (C) 000111 (D) 101001
(C) 111110 (D) 110001 Q.26 Let A and B be the two 8 bit 2’s
Q.20 An 8-bit 2’s complement representation of complement numbers
an integer is FA (Hex). Its decimal A = 1111 1010
equivalent is B = 0000 1010
(A) −10 (B) −6 Their product in 2’s complement is
(C) + 6 (D) +10 (A) 1100 0100
Q.21 Two 4-bit 2’s complement numbers 1011 (B) 1001 1100
and 0110 are added. The result expressed in (C) 1010 0101
4-bit 2’s complement notation is
(D) 1101 0101
(A) 0001 Q.27 2’s complement of a number is 100, then
(B) 0010 find the number.
(C) 1101 (A) + 4 (B) − 4
(D) Cannot be expressed in 4-bit 2’s (C) 0 (D) − 8
complement Q.28 4 bit 2’s complement representation of a
Q.22 11001, 1001 and 111001 correspond to the decimal number 1000. The number is,
2’s complement representation of which (A) + 8 (B) − 7
one of the following sets of number? (C) 0 (D) – 8

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GATE ACADEMY® 3 Number Systems
Q.29 The smallest integer that can be represented Q.4 Binary 1011001 is equal to
by an 8 bit number in 2’s complement form (A) 89decimal
is (B) 100decimal
(A) – 256 (B) – 128 (C) 900decimal
(C) – 127 (D) 0 (D) None of the above
[UPPSC EE 2019] Q.5 The decimal equivalent of binary 110.001
Q.30 Decimal equivalent of the hexadecimal is
number E5 is (A) 6.25 (B) 6.125
(A) 279 (B) 229 (C) 62.5 (D) 0.612
(C) 427 (D) 3000 [UPSC ESE 2015]
[STATE ESE EE] Q.6 2's complement of the number of 1010101
Q.31 Which of the following is an invalid state in is
8-4-2-1 Binary coded Decimal counter: (A) 0101010 (B) 0101011
(A) 1 0 0 0 (B) 1 0 0 1 (C) 1101010 (D) 1110011
(C) 0 0 1 1 (D) 1 1 0 0 Q.7 Consider the following statements:
[STATE ESE EE] 1. When two unsigned numbers are added,
Q.32 In 2’s complement representation the an overflow is detected from the carry
number 11100101 represents the decimal into the most significant position.
Number 2. An overflow does not occur if the two
numbers added are both negative.
(A) +37 (B) -31
3. If the carry into the sign bit position and
(D) + 27 (C) -27
carry out of the sign bit position are not
[STATE ESE EE] equal, an overflow condition is
Q.33 Binary subtraction of a decimal 15 from 43 produced.
will utilize which 2’s complement? Which of the above statement(s) is/are
(A) 101011 (B) 110000 correct?
(C) 110001 (D) 011100 (A) 1, 2 and 3. (B) 1 only,
[STATE ESE EE] (C) 2 only. (D) 3 only.
Self-Practice Questions (SPQs) [UPSC ESE 2015]
Q.8 In signed magnitude representation, the
Q.1 Which one of the following is correct?
binary equivalent of 22.5625 is (the bit
The convention is that the number 0 has the before comma represents the sign)
normal form representation as
(A) 0, 10110.1011
(A) 0 (B) .0
(B) 0, 10110.1001
(C) 0.0 (D) 0.10°
(C) 1, 10101.1001
[UPSC ESE 2008] (D) 1, 10110.1001
Q.2 The 9's complement of (25.639)10 is [UPSC ESE 2002]
(A) 74.360 (B) 0.6732 Q.9 A number is expressed in binary two's
(C) 6.732 (D) 7.436 complement as 10011. Its decimal
[UPSC ESE 2015] equivalent value is
Q.3 The binary equivalent of (11.6275)10 is (A) 19 (B) 13
(A) 101.11011 (B) 1011.1011 (C) –19 (D) –13
(C) 101.0011 (D) 1011.0011 [UPSC ESE 2002]
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Digital Electronics [SSC-JE & All State AE/JE] 4 GATE ACADEMY®
Q.10 Binary data is being represented in size of Q.19 The decimal equivalent of hexadecimal
byte, and in 2's complement form. The number 2A0F is
number of 0's present in representation of (– (A) 17670 (B) 17607
127) Decimal (C) 17067 (D) 10767
(A) 8 (B) 7 [UPSC ESE 2002]
(C) 6 (D) 5 Q.20 Hexadecimal conversion of decimal
[UPSC ESE 2012] number 227 will be
Q.11 Which one of the following is not a valid (A) A3 (B) E3
octal number? (C) CC (D) C3
(A) 1101 (B) 740 [UPSC ESE 2013]
(C) 970 (D) 220 Q.21 The addition of the two numbers (1A8)16 +
Q.12 The number (149)10 in octal code will be (67B) 16 will be
(A) 225 (B) 254 (A) (889)16 (B) (832)16
(C) 252 (D) 1472 (C) (823)16 (D) (723)16
Q.13 The decimal equivalent of (1431)8 is [UPSC ESE 2017]
(A) 793 (B) 739 Q.22 The Octal equivalent of the HEX number
(C) 379 (D) 397 [Link] is
Q.14 Convert the decimal 41.6875 into octal (A) 253.314 (B) 253.632
(A) 51.54 (B) 51.13 (C) 526.314 (D) 526.632
(C) 54.13 (D) 51.51 Q.23 What is the octal equivalent of FF6?
[UPSC ESE 2015] (A) 255 (B) 377
Q.15 What is the octal equivalent of (C) 256 (D) 11111111
(5621.125)10?
Q.24 The subtraction of two hexadecimal
(A) 11774.010 (B) 12765.100 numbers 8416 — 2A16 results in
(C) 16572.100 (D) 17652.010 (A) 2B16 (B) 3A16
[UPSC ESE 2017] (C) 4B16 (D) 5A16
Q.16 The binary representation of 100110 is
[UPSC ESE 2016]
numerically equivalent to:
Q.25 BCD code is
(A) The decimal representation of 46.
(A) A binary code.
(B) The octal representation of 46.
(B) Unweighted code.
(C) The octal representation of 26.
(C) The same thing as binary numbers.
(D) The decimal representation of 26.
(D) The same as Gray code.
[UPSC ESE 2003]
Q.26 Which one of the following is a non-valid
Q.17 The decimal equivalent of the hexadecimal
BCD code?
number (BAD) u is
(A) 01111001. (B) 01011011.
(A) 111013 (B) 5929
(C) 0100 1000. (D) 0100 1001.
(C) 3416 (D) 2989
[UPSC ESE 1998]
Q.18 The binary equivalent of hexadecimal
number 4F2D is Q.27 Which of the following is an invalid state in
an 8-4-2-1 Binary Coded Decimal counter
(A) 01011111 0010 1100
(A) 1 00 0 (B) 1001
(B) 0100 1111 0010 1100
(C) 00 11 (D) 1100
(C) 0100 1110 0010 1101
(D) 0100 1111 0010 1101 Q.28 The BCD code for a decimal number
(874)10 is
[UPSC ESE 2002]
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GATE ACADEMY® 5 Number Systems
(A) (100001110100)BCD Q.35 What is the Gray code word for the binary
(B) (010001111000)BCD number 101011?
(C) (100001000111)BCD (A) 101011 (B) 110101
(D) (011110000100)BCD (C) 011111 (D) 111110
[UPSC ESE 2013] [UPSC ESE 2006]
Q.29 The excess-3 code is also known as Q.36 (24)8 is expressed in Gray code as which
one of the following?
(A) Weighted code.
(A) 11000 (B) 10100
(B) Cyclic redundancy code.
(C) 11110 (D) 11111
(C) Self-complementing code.
[UPSC ESE 2008]
(D) Algebraic code.
Q.37 The binary representation 100110 is
Q.30 An Excess-3 code arithmetic operation is
numerically equivalent to the
used to perform the
1. Decimal representation 46.
(A) Binary addition.
2. Octal representation 46.
(B) Binary subtraction,
3. Hexadecimal representation 26.
(C) BCD addition.
4. Excess-3 representation 13.
(D) BCD subtraction.
Select the correct answer using the codes
[UPSC ESE 2015] given below.
Q.31 Which of the following statements is/are Codes:
correct in regard to excess 3 code?
(A) 1 and 2 (B) 2 and 3
(A) It is a BCD code.
(C) 1 and 3 (D) 2 and 4
(B) It is an unweighted code.
Q.38 If (2.3)base 4 + (1.2)base 4 = ( y )base 4 ; what is
(C) It is a self-complementing code.
the value of y?
(D) All of the above.
(A) 10.1 (B) 10.01
Q.32 Which of the following is a self-
(C) 10.2 (D) 1.02
complementing code?
[UPSC ESE 2005]
(A) 8421 code.
Q.39 How many bits are required to represent
(B) Excess-3 code, decimal value from -50 to 50?
(C) Pure binary code. (A) At least seven bits.
(D) Gray code. (B) At least six bits,
[UPSC ESE 2002] (C) At least eight bits.
Q.33 The 4-bit group that is used in excess 3 code (D) A least ten bits.
is
Q.40 The most negative number that can be
(A) 1010 (B) 0011 represented by an 8 bit signal 2's
(C) 1100 (D) 1110 complement system is
Q.34 A Gray code is a/an: (A) –12710 (B) –12810
(A) Binary weighted code. (C) –6410 (D) –25610
(B) Arithmetic code. Q.41 The range of signed decimal numbers that
(C) Code which exhibits a single bit change can be represented by 6-bit l's complement
between two successive codes. number is
(D) Alphanumeric code. (A) –31 to + 31 (B) –63 to + 64
[UPSC ESE 2005] (C) –64 to + 63 (D) – 32 to + 31

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Digital Electronics [SSC-JE & All State AE/JE] 6 GATE ACADEMY®
Q.42 2's complement representation of a 16-bit Q.46 Which of the following notations have two
number (one sign bit and 15 magnitude representations of zero?
bits) is FFFF. Its magnitude in decimal 1. 1’s complement with radix of number
representation is being 2.
(A) 0 (B) 1 2. 7's complement with radix of number
(C) 32,767 (D) 65,535 being 8.
Q.43 The largest binary number that can be 3. 9's complement with radix of number
obtained using 16-bits is being 10.
(A) 65536 (B) 65535 4. 10's complement with radix of number
(C) 32768 (D) 32767 being 10.
Q.44 How many possible combinations of input Select the correct answer using the code
variables exist in a 4-variable expression? given below
(A) 8 (B) 10 (A) 1, 2 and 4. (B) l and 3.
(C) 16 (D) 24 (C) 2, 3 and 4." (D) 1, 2 and 3.
Q.45 The number of one's present in the binary [UPSC ESE 2005]
representation of 15 × 256 + 5 ×16 + 3 are
(A) 8 (B) 9
(C) 10 (D) 11
[UPSC ESE 2014]

Answer Keys

Classroom Practice Questions

1. 22.75 2. A 3. 10767 4. D 5. 3
6. B 7. 3, 3 8. 7 9. 5 10. B
11. C 12. C 13. A 14. D 15. A
16. A 17. A 18. C 19. B 20. B
21. A 22. C 23. C 24. B 25. C
26. A 27. B 28. D 29. B 30. B
31. C 32. D 33. D
Self Practice Questions
1. C 2. A 3. B 4. A 5. B
6. B 7. D 8. B 9. D 10. C
11. C 12. A 13. A 14. A 15. B
16. B 17. D 18. D 19. D 20. B
21. C 22. B 23. B 24. D 25. A
26. B 27. D 28. A 29. C 30. D
31. D 32. B 33. B 34. C 35. D
36. C 37. B 38. A 39. A 40. B
41. A 42. B 43. D 44. C 45. A
46. D

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 2 Logic Gates
& Switching Circuits

Classroom Practice Questions (CPQs) Q.4 Which one of the following figures
represents the coincidence logic ?
Q.1 (FE35)16 XOR(CB15)16 is equal to (A)
A
(A) (3320)16 (B) (FF35)16
B
(C) (FF50)16 (D) (3520)16
F
Q.2

A
(B) A
B
B F F
A

B
(C) A
B
The circuit shown above is functionally
F
equivalent to
(A) NOR gate (B) OR gate
(C) EX-OR gate (D) NAND gate
(D) A
Q.3 Consider the following logic circuit :
B
A
F
B

Q.5
F A
C

B F
What is the required input condition (A, B,
C) to make the output x = 1, for the above
logic circuit ? C
(A) (1, 0, 1) (B) (0, 0, 1) Which one of the following circuits is the
minimized logic circuit for the circuit
(C) (1, 1, 1) (D) (0, 1, 1)
shown in figure.
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Digital Electronics [SSC-JE & All State AE/JE] 8 GATE ACADEMY®
(A) (B)
A A
Q.10 The logic function f = x . y + x . y is the
B F B F same as :
C C (A) f = (x + y) (x + y)

(B) f = (x + y) (x + y)
(C)
© (D)
A A (C) f = (x . y) (x . y)
B F B F (D) None of the above
C C Q.11 Match the logic gates in Column A with
Q.6 If the output of a logic gate is '1' when all their equivalents in Column B.
its input are at logic '0’ the gate is either Column A Column B
(A) a NAND or a NOR P. 1.
(B) an AND or an X-NOR
(C) an OR or a NAND Q. 2.
(D) an X-OR or an X-NOR
Q.7 How is inversion achieved using EX-OR R. 3.
gate?
(A) Giving input signal to the input lines of S. 4.
the gate tied together
(B) Giving input to one input line and logic Codes : P Q R S
zero to the other line (A) 2 4 1 3
(C) Giving input to one input line and logic (B) 4 2 1 3
one to the other line (C) 2 4 3 1
(D) Inversion cannot be achieved using (D) 4 2 3 1
EX-OR gate Q.12 In the figure shown, the output Y is required
Q.8 Match List-I with List-II and the select the to be Y = AB + C D . The gates G1 and G2
correct answer using the codes given below must be,
the lists :
A
List - I List - II
G1
A. A⊕B = 0 1. A≠B
B Y
B. A+B=0 2. A=B G2
C. A.B=0 3. A = 1 OR B = 1
C
D. A ⊕ B =1 4. A = 1 OR B = 0 D
Codes: (A) NOR, OR (B) OR, NAND
A B C D (C) NAND, OR (D) AND, NAND
(A) 3 2 1 4 Q.13 For the circuit shown below the output F is
(B) 2 3 4 1 given by
X
(C) 3 2 4 1
(D) 2 3 1 4 F

Q.9 Which of the following logic expressions

is incorrect?
(A) 1 ⊕ 0 = 1 (B) 1 ⊕ 1 ⊕ 1 = 1 (A) F = 1 (B) F = 0
(C) 1 ⊕ 1 ⊕ 0 = 1 (D) 1 ⊕ 1 = 0 (C) F = X (D) F = X

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GATE ACADEMY® 9 Logic Gates & Switching Circuits
Q.14 If the input to the digital circuit consisting The circuit shown above is to be used to
of a cascade of 20 X-OR gates is X, then the implement the function Z = f (A, B) = A+B
output Y is equal to . The values of I and J are :
1 (A) I = 0 and J = B
(B) I = 1 and J = B
Y
(C) I = B and J = 1
X (D) I = B and J = 0
(A) 0 (B) 1 Q.18 Consider the following gate network :
(C) X (D) X
W 1
Q.15 Boolean equation for the following truth
table is:
2 4 F
X Y Z F
X
0 0 0 0
0 0 1 1 Y 5
3
0 1 0 0 Z
0 1 1 1
1 0 0 1 Which one of the following gates is
redundant ?
1 0 1 0
1 1 0 1 (A) Gate No. 1
1 1 1 0 (B) Gate No. 2
(C) Gate No. 3
(A) F= yz' + y'z
(D) Gate No. 4
(B) F = xy' + x'y
Q.19 Which one of the following logical
(C) F = x'z + xz'
operations is performed by the digital
(D) F = x'z + xz' + xyz
circuit shown below ?
Q.16 Find the Boolean expression for the logic A
circuits shown below:
(1-NAND gate, 2- NOR gate, 3- NOR gate)
A
1
B B
(A) NOR (B) NAND
3 Y
(C) EX-OR (D) OR
Q.20 For the logic circuit given above, what is
2 the simplified Boolean function?

(A) AB (B) AB
(C) A B (D) A B
Q.17
I J

(A) X = AB + C (B) X = BC + A
A
(C) X = AB + AC (D) X = AC + B
Z
Q.21 Assume that only x and y logic input are
available, and their complements
( s + 1)( s + 2) = 0 and  are not available.
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Digital Electronics [SSC-JE & All State AE/JE] 10 GATE ACADEMY®
What is the minimum number of 2-input Q.26 The minimum number of NAND gates
NAND gates required to implement required to implement A + AB + ABC is
s = −1, − 2 ? equal to
(A) 2 (B) 3 (A) Zero (B) 1
(C) 4 (D) 5 (C) 4 (D) 7
Q.22 The output of the circuit shown in the figure Q.27 The minimum number of gates required to
is equal to realize the function AB + C (Using NAND
A gates only) is
B (A) 2 (B) 3
OUTPUT
(C) 4 (D) 6
A Q.28 The output of a NOR gate is :
B (A) High if all of its inputs are high
(A) 0 (B) 1 (B) Low if all of its inputs are low
(C) A B +A B (D) (A * B) *(A * B) (C) High if all of its inputs are low
(D) High of only one of its inputs is low
Q.23 Which of the following are universal gates?
Q.29 For the circuits shown in figure , taking
1. NAND open as ‘0’ and closed as ‘1’, the output
2. NOR expressions Y is given as
3. XOR A B C

Select the correct answer from the codes

D
given below:
(A) 1 and 2 only (B) 1 and 3 only
(C) 2 and 3 only (D) 1, 2 and 3 Y
Q.24 In NOR-NOR configuration, the minimum (A) A(B+C+D) (B) A(BC+D)
number of NOR gates needed to implement (C) A+(B+C)D (D) A+B+C+D
the switching function X+ XY+ XYZ is : [GSECL VS JE EE]
(A) 5 (B) 3 Q.30 For the circuits shown in figure, the output
functions Y is ____.
(C) 2 (D) 0 A
Q.25 B
A
C
Y
B D
E
C
(A) Y =AB+C (D+E)
X
D (B) Y = AB+C+DE
(C) Y = ABC + DE
E
(D) Y = (A + B) C + DE
F [GSECL VS JE EE]
The output X of the above logic circuit is: Q.31 The output of logic gate is 1 when all of its
(A) AB + CD + EF input are at logic 0. The gate is either
(A) a NAND or an EX-OR
(B) AB + CD + EF (B) an OR or an EX-NOR
(C) (A+B) ⋅ (C+D) ⋅ (E+F) (C) an AND or an EX-OR
(D) (A+B) ⋅ (C+D) ⋅ (E+F) (D) a NOR or an EX-NOR
[UPPSC AE 2019, STATE ESE EE]
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GATE ACADEMY® 11 Logic Gates & Switching Circuits
Q.32 The minimum number of 2-input NAND Q.39 The circuit shown in following figure is a
gates required to realize the logic function +5 V

Y = AB + AB is
R
(A) 5 (B) 3
(C) 6 (D) 4 A

[UPPSC AE 2019] B Y
Q.33 Which of the following expressions does C
NOT represent exclusive NOR of x and y?
(A) xy + xy (B) x ⊕ y (A) 3-input AND gate
(C) x ⊕ y (D) x ⊕ y (B) 3-input OR gate
[UPPSC AE 2019] (C) 3-input NAND gate
(D) 3-input NOR gate
Q.34 The minimum number of NAND gates
required to implement AB + CD is equal to [STATE ESE EE]
(A) 3 (B) 1 Self-Practice Questions (SPQs)
(C) 4 (D) 7 Q.1 A logic gate is an electronic circuit which
[STATE ESE EE] (A) Operates on binary algebra.
Q.35 The output X of the OR gate show in figure (B) Performs arithmetic and logic
is functions.
l (C) Allows flow of electrons only in one
l X direction.
l (D) Alternates between 0 and 1 values.
(A) 1 (B) 2 Q.2 Positive logic in a logic circuit is one in
which
(C) 0 (D) 3
(A) Logic 0 and 1 are represented by 0 and
[STATE ESE EE]
positive voltage respectively.
Q.36 The most suitable gate for comparing two
(B) Logic 0 and 1 are represented by the
bit is
negative and positive voltages
(A) AND gate (B) OR gate respectively.
(C) NAND gate (D) EX-OR gate (C) Logic 0 voltage level is higher than
[STATE ESE EE] logic 1 voltage level.
Q.37 The minimum number of 2-input NAND (D) Logic 0 voltage level is lower than logic
gates required to construct one 4-input 1 voltage level.
NAND gate is Q.3 The logic is said to be positive if
(A) 2 (B) 3 (A) Upper level is 0, lower is 1.
(C) 4 (D) 5 (B) Lower level is 0, upper is 1.
[STATE ESE EE] (C) Two levels overlap
Q.38 A bulb is controlled by two switches A and (D) Both (a) and (b) are true.
B. The bulb glows only when either switch Q.4 The voltage levels of a negative logic
A or switch B is ON. Its Boolean expression system
is (A) Must necessarily be negative.
(A) AB + AB (B) AB + AB (B) May be negative or positive.
(C) AB + AB (D) A B + AB (C) Must necessarily be positive.
(D) Must necessarily be 0 V and-5 V.
[STATE ESE EE]
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Digital Electronics [SSC-JE & All State AE/JE] 12 GATE ACADEMY®
Q.5 In the negative logic system, A
(A) The more negative of the two logic C
levels represents a logic '1' state.
B 0= 0V
(B) The more negative of the two logic
1= –5V
levels represents a logic '0' state.
(C) All input and output voltage levels are –5V
negative. (A) OR gate. (B) AND gate.
(D) The output is always complement of the (C) NOR gate. (D) NAND gate.
intended logic function. Q.13 An AND gate
Q.6 If L = low, H = high, a positive logic is (A) Implements logic addition.
(A) L = 5V, H = 0V (B) Gives high output only when all inputs
(B) L = 5V, H = -5V are low.
(C) L = 5V, H=1V (C) Is equivalent to a series switching
circuit.
(D) L = -5 V, H = -1 V
(D) Is equivalent to a parallel switching
Q.7 A positive logic OR gate is the same as a
circuit.
negative logic
Q.14 Consider the following logic operators:
(A) NOR gate. (B) OR gate.
1. AND. 2. OR. 3. NOT.
(C) EX-OR gate. (D) AND gate.
Their correct hierarchy is
Q.8 Three Boolean operators are:
(A) 1, 2, 3. (B) 3, 1, 2.
(A) NOT, OR, AND
(C) 1, 3, 2. (D) 2, 3, 1. 82.
(B) NOT, NAND, OR Q.15 The complete set of only those Logic Gates
(C) NOR, OR, NOT designated as Universal Gates is
(D) NOR, NAND, NOT (A) NOT, OR and AND Gates.
Q.9 The only function of a NOT gate is to (B) XNOR, NOR and NAND Gates.
(A) Invert an input signal. (C) NOR and NAND Gates.
(B) Act as a universal gate, (D) XOR, NOR and NAND Gates.
(C) Stop a signal. Q.16 NAND and NOR gates are called
(D) None of the above. 'Universal' gates primary because
Q.10 When an input electrical signal A = 101010 (A) They are available everywhere.
is applied to a NOT gate, the output signal (B) They are widely used in I.C. packages.
will be (C) They can be combined to produce
(A) 111010 (B) 101010 AND, OR and NOR gate.
(D)They can be manufactured easily,
(C) 010101 (D) 101011
Q.17 The output of a NOR gate is
Q.11 A three-input OR gate has output equal to 0
when (A) High if all of its inputs are high.
(B) Low if all of its inputs are low.
(A) All its inputs are high.
(C) High if all of its inputs are low.
(B) Two of its inputs are high.
(D) High if only one of its input is low.
(C) All are low.
Q.18 Consider the following statements:
(D) One is high and the other two are low.
1. A NAND gate is equivalent to an OR
Q.12 If negative logic is used, the diode gate gate with its inputs inverted.
shown in the given figure will represent
2. A NOR gate is equivalent to an AND
gate with its inputs inverted.

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GATE ACADEMY® 13 Logic Gates & Switching Circuits
3. A NAND gate is equivalent to an OR (A) x1 + x2 (B) x1 x2
gate with its output inverted.
4. A NOR gate is equivalent to an AND (C) x1 x2 + x1 + x2 (D) x1 x2 + x1 x2
gate with its output inverted. Q.26 An XOR gate produces output only when
Which of these statements are correct? two inputs are
(A) l and 2. (B) 2 and 3. (A) High. (B) Low.
(C) 3 and 4. (D) l and 4. (C) Different, (D) Equal.
Q.19 The output Y of the circuit shown in figure Q.27 An X-OR gate can be converted into an
is inverter by
(A) Permanently connecting one input to 1.
A Y (B) Permanently connecting both inputs to
1.
(A) AA (B) A (C) Permanently connecting one input to 0.
(C) 1 (D) A (D) Permanently connecting both inputs to
Q.20 NAND operation with x and y inputs is 0.
Q.28 For even number of ones at the inputs, the
(A) x + y (B) x + y
output of EX-NOR gate is
(C) x × y ( )
(D) x + y ( x + y ) (A) Low
Q.21 The output Y of a NOR gate for inputs A (B) High
and B is (C) Oscillating
(A) A + B (B) A + B (D) None of the above
Q.29 The output of a logic gate is ' 1' when all its
(C) A + B (D) AB
inputs are at logic '0'. Then the gate is either
Q.22 A three-input NAND gate is to be used as
(A) A NAND or an EX-OR gate
an inverter. Which one of the following
measures will achieve better results? (B) A NOR or an EX-NOR gate
(A) The two inputs not used are kept open. (C) An OR or an EX-NOR gate
(B) The two inputs not used are connected (D) An AND or an EX-OR gate
to ground (0 level). Q.30 AND operation of (79) 10 and (—56)10
(C) The two inputs not used are connected results in:
to logic (1 level). (A) 50 H (B) 48 H
(D) None of the above. (C) 42 H (D) 08 H
Q.23 The output of an EX–OR gate with A and Q.31 The switching circuit given in A the figure
B as inputs will be can be expressed in binary logic notation
(A) AB + AB (B) ( A + B )( A + B ) as
A C E
(C) (A + B)(AB) (D) A + B + AB
Q.24 In exclusive OR gate, when output is zero B D
the inputs are
(A) 0, 1 (B) 1, 0
(C) 1, 1 (D) 1, x
(A) L = (A + B) (C+ D) E
Q.25 The switching function of an exclusive –
OR gate is given by f ( x1 , x2 ) = x1 + x2 (B) L = AB + CD + E
(C) L = E + (A + B) (C + D)
where f ( x1 , x2 ) is equal to
(D) L = (AB + CD) E
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Digital Electronics [SSC-JE & All State AE/JE] 14 GATE ACADEMY®
Q.32 The Boolean expression for the output Y in Q.36 The circuit shown below generates the
the logic circuit is function of
A x

y
A
A
B Y
C
f
(A) ABC (B) ABC
(C) ABC (D) ABC
Q.33 For a 3-input logic circuit shown below, the
(A) x ⊕ y (B) 0
output Z can be expressed as
P (C) x y + yx + yx (D) x y
Q.37 For the circuit shown in the figure the
Boolean expression for the output Y in
Q Z
terms of inputs P, Q, R and S is

R P

(A) Q + R (B) PQ + R
(C) Q + R (D) P + Q + R Q
Y

Q.34 In the logic circuit shown in the A figure,

R
Y is given by
A

S
B

Y (A) P + Q + R + S (B) P + Q + R + S
C (C) ( P + Q)( R + S ) (D) ( P + Q )( R + S )
Q.38 A, B, C, and D are input, and Y is the output
D
bit in the XOR gate circuit of the figure.
(A) Y = ABCD Which of the following statements about
(B) Y = (A + B) (C + D) the sum S of A, B, C, D and Y is correct?
(C) Y = A + B + C + D A
(D) Y = AB + CD XOR
B
Q.35 Which one of the following is the correct
output (f) of the circuit?
XOR Y
a

b C
f XOR

c
D
(A) S is always with zero or odd.
d (B) S is always either zero or even.
( )
(A) ( a + b ) c + d ( )( )
(B) a + b c + d (C) S = 1 only if the sum of A, B, C and D
is even
(C) ( a + b )( c + d ) (D) ( a + b ) ( a + d ) (D) S = 1 only if the sum of A, B, C and D
is odd.
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GATE ACADEMY® 15 Logic Gates & Switching Circuits
Q.39 The given circuit, the output Y equals
which one of the following?
A

(A) A + B (B) A B + A B
(C) AB (D) A + B

Answer Keys

Classroom Practice Questions

1. D 2. C 3. D 4. A 5. C
6. A 7. C 8. B 9. C 10. B
11. D 12. A 13. B 14. B 15. C
16. B 17. B 18. B 19. C 20. B
21. C 22. B 23. A 24. D 25. A
26. A 27. A 28. C 29. B 30. D
31. D 32. D 33. D 34. A 35. A
36. D 37. D 38. C 39. A
Self Practice Questions
1. B 2. D 3. B 4. B 5. A
6. D 7. D 8. A 9. A 10. C
11. C 12. B 13. C 14. B 15. C
16. C 17. C 18. A 19. D 20. B
21. B 22. C 23. C 24. C 25. D
26. C 27. A 28. B 29. B 30. B
31. A 32. B 33. C 34. D 35. A
36. A 37. B 38. B 39. D

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 3 Boolean Algebra

Classroom Practice Questions (CPQs) Select the correct answer from the codes
given below.
Q.1 The Boolean function A + BC is a reduced
(A) 1 only (B) 2 and 3
form of which one of the following ?
(C) 3 only (D) 3 and 4
(A) AB + BC (B) AB + ABC
[UPSC ESE 2009]
(C) (A+B).(A+ C) (D) None of these Q.5 The Boolean expression
[UPSC ESE 2008] A+B+C + A+B+C + A+B+C + ABC reduces to :
Q.2 Which one of the following statements is (A) A (B) B
not correct ? (C) C (D) A + B + C
(A) X + XY = X [UPSC ESE 2010]
(B) X (X + Y) = XY Q.6 The standard SOP expression for Boolean
expression AB + AC+ BC is :
(C) XY + XY=X
(A) ABC + ABC+ ABC + ABC
(D) ZX + ZXY=ZX + ZY
(B) ABC + ABC+ ABC
[UPSC ESE 2008] (C) ABC + ABC+ ABC
Q.3 Which of the following Boolean algebra (D) ABC + ABC+ ABC
rules is correct?
[UPSC ESE 2010]
(A) A ⋅ A = 1 Q.7 The complement of the expression
(B) A + AB = A + B Y = ABC + ABC+ ABC + ABC is :
(C) A + AB = A + B (A) ( A+B )( A+C ) (B) ( A+B ) ( A+C )
(D) A( A + B ) = B
(C) (A + B) (A + C) (D) ( A+B )( A+C )
[UPSC ESE 2009]
[UPSC ESE 2010]
Q.4 What are the ultimate purposes of minizing
logic expressions ? Q.8 The logic function f = x . y + x . y is the
1. To get a small size expression. same as :
2. To reduce the number of variables n (A) f = (x + y) (x + y)
the given expression.
(B) f = (x + y) (x + y)
3. To implement the function of the logic
expression with least hardware. (C) f = (x . y) (x . y)
4. To reduce the expression for making it (D) None of the above
feasible for hardware implementation. [UPSC ESE 2011]
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GATE ACADEMY® 17 Boolean Algebra

Q.9 If the Boolean expression PQ + QR + PR Q.15 Logic function ( A + B)( A + B) can be

is minimized, the expression becomes :
reduced to :
(A) PQ + QR (B) PQ + PR (A) B (B) B
(C) QR + PR (D) PQ + QR + PR (C) A (D) A
[UPSC ESE 2011] [UPSC ESE 2013]
Q.10 The correct expression is Q.16 Logic function A B D + A B D can be
(A) AB + AB = AB ( A + B) reduced to :
(B) AB + AB = AB ( A + B) (A) A B (B) AB

(C) AB + AB = AB ( A + B) (C) B D (D) A D

(D) AB + AB = AB ( A + B) [UPSC ESE 2013]

Q.17 The minterms for AB + ACD are :
[UPSC ESE 2012]
Q.11 Simplified form of the logic expression (A) ABCD + ABCD + ABC D + ABC D + ABCD
( A + B + C )( A + B + C ) ( A + B + C ) is (B) ABC D + ABCD + ABC D + ABCD + ABCD

(A) AB + C (B) A + BC (C) ABCD + ABCD + ABC D + ABCD + ABC D

(C) A (D) AB + C (D) ABCD + ABCD + ABCD + ABC D + ABCD

[UPSC ESE 2012] [UPSC ESE 2013]
Q.12 The Boolean equation Q.18 On simplification of expression

X = {( A + B ) ( B + C )} B can be simplified Y = ( A • B + C )( A + B + C ) , using Boolean

to algebra, the solution is
(A) ( A • B + C )( A + B • C )
(A) X = AB (B) X = AB
(C) X = AB (D) X = A B (B) ( A + B + C )( A + B + C )

[UPSC ESE 2012] (C) ( A • B + C )( A • C + B )

Q.13 The logic function (D) ( B • C + A)( A • B + C )
(
f ( A, B, C , D ) = A + BC ) ( B + CD ) [UPSC ESE 2015]
can be expressed to : Q.19 K-map method of simplification can be
applied when the given function is in
(A) A B + BC + AC D + BCD
(A) Product of sum form
(B) AB + AB + ACD + B C D (B) Sum of product form
(C) AB + AB + ACD + BCD (C) Canonical form
(D) AB + AB + ACD + BCD (D)Any form
[UPSC ESE 2013] [UPSC ESE 2015]
Q.14 A 3 variable truth table has a high output for Q.20 The function Y = A + B • C in canonical
the input : 010, 011 and 110. The Boolean sum of product form is
expression for sum of product (SOP) can be (A) Y = Σ 1, 3, 5, 6, 7
written as : (B) Y = Σ 1, 4, 5, 6, 7
(A) AB + BC (B) AB + BC (C) Y = Σ 2, 3, 5, 6
(C) AB + BC (D) AB + BC (D) Y = Σ 2, 3, 5, 7
[UPSC ESE 2013] [UPSC ESE 2015]
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Digital Electronics [SSC-JE & All State AE/JE] 18 GATE ACADEMY®
Q.21 The simplified form of the Boolean Q.27 Consider the following expression:
expression AB + A(B + C) + B(B + C) is A⋅ B ⋅C ⋅ D + A⋅ B ⋅C ⋅ D + A⋅ B ⋅C ⋅ D
given by
+ A⋅ B ⋅C ⋅ D + A⋅ B ⋅C ⋅ D ⋅ E
(A) AB + AC (B) B + AC
+ A⋅ B ⋅C ⋅ D ⋅ E + A⋅ B ⋅C ⋅ D ⋅ E
(C) BC + AC (D) AB + C
[UPSC ESE 2016] The simplification of this by using
theorems of Boolean algebra will be
Q.22 Product a Max terms representation for the
Boolean function F = BD + AD + BD is (A) A + B (B) A ⊕ B
(A) π M (1, 3, 5, 7) (C) ( A + B )( A ⋅ B ) (D) A ⋅ B
(B) π M (0, 2, 4, 6) [UPSC ESE 2019]
(C) π M (0, 1, 2, 3) Q.28 An electric power generating station
(D) π M (4, 5, 6, 7) supplies power to three loads A, B and C.
Only a single generator is required when
[UPSC ESE 2016]
any one load is switched on. When more
Q.23 Simplified form of the Boolean expression
than one load is on, an auxiliary generator
Y = (A.B+ C)(A + B + C) is must be started. The Boolean equation for
(A) AC + AC + BC + BC the control of switching of the auxiliary
generator will be
(B) (A + B + C)(A + B + C)
(A) AA + BB + CC
(C) (A + B)(A + C)
(B) ABC + BCA + CAB
(D) A (B + C) (C) AB + AC
[UPSC ESE 2016] (D) AB + AC + BC
Q.24 What is the function Y = A + BC in [UPSC ESE 2019]
Product-of Sums (POS) form? Q.29 An expression f = AB + A + AB can be
(A) M 6 M 5 M 4 M 3 (B) M 3 M 2 M 1M 0 reduced to
(C) M 0 M 2 M 3 (D) M 4 M 3 M 2 M 1 (A) A (B) B
[UPSC ESE 2016] (C) 0 (D) 1
Q.25 The minterm expansion of [UPSC ESE 2020]
F ( A, B, C ) = AB + BC + AC is Q.30 K-map is used to minimize the number of
(A) Flip-flops in digital circuits
(A) m2 + m4 + m6 + m1
(B) Layout spaces in digital circuits for
(B) m0 + m1 + m3 + m5 fabrication
(C) m7 + m6 + m2 + m4 (C) Functions of 3, 4, 5 and 6 variables
(D) m2 + m3 + m4 + m5 (D) Registers in CPU
[UPSC ESE 2020]
[UPSC ESE 2017]
Q.26 The simplification in minimal sum of Q.31 If A and B are boolean variables, then
product (SOP) of (A+B).( A + B ) = ?
Y = F ( A, B, C , D) = Σm (0, 2,3,6,7) (A) A (B) A+B
(C) AB (D) B
+Σ(8,10,11,15)
[CSEB JE Electrical]
Using K-maps is :
Q.32 The complement of [(A.B + C).D + E] F is
(A) Y = AC + BD (B) Y = AC + BD
(A) [( A + B).C + D.E ] + F
(C) Y = AC + BD (D) Y = AC + BD
[UPSC ESE 2017] (B) [( A + B).C + D.E ].F

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GATE ACADEMY® 19 Boolean Algebra

(C) [( A + B).C + D].E + F Q.39 The output expression for the Karnaugh
map shown below is
(D) [( A + B).C + D]E + F BC
A 00 01 11 10
[UPPSC AE 2019]
0 1 0 0 1
Q.33 A combination circuit has inputs A, B and
C. its z K-map is given below. The output 1 1 1 1 1
of circuit is given by (A) A + B (B) A + C
AB (C) A + C (D) A + C
C 00 01 11 10 Q.40 The output expression for the Karnaugh
0 1 1 map shown below is
CD
AB 00 01 11 10
1 1 1 00 0 0 0 0
01 1 0 0 1
(
(A) AB + AB C ) (
(B) AB + AB C ) 11 1 0 1 1
(C) ABC (D) A ⊕ B ⊕ C 10 0 0 0 0
[UPPSC AE 2019] (A) BD + BCD (B) BD + AB
Q.34 POS form of Boolean expression is suitable (C) BD + ABC (D) BD + ABC
for circuit implementation, using Q.41 Consider the following Boolean function
(A) XOR (B) NAND with four variables
(C) AND (D) NOR F(w, x, y, z) = Σ (1, 3, 4, 6, 9, 11, 12, 14).
The function is
[UPPSC AE 2019]
(A) Independent of one variables
Q.35 The Boolean function A + BC is a reduced
(B) Independent of two variables
form of
(C) Independent of three variables
(A) AB + BC (B) (A + B)(A + C) (D) Dependent on all variables
(C) A'B + ABV (D) (A + C)B Q.42 The SOP (sum of products) form of a
[UPPSC AE 2019] Boolean functions is  (0,1, 3, 7,11) , where
Q.36 The boolean expression A(A+B) is equal to inputs are A, B, C, D, (A is MSB, and D is
(A) 1 (B) B LSB). The equivalent minimized
(C) A (D) A+B expression of the function is
[STATE ESE EE] (A) ( B + C ) ( A + C ) ( A + B ) (C + D)
Q.37 The Boolean expression (A + C + D) (B + (B) ( B + C ) ( A + C ) ( A + C ) (C + D)
D + C) may be simplified as (C) ( B + C ) ( A + C ) ( A + C ) (C + D)
(A) AB + CB (B) AB + C + D
(D) ( B + C ) ( A + B ) ( A + B ) (C + D)
(C) A + BC + D (D) A + B + CD
Q.43 In the Karnaugh map shown below, X
[STATE ESE EE] denotes a don’t care term. What is the
Q.38 In Boolean Algebra, if F = (A + B) ( A + C) minimal form of the function represented
then by the Karnaugh map?
ab
(A) F = AB + A C
cd
(B) F = AC + A B
(C) F = AB + AB X

(D) F = A C + A B X
[STATE ESE EE] X

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Digital Electronics [SSC-JE & All State AE/JE] 20 GATE ACADEMY®

(A) b . d + a . d The minimized expression for the given K

map (x don't care) is :
(B) a . b + b . d + a . b . d
(A) A + BC (B) B +AC
(C) b . d + a . b . d
(C) C + AB (D) A B C
(D) a . b + b . d + a . d
Q.5 Consider the Boolean expression
Self-Practice Questions (SPQs) X = ABCD + ABCD + ABCD + ACBD
Q.1 Karnaugh map is used to The simplified form of X is :
[UPSC ESE 2000]
[UPSC ESE 2002]
(A) minimise the number of flip-flops in a
(A) C + D (B) B C
digital circuit
(B) minimise the number of gates only in a (C) C D (D) B C
digital circuit Q.6 The Boolean Expression
(C) Minimise the number of gates and fan- (A + B) (A + C) (B + C)
in of a digital circuit
Simplifies to [UPSC ESE 2003]
(D) design gates
(A) (A + B)C (B) (A + B)C
Q.2 For the Karnaugh map shown in the given
figure, the minimum Boolean function is : (C) (A + B)C (D) (A + B) C
[UPSC ESE 2001] Q.7 A, B and C are three Boolean variables,
Which one of the following Boolean
expressions cannot be minimized any
further ? [UPSC ESE 2004]
(A) Z =A.B.C + A.B.C + A.B.C + A.B.C
(B) Z = A.B.C + A.B.C + A.B.C + A.B.C
(C) Z = A.B.C + A.B.C + A.B.C + A.B.C

(A) x'y' + z' + yz (B) xz' + z + zy' (D) Z = A.B.C + A.B.C + A.B.C + A.B.C
(C) xy + z + y'z (D) x'z + z' + yz Q.8 [UPSC ESE 2005]
Q.3 Which one of the following is equivalent to
the Boolean expression
Y = A B+ B C + C A
(A) AB + BC + CA [UPSC ESE 2001]
(B) (A + B) (B + C) (A + C)
(C) (A + B) (B + C) (C + A) What is the minimized logic expression
(D) (A + B) (B + C) (C + A) corresponding to the given Karnaugh Map?
Q.4 [UPSC ESE 2002] (A) xz
(B) w x y + w y z + w y z + w x y
(C) w x y + w y z + w y z + w x y
(D) x z + w y z + w x y + w x y + w y z
Q.9 The Boolean function
( x + y ) ( x + z )( y + z ) is equal to which one
of the following expressions?
[UPSC ESE 2005]
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 GATE ACADEMY® 21 Boolean Algebra
(A) ( x + y) ( y + z ) (B) ( x + z ) ( y + z ) Q.16 Match List I (Boolean Logic Function) with
(C) ( x + y) ( x + z ) (D) ( x + y) ( x + z ) List II (Inverse of Function) and select the
correct answer using the code given below
Q.10 What is the Boolean expression for the truth the lists : [UPSC ESE 2007]
table shown below? [UPSC ESE 2006]
List I
A 0 0 0 0 1 1 1 1
A. ab + bc + ca + abc
B 0 0 1 1 0 0 1 1
B. ab + ab + c
C 0 1 0 1 0 1 0 1
C. a + bc
f 0 0 0 1 0 0 1 0
D. (a + b + c )a + b + c )(a + b + c)
(A) B( A + C )( A + C )
List II
(B) B( A + C )( A + C )
1. a(b + c)
(C) B ( A + C )( A + C )
2. ab + bc + ca
(D) B ( A + C )( A + C ) 3. (a ⊕ b)c
Q.11 What does the Boolean expression 4. abc + abc + abc
AD + ABCD + ACD + AB + ACD + AB .
Codes : A B C D
on minimization result into? (A) 3 2 1 4
[UPSC ESE 2006] (B) 2 3 1 4
(A) A + D (B) AD + A
(C) 3 2 4 1
(C) AD (D) A +D (D) 2 3 4 1
Q.12 If A and B are Boolean variables. then what Q.17 Consider the following statements :
is (A + B) ⋅ (A + B) equal to ?
1. Minimization using Karnaugh map may
[UPSC ESE 2006] not provide unique solution.
(A) B (B) A 2. Redundant grouping in Karnaugh map
(C) A + B (D) AB may result in non-minimized solution.
Q.13 What is the Boolean expression A ⊕ B
equivalent to ? [UPSC ESE 2006] 3. Don’t care states if used in karnaugh
(A) AB + AB (B) AB + AB map for minimization, the minimal
(C) B (D) A solution is not obtained.
Q.14 When the Boolean function Which of the statements given above are
correct? [UPSC ESE 2007]
[UPSC ESE 2007]
F (x1 x 2 x 3 )=Σ (0,1, 2,3)+Σ Φ (4,5, 6, 7)
(A) 1, 2 and 3 (B) 2 and 3 only
(C) 1 and 3 only (D) 1 and 2 only
is minimized, what does one get?
Q.18 The Boolean functions can be expressed in
(A) 1 (B) 0
canonical SOP (Sum of products) and POS
(C) x1 (D) x3 (Product of sums) form. For the function,
Q.15 By inspecting the Karnaugh map plot of the Y = A + B.C, which are such two forms ?
switching function F ( x1 x2 x3 ) = Σ(1,3, 6, 7) one [UPSC ESE 2008]
can say that the redundant prime implicant (A) Y = (1, 2, 6, 7) and Y = ∏(0, 2, 4)
is [UPSC ESE 2007]
(B) Y = (1, 4, 5, 6, 7) and Y = ∏(0, 2, 3)
(A) x1 x3 (B) x2 x3
(C) Y = (1, 2, 5, 6, 7) and Y = ∏(0, 1, 3)
(C) x1 x2 (D) x3
(D) Y = (1, 2, 4, 5, 6, 7) and Y = ∏(0, 2, 3, 4)
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Digital Electronics [SSC-JE & All State AE/JE] 22 GATE ACADEMY®
Q.19 Given the following Karnaugh map, which (A) QS + PRS + PQR + PRS + PQR
one of the following represents the minimal
Sum - Of - Products of the map? (B) QS + PRS + PQR + PRS + PQR

yz
wx
00 01 11 10 (C) PRS + PQR + PRS + PQR
00 0 x 0 x (D) PRS + PQR + PRS + PQR
01 x 1 x 1 Q.23 Minimum SOP for f(w, x, y, z) shown in
11 0 x 1 0 Karnaugh – map below is
10 0 1 x 0

(A) xy + y’z
(B) wx’y’ + xy + xz
(C) w’x + y’z + xy
(D) xz + y
Q.20 The number of product terms in the
minimized sum-of-product expression
(A) x z + y’ z (B) x z’ + z x’
obtained through the following K-map
(where, ‘d’ denotes don’t care states) (C) x’ y + z x’ (D) None

1 0 0 1
0 d 0 0
0 0 d 1
1 0 0 1

(A) 2 (B) 3
(C) 4 (D) 5
Q.21 The function represented by the Karnaugh
map given below is
BC
A 00 01 10 11
0 1 0 0 1
1 1 0 0 1

(A) A.B (B) AB + BC + CA

(C) B ⊕ C (D) [Link]
Q.22 The minimal sum-of-products expression
for the logic function f represented by the
given Karnaugh map is
PQ
RS 00 01 11 10
00 0 1 0 0

01 0 1 1 1

11 1 1 1 0

10 0 0 1 0

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GATE ACADEMY® 23 Boolean Algebra

Answer Keys

Classroom Practice Questions

1. C 2. A 3. C 4. D 5. B
6. A 7. D 8. B 9. B 10. A
11. B 12. C 13. A 14. A 15. A
16. B 17. B 18. B 19. D 20. B
21. B 22. B 23. B 24. C 25. D
26. D 27. D 28. D 29. C 30. C
31. A 32. C 33. D 34. D 35. B
36. C 37. B 38. B 39. B 40. D
41. B 42. A 43. A
Self Practice Questions
1. B 2. D 3. C 4. A 5. C
6. C 7. C 8. B 9. C 10. A
11. D 12. B 13. B 14. A 15. B
16. B 17. D 18. B 19. A 20. A
21. C 22. D 23. B

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 4 Combinational Circuits

Classroom Practice Questions (CPQs) Q.3

Q.1 Consider the following circuit

What is the output f ( x, y) of the multiplexer

resulting from the input logical values
In the above TTL circuit, S 2 to S 0 are (A) An EXOR gate (B) A NOR gate
select lines and X 7 to X 0 are input lines. (C) An AND gate (D) A NAND gate
S 0 and X 0 are LSBs. What is the output Y? [UPSC ESE 2005]
(A) Indeterminate (B) A ⊕ B Q.4 Consider the following statements:
(C) A ⊕ B (D) C ⊕ B ⊕ A A half-adder
[UPSC ESE 2004] 1. is a half-subtractor also.
Q.2 Consider the following statements : 2. has two outputs CH = x. y and
A 4 : 16 decoder can be constructed (with SH = x ⊕ y for two inputs x and y
enable input) by 3. has two outputs and SH = x ⊕ y for two
1. using four 2 : 4 decoders (each with an inputs x and y
enable input) only. 4. is a combinational circuit.
2. using five 2 : 4 decoders (each with an
Which of the statements given above is/are
enable input) only.
correct?
3. using two 3 : 8 decoders (each with an
(A) 1, 3 and 4 (B) 1, 2 and 4
enable input) only.
(C) 4 only (D) 2 and 3
4. using two 3 : 8 decoders (each with an
enable input) and an inverter. [UPSC ESE 2005]
Which of the statements given above is/are Q.5 When two 16-input multiplexers drive a 2-
correct? input MUX, what is the result?
(A) 2 and 3 (B) 1 only (A) 2-input MUX (B) 4-input MUX
(C) 2 and 4 (D) None of the above (C) 16-input MUX (D) 32-input MUX
[UPSC ESE 2005] [UPSC ESE 2007]

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GATE ACADEMY® 25 Combinational Circuits
Q.6 A digital multiplexer can be used for which Q.10
of the following ?
1. Parallel to serial conversion
2. Many-to-one switch
3. To generate memory chip select
4. For code conversion
Select the correct answer using the code
given below :
(A) 1, 3 and 4 (B) 2, 3 and 4
(C) 1 and 2 only (D) 2 and 3 only
[UPSC ESE 2008] A 4 x 1 MUX is used to implement a 3-input
Q.7 Which of the following circuit come under Boolean function is as shown above. The
the class of combinational logic circuits? Boolean function F(A, B,C) implemented is:
1. Full adder (A) F(A, B,C) =  (1, 2, 4, 6)
2. Full subtractor (B) F(A, B,C) =  (1, 2, 6)
3. Half adder
(C) F(A, B,C) =  (2, 4, 5, 6)
4. J-K flip-flop
5. Counter (D) F(A, B,C) =  (1, 5, 6)
Select the correct answer from the codes [UPSC ESE 2010]
given below: Q.11 Consider the following statements:
(A) 1 only (B) 3 and 4 1. A multiplexer is analogous to a rotary
(C) 4 and 5 (D) 1, 2 and 3 switch.
[UPSC ESE 2009] 2. A decoder is a combinational logic circuit
Q.8 With which decoder it is possible to obtain that converts binary information from ‘n’
many code conversions? input lines to a maximum of 2n distance
(A) 2 line to 4 line elements at the output.
(B) 3 line to 8 line 3. The Boolean expression for the output
(C) not possible with any decoder difference ‘D’ form a full subs tractor is
(D) 4 line to 16 line decoder exactly the same as the output sum ‘S’
[UPSC ESE 2009] form a full adder.
Q.9 Which of the above statements is/are correct?
(A) 2 and 4 only (B) 4 only
(C) 1 and 3 only (D) 1, 2 and 3
[UPSC ESE 2010]
Q.12 A binary full–subtractor :
(A) Consist of two cascaded half-
subtractors
(B) Contains two half–subtractors and one
OR gate
In the above circuit X is given by: (C) Can subtract any binary number
(A) X = ABC + ABC + ABC + ABC (D) Can be made out of a full–adder
(B) X = ABC + ABC + ABC + ABC [UPSC ESE 2013]
(C) X = AB + BC + AC Q.13 A digital multiplexer can be used for :
(D) X = AB + BC + AC 1. Parallel to serial conversion
[UPSC ESE 2010] 2. Many–to-one switch
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Digital Electronics [SSC-JE & All State AE/JE] 26 GATE ACADEMY®
3. Generating memory chip select (A) 1 only (B) 2 only
4. Code conversion (C) Both 1 and 2 (D) Neither 1 nor 2
(A) 1, 2 and 3 (B) 2 and 3 only [UPSC ESE 2016]
(C) 1 and 2 only (D) 1 and 3 only Q.18 Consider the following statements with
[UPSC ESE 2013] respect to combinational circuit :
Q.14 The Boolean function ‘f ‘ implemented as 1. The output at any time depends only on
shown in the figure using two input the present combination of inputs.
multiplexers is 2. It does not employ storage elements
C O 3. It performs an operation that can be
0 0
specified logically by a set of Boolean
f
C A functions.
1 1
Which of the above statements are correct?
B E
(A) 1 and 2 only (B) 1 and 3 only
(A) ABC + ABC (B) ABC + ABC (C) 2 and 3 only (D) 1, 2 and 3
(C) ABC + ABC (D) ABC + ABC [UPSC ESE 2016]
[UPSC ESE 2014] Q.19 Consider the following statements :
Q.15 A half adder can be constructed using A multiplexer
(A) One XOR and one OR gate with their 1. selects one of the several inputs and
outputs connected in parallel. transmit it to a single output.
(B) One XOR and one OR gate with their 2. route the data from a single input to
outputs connected in series. one of many outputs.
(C) One XOR gate and one AND gate. 3. converts parallel data into serial data
(D) Two XNOR gates only. 4. is a combinational circuit
[UPSC ESE 2015] Which of the above statements are correct ?
Q.16 The following switching functions are to be (A) 1 and 3 only (B) 2 and 4 only
implemented using a Decoder : (C) 1, 3 and 4 only (D) 2, 3 and 4 only
f1 = Σm (1, 2, 4, 8, 10, 14) [UPSC ESE 2016]
f 2 = Σm(2, 5, 9, 11) Q.20 How many 3 to 8 line decoders with an
f 3 = Σm (2, 4, 5, 6, 7) enabler input are needed to construct a 6 to
64 line decoder without using any other
The minimum configuration of the decoder logic gates?
should be
(A) 11 (B) 10
(A) 2 to 4 lines (B) 3 to 8 lines
(C) 9 (D) 8
(C) 4 to 16 lines (D) 5 to 32 lines
[UPSC ESE 2017]
[UPSC ESE 2015]
Q.21 A logic circuit that accepts several data
Q.17 For realizing a binary half-subtractor inputs and allows only one of them at a time
having two inputs A and B, the correct set to get through to the output is called
of logical expressions for the outputs D (A
(A) Multiplexer (B) De-multiplexer
minus B) and X (borrow) are
(C) Transmitter (D) Receiver
1. The difference output D = AB + AB
[UPSC ESE 2020]
2. The borrow output B = AB Q.22 Consider the following :
Which of the above statements is/are Any combinational circuit can be built
correct? using
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GATE ACADEMY® 27 Combinational Circuits
1. NAND gates 2. NOR gates Q.25 For a four variable K-Map, if each cell is
3. EX-OR gates 4. Multiplexers assigned one integer value in range 0-15
then which is the cells adjacent to the cell
Which of these are correct ?
corresponding to decimal value 7 ?
(A) 1, 2 and 3 (B) 1, 3 and 4
(A) 3, 5, 6 and 8
(C) 2, 3 and 4 (D) 1, 2 and 4
(B) 3, 5, 10 and 11
[UPSC ESE 2002]
(C) 3, 5, 6 and 15
Q.23 Match List-I (Operation) with List-II
(Associated Devices) and select the correct (D) 4, 6, 8 and 15
answer using the codes given below the [UPSC ESE 2015]
lists : Q.26 If a, b, c are 3-input variables, then Boolean
List-I List-II function y = ab + bc + ca represents
(Operation) (Associated Devices) 1. A 3-input majority gate
A. Counting 1. ROM 2. A 3-input minority gate
B. Decoding 2. Multiplexer 3. Carry output of a full adder
C. Data selection 3. Demultiplexer 4. Product circuit for a, b and c
D. Code convertion 4. Register Which of the above statements are correct?
Codes: A B C D (A) 2 and 3 (B) 2 and 4
(A) 3 4 2 1 (C) 1 and 3 (D) 1 and 4
(B) 3 4 1 2 [UPSC ESE 2016]
(C) 4 3 1 2 Q.27 Full subtractor can be realized by using
(D) 4 3 2 1 ______
[UPSC ESE 2004] (A) two half subtractors
Q.24 Consider the following circuit : (B) two half subractors and a NOT gate
(C) two half subtractors and AND gate
1 (D) two half subtractors and a QR gate
0 [GSECL VS JE EE]
A
1
Q.28 A full adder can be made out of____.
B 4x1 f (A) two half adders
S 2 MUX
(B) two half adders and a NOT gate
3
(C) two half adders and an AND gate
(D) two half adders and an OR gate
C2 C1
[GSECL VS JE EE]
Which one of the following gives the Q.29 Which of the following can be used as a
function implemented by the MUX-based Parallel-to-Series conveter ?
digital circuit ?
(A) Multiplexer
(A) f = C2 .C1.S + C2 .C1.( A + B)
(B) Decoder
(B) f = C2 .C1 + C2 .C1 + C2 .C1 .S + C2 .C1 .AB (C) Demultiplexter
(C) f = AB + S (D) Digital Counters
[CSEB JE]
(D) f = C2 .C1 + C2 .C1 .S + C2 .C1 .AB
Q.30 The output fof the 4 : 1 MUX shown in
[UPSC ESE 2004]
figure is

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Digital Electronics [SSC-JE & All State AE/JE] 28 GATE ACADEMY®

0
(A) 2m = n (B) 2n = m
f (C) mn = 2 (D) n2 = m
1 4 :1 MUX
[STATE ESE EE]
Vcc 2
3 S1 S0 Q.37 A full adder can be implemented with half
adders and OR gates. A 4-bit parallel full
x y adder without any initial carry requires
(A) 8 half adders, 4 OR gates
(A) xy + x (B) x + y
(B) 8 half adders, 3 OR gates
(C) x + y (D) xy + x (C) 7 half adders, 4 OR gates
[UPPSC AE 2019] (D) 7 half adders, 3 OR gates
Q.31 Which of the following circuits come under [STATE ESE EE]
the class of sequentual logic circuits-
Self-Practice Questions (SPQs)
(A) Full adder
(B) Full subtractor Q.1 The logic circuit realized by the circuit
shown in the given figure will be
(C) Half adder
(D) J-K flip counter
[STATE ESE EE]
Q.32 What are the output bit s (sum) and c (carry)
of a Half odder having input A = 1 and B =
1?
(A) 1,1 (B) 1,0
(C) 0,1 (D) 0,0 (A) F = B O C (B) F = B ⊕ C
[STATE ESE EE] (C) F = AO C (D) F = A⊕C
Q.33 How many 3-line to 8-line decoders are
Q.2 Which one of the following statements
required for a 1 of 32 decoder ?
correctly defines the full adder ?
(A) 1 (B) 2
An adder circuit
(C) 4 (D) 8
(A) Having two inputs used to add two
[STATE ESE EE] binary digits. It produces their sum and
Q.34 A full adder circuit has carry as input
(A) two inputs and one output (B) Having three inputs used to add two
(B) two inputs and two outputs binary digits plus a carry. It produces
(C) three inputs and one output their sum and carry as outputs
(D) three inputs and two outputs (C) Used in the least significant position
[STATE ESE EE] when adding two binary digits with no
Q.35 A full substractor can be constructed from carry-in to consider. It produces their
two half substractors and a sum and carry as outputs
(A) 2-input NAND gate (D) Having two inputs and two outputs
(B) 2-input NOR gate Q.3 The half-adder circuit in the given figure
has inputs AB = 11
(C) 2-input OR gate
(D) 2-input AND gate
[STATE ESE EE]
Q.36 A multiplexure has n data inputs, m control
inputs and one data output, then

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GATE ACADEMY® 29 Combinational Circuits
The logic level of P and Q outputs will be Q.9 For a binary half-subtractor having two
(A) P = 0 and Q = 0 (B) P = 0 and Q = 1 inputs A and B the correct sets of logical
(C) P = 1 and Q = 0 (D) P = 1 and Q = 1 expression for the output D( = A minus B)
Q.4 Which one of the following can be used as and X( = borrow) are
parallel to series converter ? (A) D = AB + AB , X = AB
(A) Decoder (B) Digital counter (B) D = AB + AB , X = AB
(C) Multiplexer (D) demultiplexer (C) D = A B + A B, X = A B
Q.5 Consider the following statements : (D) D = A B + A B, X = A B
A multiplexer
Q.10 Which one of the following statements
1. Selects one of the several inputs and describes the operation of a multiplexer ?
transmits it to a single output
(A) A logic circuit used to generate coded
2. routes the data from a single input to output
one of many outputs (B) A logic circuit used to generate F's
3. Converts parallel data into serial data complement
4. is a combinational circuit (C) A logic circuit that accepts two or more
Which of these statements are correct ? inputs and allows one of them at a time
(A) 1, 2 and 4 (B) 2, 3 and 4 to get through the output
(C) 1, 3 and 4 (D) 1, 2 and 3 (D) A logic circuit that transmits one input
Q.6 The number of 4-line-to-16-line decoder to several output lines
required to make an 8-line-to-256-line Q.11 The output F of the multiplexer circuit
decoder is shown below expressed in terms of the
(A) 16 (B) 17 input P, Q and R is
(C) 32 (D) 64 R I0
Q.7 Consider the following digital circuits : R I1
MUX Y F
R I2
1. Multiplexers
R I3 S S0
2. Real only memories 1

3. D-latch
4. Circuit as shown P Q
(A) F = P ⊕ Q ⊕ R
(B) F = PQ + QR + RP
(C) F = ( P ⊕ Q) R
Which of these come under the class of
combinational circuit? (D) F = ( P ⊕ Q ) R
(A) 1 and 2 (B) 3 and 4 Q.12 The output F of the 4 to 1 MUX shown in
figure is
(C) 1, 2 and 3 (D) 1, 2, 3 and 4
Q.8 The addition of two binary variables A and 3
B results into a sum and a carry output. + 5V 2 4:1
Consider the following expressions for the MUX F
1
SUM and CARRY outputs.
0 S1 S0
1. SUM = A.B+A.B 2. SUM = A.B+A.B
3. CARRY = A.B 4. CARRY = A+B
x y
Which of these expressions are correct ?
(A) 1 and 3 (B) 2 and 3 (A) x y + x (B) x + y
(C) 2 and 4 (D) 1 and 4 (C) x + y (D) x y + x
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Digital Electronics [SSC-JE & All State AE/JE] 30 GATE ACADEMY®
Q.13 An 8 to 1 multiplexer is used to implement a (A) ( X ⊕ Y ) ⊕ Z (B) ( X ⊕ Y ) ⊕ Z
logical function Y as shown in the figure.
The output Y is given by (C) ( X ⊕ Y ) ⊕ Z (D) ( X ⊕ Y ) ⊕ Z
0 I0 Q.16 Consider the circuit shown below. The
D I1 output of a 2: 1 Mux is given by the
0 I2 function (ac’ + bc).
D I3 8:1
I4 Y
0 MUX
1 a a
0 I5 2:1 2:1 f
1 I6 Mux g Mux
b b
0 I7 0
c c
S2 S1 S0
x1 x2
A B C
Which of the following is true?
(A) Y = A B C + AC D
(A) f = x1’ + x2
(B) Y = A B C + A B D
(B) f = x1’ x2 + x1x2’
(C) Y = A B C + AC D (C) f = x1 x2 + x1’x2’
(D) Y = A B C + A B C (D) f = x1 + x2’
Q.14 Consider the 4-to-1 multiplexer with two Q.17 What are the minimum number of 2 to 1
select lines S1 and S0 given below multiplexers required to generate a 2-input
AND gate and a 2-input EX-OR gate?
0 0
(A) 1 and 2 (B) 1 and 3
1 1 4-to1
F (C) 1 and 1 (D) 2 and 2
R 2 Multiplexer
R 3 Q.18 The minimum number of 2 to 1
SS1 S S 0 multiplexers required to realize a 4 to 1
multiplexer is
(A) 1 (B) 2
P
P OQ
(C) 3 (D) 4
The minimal sum-of-products form of the
Boolean expression for the output F of the Q.19 The following circuit implements a two-
multiplexer is input AND gate using two 2 ×1
multiplexers.
(A) PQ + QR + PQR
a 1 1
(B) PQ + PQR + PQR + PQR
2 ´1 2 ´1
a ×b
(C) PQR + PQR + QR + PQR MUX MUX
b 0 0
(D) PQR
Q.15 A MUX circuit shown in the figure below X1 X2 X3
implements a logic function. The correct
What are the values of X 1 , X 2 , X 3 ?
expression for F1 is
(A) X 1 = b, X 2 = 0, X 3 = a
Z 1
MUX F1 (B) X 1 = b, X 2 = 1, X 3 = b
Z 0
S (C) X 1 = a, X 2 = b, X 3 = 1
(D) X 1 = a, X 2 = 0, X 3 = b
X 1

MUX
F0
Q.20 What Boolean function does the circuit
X 0
S below realize?
Y

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 GATE ACADEMY® 31 Combinational Circuits

07 (A) Half Adder (B) Comparator

(C) Half subtractor (D) All of the above
z
y 3:8 f
x decoder

00

(A) xz + xz (B) xz + xz
(C) xy + yz (D) xy + yz
Q.21 In the 4×1 multiplexer, the output F is given
by F = A ⊕ B . Find the required input
I 3 I 2 I1 I 0 .

I0

I1 4 ´1
MUX F
I2

I3
S1 S0

A B

(A) 1010 (B) 0110

(C) 1000 (D) 1110
Q.22 Consider the circuit shown in the figure.

Y 0
MUX 0
0 1 MUX F
1

X
Z
The Boolean expression F implemented by
the circuit is
(A) X Y Z + X Y + Y Z
(B) X Y Z + X Z + Y Z
(C) X Y Z + X Y + Y Z
(D) X Y Z + X Z + Y Z
Q.23 The circuit shown can act as
1:4 DE-MUX
I0
I1
x0
'1' D I2
output
I3
y0

A B
input

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GATE ACADEMY® 32 Boolean Algebra

Answer Keys

Classroom Practice Questions

1. A 2. C 3. A 4. B 5. D
6. C 7. D 8. D 9. A 10. A
11. C 12. B 13. C 14. A 15. C
16. C 17. A 18. D 19. C 20. C
21. A 22. D 23. D 24. D 25. C
26. C 27. D 28. D 29. A 30. B
31. D 32. C 33. C 34. D 35. C
36. A 37. C
Self Practice Questions
1. D 2. B 3. B 4. C 5. C
6. B 7. A 8. B 9. C 10. C
11. A 12. B 13. C 14. A 15. D
16. C 17. A 18. C 19. A 20. B
21. B 22. B 23. A

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 5 Sequential Circuits

Classroom Practice Questions (CPQs) (A) Qn+1 = JQn + KQn

Q.1 A ring counter consisting of five flip-flops (B) Qn+1 = J Qn + K Qn

will have (C) Qn+1 = J Qn + K Qn
(A) 5 states (B) 10 states (D) Qn+1 = JQn + K Qn
(C) 32 states (D) 10 states [UPSC ESE 2003]
[UPSC ESE 2000] Q.6 The number of unused states in a 4-bit
Q.2 The characteristic equation of the T-flip- Johnson counter is
flop is given by (A) 2 (B) 4
(A) Q + = T Q + T Q (B) Q + = T Q + QT (C) 8 (D) 12
[UPSC ESE 2003]
(C) Q + = T Q (D) Q+ = T Q
Q.7 Match List I (Type of flip-flop) with List II
[UPSC ESE 2001] (Symbol) and select the correct answer
Q.3 The initial contents of the 4-bit serial-in- using the code given below the lists:
parallel-out right shift register shown in the List I
give figure is 0110. After three clock pulses (Type of flip-flop)
are applied, the contents of the shift register A. T flip-flop
will be B. Level-triggered JK flip-flop
C. Leading edge-triggered JK flip-flop
D. Trailing edge-triggered JK flip-flop
List II

1.
(A) 0000 (B) 0101
(C) 1010 (D) 1111
[UPSC ESE 2001]
Q.4 Minimum number of J – K flip flops needed
2.
to construct a BCD counter is
(A) 2 (B) 3
(C) 4 (D) 5
[UPSC ESE 2003] 3.
Q.5 The characteristic equation for the next
state (Qn+1 ) of a J – K flip-flop is

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Digital Electronics [SSC-JE & All State AE/JE] 34 GATE ACADEMY®
Q.11
4.

Code : A B C D
(A) 1 2 3 4 In a JK flip-flop we have J = and K = 1.
(B) 2 1 3 4 Assuming the flip-flop was initially cleared
and then clocked for 6 pulses, the sequence
(C) 1 2 4 3
at the Q output will be :
(D) 2 1 4 3
(A) 010000
[UPSC ESE 2005]
(B) 011001
Q.8 Which of the following flip-flop is used as
(C) 010010
a latch?
(D) 010101
(A) J K flip-flop (B) R S flip-flop
[UPSC ESE 2011]
(C) T flip-flop (D) D flip-flop
Q.12 Which one of the following circuits
[UPSC ESE 2009]
converts a JK F/F to a T F/F ?
Q.9 Which of the following circuit come under
the class of sequential logic circuit? (A)

1. Full adder
2. Full substractor
3. Half adder
4. J-K flip-flop (B)
5. Counter
Select the correct answer from the codes
given below:
(A) 1 and 2 (B) 2 and 3 (C)
(C) 3 and 4 (D) 4 and 5
[UPSC ESE 2009]
Q.10

(D)

An X–Y flip flop, whose characteristic table [UPSC ESE 2011]

is given above is to implemented using J-K Q.13 The characteristic equation of the T flip-
flip flop. This can be done by making: flop is given by
(A) J = X, K = Y (a) Qn +1 = TQn (b) Qn +1 = TQn + QnT
(B) J = X, K = Y (c) Qn +1 = TQn (d) Qn +1 = TQn
(C) J = Y, K = X
[UPSC ESE 2012]
(D) J = Y, K = X Q.14 If both inputs of S-R NAND latch are low,
[UPSC ESE 2010] the output will be
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GATE ACADEMY® 35 Sequential Circuits
(a) Unpredictable (b) Toggle Q.19 A cascaded arrangement of flip – flops,
(c) Reset (d) Remain same where the output of one flip – flop drives
[UPSC ESE 2012] the clock input of the following flip- flop, is
Q.15 In the J-K flip-flop we have J = Q and K = known as
1 as shown in the figure. Assuming the flip- (A) Synchronous counter
flop was initially cleared and then clocked (B) Ripple counter
for 6 pulses, the sequence at the Q output (C) Ring counter
will be (D) Up counter
[UPSC ESE 2019]
J Q Q.20 The number of flip –flops required to
construct an 8-bit shift register will be
(A) 32 (B) 16
K Q (C) 8 (D) 4
CLK [UPSC ESE 2019]
(A) 010000 (B) 011001 Q.21 Refer to the NAND and NOR latches
(C) 010010 (D) 010101 shown in the figure. The input ( P1 , P2 ) for
[UPSC ESE 2014] both the latches are first made (0, 1) and
Q.16 Consider the circuit shown in the figure. then, after a few seconds, made (1, 1). The
The expression for the next state Q (t + 1) is corresponding stable output (Q1 , Q2 ) are
P1
Q1
S
Q(t)
x

Q2
R P2

(A) x Q (t ) (B) x ⊕ Q (t ) P1
Q1
(C) x Q (t ) (D) x  Q (t )
[UPSC ESE 2014]
Q.17 A flip-flop is a
(A) Combinational logic circuit and edge Q2
P2
sensitive
(A) NAND: first (0, 1) then (0, 1) NOR :
(B) Sequential logic circuit and edge
first (1, 0) then (0, 0).
sensitive
(C) Combinational logic circuit and level (B) NAND: first (1, 0) then (1, 0) NOR :
sensitive first (1, 0) then (1, 0).
(D) Sequential logic circuit and level (C) NAND: first (1, 0) then (1, 0) NOR :
sensitive first (1, 0) then (0, 0).
[UPSC ESE 2016] (D) NAND: first (1, 0) then (1, 1) NOR :
Q.18 If the input to a T flip-flop is a 100 MHz first (0, 1) then (0, 1).
signal, the final output of three Tflip-flops [GATE 2009, IIT Roorkee]
in a cascade is Q.22 In the circuit shown in figure, when input
(a) 1000 MHz (b) 520 MHz A = B = 0, the possible logic states of C and
(c) 333 MHz (d) 12.5 MHz D are
[UPSC ESE 2017]

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Digital Electronics [SSC-JE & All State AE/JE] 36 GATE ACADEMY®
A Q.28 A D-flip-flop can be made from a J-K flip-
C flop by making making
(A) J = K (B) J = K = 1
D
B (C) J = 0, K = 1 (D) J = K
(A) C = 0, D = 1 or C = 1, D = 0 [UPPSC AE 2019]
(B) C = 1, D = 1 or C = 0, D = 0 Q.29 Which of the following equations satisfy
(C) C = 1, D = 0 the J-K flip-flop?

(D) C = 0, D = 1 (A) Qn +1 = J nQn + K n Qn

[GATE 2001, IIT Kanpur] (B) Qn +1 = J nQn + K n Qn

Q.23 For a flip-flop formed using two NAND (C) Qn +1 = J nQn + K n Qn
gates as shown in figure. The unstable state
corresponds to (D) Qn +1 = J nQn + K nQn
X
Q [UPPSC AE 2019]
Q.30 A ripple counters speed is limited by the
propagation delay of
Y
Q (A) each flip-flop
(A) X = 0, Y = 0 (B) X = 0, Y = 1 (B) all flip-flop and gates
(C) X = 1, Y = 0 (D) X = 1, Y = 1 (C) flip-flops only with gates

[GATE 1999, IIT Bombay] (D) only circuit gates

Q.24 All the logic gates in the circuit shown [UPPSC AE 2019]
below have finite propagation delay. The Q.31 Which of the following is a sequential
circuit can be used as a clock generator, if circuit ?
(A) AND gate
Y
(B) NAND gate
(C) Bistable multivibrator
(D) EX-OR gate
X
[STATE ESE EE]
(A) X = 0 (B) X = 1
Q.32 If the J-K Flip Hop’s output is zero, then in
(C) X = 0 or 1 (D) X = Y
order to change its output to I the input
Q.25 How many flip flops are required to design
combination
MOD-10 counters?
(A) J = 0, K = X
(A) 2 (B) 3
(B) J = I, K = X
(C) 5 (D) 4
[VS JE Electrical 2021] (C) J = X, K= I
Q.26 A J-K flip-flop is in a ‘No cahange’ (D) J = X. K = 0
conditions when_____. [STATE ESE EE]
(A) J=0, K=0 (B) J=0,K=1 Q.33 The number of unused states in a 4-bit
(C) J=1,K=0 (D) J=1,K=1 Johnson counter is
[AE JE Electrical 2021] (A) 2 (B) 4
Q.27 ABCD Counters can be constructed using: (C) 8 (D) 12
(A) SR Flip-Flop (B) JK Flip-Flops [STATE ESE EE]
(C) JK Flip-Flop (D) Flip-Flop Q.34 Which of the follow ing is not a
[CSEB AE 2018] characteritic of a flip-flop?

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GATE ACADEMY® 37 Sequential Circuits
(A) It is a bistable device M S A J Q
(B) It has two outputs Comb.
logic
(C) It has two outputs which are
B K Q'
complement of each other
(D) It has one input terminal Clock
What is the output of the combination logic
[STATE ESE EE]
circuit to the J input ?
Q.35 The basic sequential logic building block in
which the output follows the data input as (A) AB (B) A
long as the ENABLE input is active, is (C) B (D) AB
(A) J-K flip-flop (B) D flip-flop [UPSC ESE 2008]
(C) T flip-flop (D) D Latch Q.4 The digital circuit shown in the figure
[STATE ESE EE] works as a
Q.36 How many FFs are required to build a
binary counter circuit to count from 0 to D Q
X
1023 ?
CLK Q
(A) 1 (B) 6
(C) 10 (D) 24 (A) JK flip-flop
[STATE ESE EE] (B) Clocked RS flip-flop
Q.37 Which one of the following is not a (C) T flip-flop
sequential circuit / system ? (D) Ring counter
(A) Clocked S-R flip-flop [UPSC ESE 2008]
(B) Shift register Q.5
(C) ROM
(D) Ripple counter
[STATE ESE EE]
Self-Practice Questions (SPQs)
The digital circuit using two inverters as
Q.1 D flip-flop can be made from a J – K flip- shown above acts as :
flop by making (A) A bistable multivibrator
(A) J = K (B) J = K = 1 (B) An astable multivibrator
(C) J = 0, K = 1 (D) J = K (C) A monostable multivibrator
[UPSC ESE 2003] (D) An oscillator
Q.2 A J-K flip-flop can be made from an S-R [UPSC ESE 2010]
flip-flop by using two additional Q.6 Which of the following is correct for a
(A) AND gates (B) OR gates gated D-type flip?
(C) NOT gates (D) NOR gates (A) The output is either SET or RESET as
[UPSC ESE 2008] soon as the D input goes HIGH or
Q.3 The following truth table has to be realized LOW
with the circuit shown in the figure: (B) The output complement follows the
A B Qn +1 input when enable
0 0 Q'n (C) Only one of the inputs can be HIGH at
0 1 1 a time
1 0 Qn (D) The output toggles if one of the inputs
1 1 0 is held HIGH
[UPSC ESE 2013]
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Digital Electronics [SSC-JE & All State AE/JE] 38 GATE ACADEMY®
Q.7 Race-around condition occurs in Codes:
(A) Multiplexer (B) ROM A B C
(C) Flip-flops (D) Voltage-regulator (A) 2 1 3
[UPSC ESE 2015] (B) 3 1 2
Q.8 Consider the following circuits : (C) 2 3 1
1. Full adder (D) 3 2 1
2. Half adder [UPSC ESE 2012]
3. JK flip-flop Q.12 The expression for MOD number for a
4. Counter ripple counter with N flip-flops is
Which of the above circuits are classified as (A) N (B) 2 N
sequential logic circuits?
(C) 2 N −1 (D) 2 N − 1
(A) 1 and 2 (B) 3 and 4
[UPSC ESE 2016]
(C) 2 and 3 (D) 1 and 4
Q.13 The output Qn +1 of a J-K flip-flop for the
[UPSC ESE 2016]
input J = 1, K = 1 is
Q.9 The frequency of the clock signal applied to
the rising edge triggered D-flip-flop shown (A) 0 (B) 1
in figure is 10 kHz. The frequency of the (C) Qn (D) Qn
signal available at Q is :
Q.14
Q
A

B Q

(A) 10 kHz (B) 2.5 kHz The circuit shown in figure is a

(C) 20 kHz (D) 5 kHz (A) R-s latch (B) R-S flip-flop
[UPSC ESE 2007] (C) D latch (D) D flip-flop
Q.10 Which of the following counter results in
Q.15 On the third clock pulse a 4- bit johnson
least delay?
sequence is 1110 at Q0 , Q1 , Q2,Q3 , what will
(A) Ring counter
be the initial sequence of the register.
(B) Ripple counter
(A) 1000 (B) 0001
(C) Synchronous counter
(C) 1110 (D) 0011
(D) Asynchronous counter
Q.16 Identify the characteristic equation of X-Y
[UPSC ESE 2010]
flip flop whose truth table is given
Q.11 Match List-I with List-ll and select the
X Y Q ( n + 1)
correct answer using the code given below
the lists: 0 0 0
List-I 0 1 Q0
A. Shift registers
1 0 Qn
B. Counter
1 1 1
C. Decoder
List-II (A) XY Q (B) XY + XQ
1. Frequency division (C) XQ + YQ (D) XY + XQ + YQ
2. Addressing in memory chips
3. Serial to parallel data conversion
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GATE ACADEMY® 39 Sequential Circuits

Answer Keys

Classroom Practice Questions

1. A 2. B 3. C 4. C 5. C
6. C 7. D 8. D 9. D 10. D
11. D 12. A 13. B 14. A 15. D
16. B 17. B 18. D 19. B 20. C
21. C 22. A 23. A 24. B 25. D
26. A 27. B 28. D 29. A 30. A
31. C 32. B 33. C 34. D 35. B
36. C 37. C
Self Practice Questions
1. D 2. A 3. B 4. C 5. A
6. A 7. C 8. B 9. D 10. C
11. B 12. B 13. D 14. A 15. D
16. C

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 6 ADC and DAC

Classroom Practice Questions (CPQs) List - II (Characteristics)

1. Integrating type
Q.1 The output voltage of a 5-bit D/A binary
ladder that has a digital input of 11011 2. Fastest converter
(assuming 0 = 0 V and 1 = + 10 V) is 3. Maximum conversion time = N – bits
(A) 3.4375 V (B) 6.0 V 4. Uses a DAC in its feedback path.
(C) 8.125 V (D) 9.6875 V Codes: A B C D
[UPSC ESE 2001] (A) 1 4 3 2
Q.2 An 8-bit D/A converter has a full scale (B) 1 3 4 2
output voltage of 20V. The output voltage
(C) 2 4 3 1
when the input is 11011011, is
(D) 2 3 4 1
(A) 160 mV (B) 78 mV
(C) 20 V (D) 17 V [UPSC ESE 2004]
[UPSC ESE 2001] Q.5 In order to build a 3 bit simultaneous A/D
Q.3 Digital measuring instruments use the converter, what is the number of
following three types of A to D converters: comparator circuits required?
1. Dual Slope Type (A) 7 (B) 8
2. Counter Type (C) 15 (D) 16
3. Flash Type [UPSC ESE 2008]
The correct sequence for these converters in Q.6 Match List I with List II and select the
decreasing order of their speed (fastest to correct answer using the code given below
slowest) is the Lists:
(A) 3, 1, 2 (B) 1, 2, 3 List I (Type of N-bit ADC)
(C) 2, 3, 1 (D) 3, 2, 1 A. Flash converter
[UPSC ESE 2001] B. Successive approximation
Q.4 Match List –I (Type of N-bit ADC) with List
C. Counter ramp
– II (Characteristics) and select the correct
D. Dual slope
answer using the codes given below the lists:
List - I (Type of N-bit ADC) List II (Characteristics)
A. Flash converter 1. Integrating Type
B. Successive approximation 2. Fastest converter
C. Counter ramp 3. Maximum conversion time = N bits
D. Dual slope 4. Uses a DAC in its feedback path
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GATE ACADEMY® 41 ADC and DAC
Code: (C) Proportional to Va
A B C D (D) Inversely proportional to Va
(A) 2 3 4 1
[UPSC ESE 2014]
(B) 1 3 4 2
Q.10 A 5-bit D/A converter has a current output.
(C) 2 4 3 1 If an output current is produced for a digital
(D) 1 4 3 2 input of 10100, the value of for a digital
[UPSC ESE 2009] input of 11101 will be
Q.7 Dual-slope integration type Analog-to- (A) 12.5 mA (B) 13.5 mA
Digital converters provide : (C) 15.5 mA (D) 14.5 mA
1. Higher speeds compared to all other [UPSC ESE 2014]
types of A/D converters. Q.11 The speed of conversion is maximum in
2. Very good accuracy without putting (A) Successive approximation A/D
extreme requirements on component converter.
stability. (B) Parallel comparative A/D converter.
3. Good rejection of power supply hum. (C) Counter ramp A/D converter.
4. Better resolution compared to all other (D) Dual slope A/D converter.
types of A/D converters for the same
[UPSC ESE 2015]
number of bits.
Q.12 An A-to-D converter in which one sub
(A) 2 and 3 only
circuit is a D-to-A converter is
(B) 3 and 4 only (A) Parallel A\D converter
(C) 4 and 1 only (B) Dual slope A/D converter
(D) 1, 2, 3 and 4 (C) Successive approximation A/D
[UPSC ESE 2011] converter
Q.8 Consider the following statements for an (D) Extended parallel type A/D converter
/V-bit DACs : [UPSC ESE 2016]
1. R-2R ladder type is based on dual Q.13 A 12-bit A/D converter has a full-scale
slope integration. analog input of 5 V. Its resolution is :
2. R-2R requires resistors of large spread (A) 1.22 mV (B) 2.44 mV
in values.
(C) 3.66 mV (D) 4.88 mV
3. R-2R requires roughly 2N resistors.
[UPSC ESE 2017]
4. R-2R requires roughly N number of Q.14 The analog-to-digital converters are
resistors. employed in :
Which of these statements is/are correct? (A) Voltmeter
(A) 3 only (B) 1 only (B) Wattmeter
(C) 1 and 3 (D) 2 and 4 (C) Energy meter
[UPSC ESE 2011] (D) Digital multimeter
Q.9 A dual slope analog to digital converter Q.15 Which of the following is NOT an Analog-
uses N-bit counter. When the input signal to-Digital Converter?
Va is being integrated, the counter is (A) Successive Approximation Convener
allowed to count up to the value (B) Counter Type
(A) Equal to 2 − 2 N
(C) Dual Slope Converter
(B) Equal to 2 N − 1 (D) R-2R ladder
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Digital Electronics [SSC-JE & All State AE/JE] 42 GATE ACADEMY®
Q.16 Find out the integrating type analog to (C) 8-bit D/A converters
digital converter from the following. (D) Op-amp comparators
(A) flash type converter
Self-Practice Questions (SPQs)
(B) tracking converter
Q.1 Match List-I (ADCs) with List-ll
(C) successive approximation type
(Characteristics) and select the correct
converter
answer using the codes given below the
(D) dual-slope analog to digital converter
lists:
Q.17 A 10-bit D/A converter gives a maximum
List-I
output of 10.23 V. The resolution is
A. Parallel-comparator
(A) 10 mV (B) 20 mV
(C) 15 mV (D) 25 mV B. Successive approximation
Q.18 The ADC that has maximum clock periods C. Dual-slope
equal to number of bits is D. Counter-ramp
(A) Dual slope ADC List-II
(B) Counter ramp ADC 1. Null balancing type
(C) Successive approximation ADC 2. Fastest converter
(D) Flash converter ADC 3. Voltage-dependent conversion time
Q.19 The number of comparators required in a 3- 4. Integrating type Codes:
bit comparator type ADC is A B C D
(A) 2 (B) 3 (A) 2 1 3 4
(C) 7 (D) 8 (B) 2 1 4 3
Q.20 In a flash A to D converter, the priority (C) 1 2 4 3
encoder is used to
(D) 1 2 3 4
(A) Select the first input
[UPSC ESE 2002]
(B) Select the highest value input
Q.2 Which one of the following D/A converters
(C) Select the lowest value input has the resolution of approximately 0.4% of
(D) Select the last input its full scale range ?
Q.21 A 4-bit R/2R ladder digital-to-analog (A) 8-bit (B) 10-bit
converters uses
(C) 12-bit (D) 16-bit
(A) Two resistor values
[UPSC ESE 2006]
(B) Three resistor values
Q.3 Given below are three types of converters :
(C) Five resistor values
1. Successive approximation type
(D) Four resistor values
2. Weighted resistor type
Q.22 The main advantage of the successive -
approximation A/D converter over the 3. R-2 R ladder type
counter - ramp A D converter is its Which of these types are D to A converters?
(A) More complex circuitry (A) Only 1 and 2 (B) Only 2 and 3
(B) Less complex circuitry (C) Only 1 and 3 (D) 1, 2 and 3
(C) Longer conversion time [UPSC ESE 2006]
(D) Shorter conversion time Q.4 Which of the following A/D converter is
Q.23 The practical of binary-weighted digital-to- used in a Digital Storage Oscilloscope
analog converters is limited to (DSO)?
(A) R/2R ladder D/A converters (A) Ramp type
(B) 4-bit D/A converters (B) Successive approximation type

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GATE ACADEMY® 43 ADC and DAC
(C) Dual slope type Q.9 When a large number of analog signals is to
(D) Parallel type be converted to digital form, an analog
multiplexer is used. The A-to-D converter
[UPSC ESE 2007]
most suitable in this case will be
Q.5 In which one of the following types of analog
(A) Forward counter type
to digital converters the conversion time is
practically independent of the amplitude of (B) Up-down counter type
the analog signal? (C) Successive approximation type
(A) The dual slope integrating type (D) Dual slope type
(B) Successive approximation type [UPSC ESE 2016]
(C) Counter ramp type Q.10 Which one of the following Analog-to-
Digital converters (ADC) does not use a
(D) Tracking type
DAC?
[UPSC ESE 2009] (A) Digital ramp ADC
Q.6 The resolution of a DCA depends on which (B) Successive approximation
of the following?
(C) Single-slope ADC
(A) The number of bits (D) Counting ADC
(B) Monotonocity [UPSC ESE 2017]
(C) Reference voltage Q.11 The resolution of 6-bit DAC will be nearly
(D) The values of resistance (A) 4.6% (B) 3.2%
[UPSC ESE 2009] (C) 1.6% (D) 1.2%
Q.7 A dual slope Analog to Digital converter [UPSC ESE 2020]
1. Responds very fast. Q.12 The resolution of a 12 bit Analog to Digital
2. Has better accuracy. converter in percent is
3. Requires an accurate and stable dc (A) 0.01220 (B) 0.02441
source. (C) 0.04882 (D) 0.09760
4. Requires a buffer at the input side. [UPSC ESE 2002]
(A) 1 is not correct Q.13 A 8-bit A/D convertor is used over a span
of
(B) 2 and 3 are correct
zero to 2.56 V. The binary representation of
(C) 3 and 4 are correct 1.0 V signal is
(D) 1, 2, 3 and 4 are correct (A) 01100100 (B) 011 10001
[UPSC ESE 2011] (C) 10100101 (D) 10100010
Q.8 Dual slop integration type analog-to-digital [UPSC ESE 2013]
converters provide : Q.14 Consider the following statements:
(A) Higher speed compared to all other 1. Flash type ADCs are considered the
types of A/D converters. fastest.
(B) Very good accuracy without putting 2. In successive approximation type
extreme requirement on components ADCs,
stability. conversion time depends upon the
(C) Poor rejection of power supply hum. magnitude of the analog voltage.
(D) Better resolution compared to all other 3. Counter-type ADCs work with fixed
type of A/D converters for the same conversion time.
number of bits. 4. Dual slope ADCs are considered the
[UPSC ESE 2013] slowest.

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Digital Electronics [SSC-JE & All State AE/JE] 44 GATE ACADEMY®
Which of the above statements are correct?
(A) 2 and 3 only
(B) 2 and 4 only
(C) 1 and 4 only
(D) 1 and 3 only
[UPSC ESE 2018]

Answer Keys

Classroom Practice Questions

1. C 2. D 3. D 4. D 5. A
6. A 7. A 8. A 9. B 10. D
11. B 12. C 13. A 14. D 15. D
16. D 17. A 18. B 19. C 20. B
21. A 22. D 23. B
Self Practice Questions
1. B 2. A 3. B 4. A 5. B
6. A 7. A 8. B 9. C 10. C
11. C 12. B 13. A 14. C

Gate Academy Shop Address : Street 04, Narsingh Vihar, Katulbod, Bhilai 490022 (C.G.), Contact : 97131-13156 Online Test Series
[Link] Live class room: [Link] [Link]