1. Difference between 8085 & 8086 2. Pin Diagram of 8085 & 8086 ? 3. Addressing Mood of 8085? b.

3. Addressing Mood of 8085? b. Execution Unit (EU) Timing and control unit: Generates control signals 8. Explain the Memory Segmentation of
Microprocessor.? The 8085 microprocessor supports five addressing Decodes and executes instructions using a 16-bit (RD, WR, ALE, etc.) for bus operations. 8086 with diagram.
Feature 8085 8086 modes. Here they are with brief definitions and ALU and internal registers. Address / address-data buffers: 16-bit address bus Concept: 8086 uses segmentation to manage up
microproces microprocesso examples: Consists of: (A0–A15) and 8-bit multiplexed AD0–AD7 data bus. to 1 MB (2²⁰) memory using 20-bit addresses.
sor r a. Immediate addressing mode General-purpose registers: AX, BX, CX, DX (16-bit). Segment: 64 KB block (16-bit segment base).
Data bus 8-bit 16-bit Operand (8-bit or 16-bit data) is specified directly Pointer and index registers: SP, BP, SI, DI. 6. Explain the 8085 Flag Register with Offset: 16-bit displacement within the segment.
width in the instruction. Flag register (PSW) storing status flags (ZF, SF, CF, diagram. The flag register in 8085 is 8-bit, but Physical address = (Segment × 16) + Offset (or (seg
Address 16-bit (64 KB 20-bit (1 MB Example: MVI A, 05H, ADI 05H. AF, OF, etc.). only 5 bits are used as flags. × 10H) + offset).
bus width memory) memory) b. Register addressing mode Receives instructions from the BIU’s queue and Bit positions and meaning (draw as a 7→0
Basic 8-bit, 16-bit, Operand is present in a register (or register pair). passes operand addresses back to BIU. labeled bar):
architect accumulator register-based Example: MOV A, B, ADD C, PUSH D. b. Key architectural features
B B B B B B B B
ure -based (general-purpo c. Direct addressing mode Segmented memory model: up to 1 MB memory
it it it it it it it it
se registers) The 16-bit address of the operand is given directly using 20-bit address (segment:offset).
7 6 5 4 3 2 1 0
ALU size 8-bit ALU 16-bit ALU b in the instruction. Pipelining: BIU fetches next instructions while EU
Clock About 3 MHz 5, 8, or 10 Example: LDA 2500H, STA 2050H. executes the current one, increasing throughput.
frequency (single MHz d. Register indirect addressing mode Two modes: Minimum mode (single-processor) A C
S Z — — — P
version) (multiple  The address of the operand is held in a and maximum mode . C Y

versions) The 8086 is a 16-bit processor split into two register pair; the data is in memory at that 5. Explain the architecture of 8085
S (Sign flag, bit 7): 1 if result is negative (MSB = 1).
Memory Not Segmented units: BIU and EU, with segmented memory and address. with a neat diagram.
Z (Zero flag, bit 6): 1 if result is zero.
segmenta supported (CS, DS, SS, pipelining.  Example: MOV A, M (HL pair holds the The 8085 is an 8-bit microprocessor with Von Segment types:
AC (Auxiliary Carry flag, bit 4): 1 if carry from bit-3
tion ES) Blocks (draw like a two-unit block diagram): address). Code segment (CS): Program instructions.
(during BCD operations).
Pipelining No pipelining Has 6-byte Bus Interface Unit (BIU): e. Implied (implicit) addressing mode Data segment (DS): Data variables.
P (Parity flag, bit 2): 1 if result has even parity.
instruction • Segment registers: CS, DS, SS, ES (16-bit). Stack segment (SS): Stack (SP/BP).
CY (Carry flag, bit 0): 1 if carry out from MSB
queue • IP (Instruction Pointer). Extra segment (ES): Extra data (e.g., string
(addition/subtraction) or borrow (subtraction).
(pipelining) • Instruction queue (6-byte) for pipelining. operations).
7. Highlight the functions of BIU (Bus Interface
Operating Single mode Minimum • Address adder for 20-bit physical address 9. Explain different Addressing Modes of 8086 with
Unit) and EU (Execution Unit) in 8086
modes only mode and (segment:offset). examples.
Bus Interface Unit (BIU):
maximum Execution Unit (EU): 8086 supports about 8 main addressing modes:
Fetches instructions from memory and stores them
(multiprocesso  16-bit ALU. Immediate
in the 6-byte instruction queue.
r) mode  General-purpose registers: AX, BX, CX, DX. • Operand is in the instruction.
Reads/writes data from/to memory and I/O ports.
Instructio 8-bit 16-bit, richer  Pointer and index: SP, BP, SI, DI. • Example: MOV AX, 0500H
Computes 20-bit physical addresses using
n set oriented, (many  16-bit flag register (PSW) with 6 status flag Register
Both the operand and its destination are fixed by segment: offset (e.g., CS + IP, DS + BX, etc.).
simpler addressing • Both operands are registers.
the instruction; no explicit address is given. Handles all bus operations (address driving, RD,
modes) • Example: MOV AX, BX, ADD AL, BL
Example: CMA (complement accumulator), HLT. WR, DT/R, DEN, ALE, etc.).
Register Fewer 8-bit Many 16-bit Direct
4. Architecture of 8086? Execution Unit (EU):
set registers (A, registers (AX, • Memory address given directly.
• Decodes and executes instructions taken
B, C, D, H, L, BX, CX, DX, BP, • Example: MOV AX, [2000H] (assuming DS
from the BIU’s queue.
etc.) SP, SI, DI, segment)
• Performs arithmetic and logical
segment) Register indirect
operations using the ALU.
• Address in a base register.
• Manages general-purpose, pointer, and
• Example: MOV AX, [BX]
index registers and updates the flag register.
Register relative
Neumann architecture (program and data share the • Does not directly drive the buses; it passes
• Base register + 8-bit/16-bit displacement.
same memory). operand addresses to BIU.
• Example: MOV AX, [BX+10]
Main blocks (you can draw as a block diagram):
Base indexed
The 8086 microprocessor has a 16-bit Arithmetic and Logic Unit (ALU): 8-bit unit that
performs arithmetic and logical operations using • Base + index register.
architecture divided into two main units: the Bus
the accumulator and a temporary register. • Example: MOV AX, [BX+SI]
Interface Unit (BIU) and the Execution Unit (EU).
Accumulator (A): 8-bit register used as primary Relative indexed
a. Bus Interface Unit (BIU)
operand and result register. • Base + index + displacement.
Handles all communication with memory and
Flag register: 8-bit register having 5 active flags (S, • Example: MOV AX, [BX+SI+20]
I/O through the address, data, and control buses.
Z, AC, P, CY). Implied
Contains:
Register array: General-purpose registers B, C, D, E, • No explicit operand (intrinsic).
 Segment registers: CS (code), DS (data), SS
(stack), ES (extra). H, L arranged in pairs (BC, DE, HL). • Example: STC, CLD

 Instruction Pointer (IP), which holds the Program counter (PC) and stack pointer (SP): 16-bit
offset of the next instruction. registers for program sequencing and stack
 Instruction queue (6 bytes) that prefetches addressing.
instructions for pipelining. Instruction registers and decoder: Fetches
instruction byte and decodes it.
 10. Explain the Interrupt Structure of 8051 with resources.
14. Explain the I/O interfacing techniques in 8085. 15. Minimum and Maximum modes of #Advantages of Microcontrollers Storage: A computer's storage is a
priority levels. ◆ The flexibility Embedded Operating System are device that contains the digital data a user saved.
Also discuss: 8086? Minimum mode and maximum mode are
8051 has 5 interrupts: specifying the processor chips that are due to Examples of this are a solid state drive (SSD) or a
Memory-mapped I/O the two operating modes of the 8086, selected by hard disk drive (HDD).
Two external interrupts: INT0 and INT1 the programmable nature.
I/O-mapped I/O. Differences between them with the MN/MX pin: MN/MX = 1 gives minimum mode, ◆ In fact, faster speed of execution is fully Input and output (IO) devices: Input devices such
(hardware-triggered).
examples. and MN/MX = 0 gives maximum mode. In integrated into the processor such as a computer as a keyboard and mouse enable a user to bring
Two timer interrupts: TF0, TF1. data to the computer. Output devices like a
I/O interfacing techniques: minimum mode, the 8086 is used as a single- on a chip. These devices are operating at a faster
One serial-port interrupt: RI/TI. speed to executing the instructions to the monitor, printer, and speaker allow the computer
8085 supports two schemes: memory-mapped processor system and generates all control signals
Priority levels (in standard 8051): general purpose of microprocessors. to send output to the user, depending on the data
I/O and I/O-mapped I/O (also called port-mapped itself; in maximum mode, the 8086 is used in it received Ê
• Priority can be set to two levels: high ◆ More than one task may perform the PLCs
I/O). multiprocessor/coprocessor systems and external and microcontrollers are repetitive for
(1) and low (0).
Memory-mapped I/O hardware like the 8288 bus controller generates human attention.
• By default, INT0 > TF0 > INT1 > TF1 > RI/TI. ◆ The microcontrollers are controlling the read-
• I/O devices are assigned memory addresses. control signals from the status lines.
Key points: only memory that is rather than the random
• Same memory-access instructions are Minimum mode
• Each interrupt has a vector address (e.g., access memory
used: LDA, STA, MOV M, A, etc. • Used for standalone 8086 systems.
Applications of Microcontrollers
0003H for INT0, 000BH for TF0, etc.).
• ALU operations can be applied directly on • The processor itself provides signals such as ◆ We know that microcontrollers are used for
• Hardware can be edge-sensitive (INT0, INT1)
I/O data. RD, WR, ALE, INTA, DT/R, and DEN. most of the household and industrial
or level-sensitive (configurable). applications. The huge areas of applications are
I/O-mapped I/O • Simpler hardware, because no bus controller
as follows.
• I/O devices are given separate 8-bit port is needed.
11. Explain 8-bit Subtraction. ◆ Evolution of Microcontrollers measuring the
addresses (0–255). Maximum mode physical quality for example force,
In 8-bit processors (like 8085). Microprocessor Vs Microcontroller Comparison:
• Only IN and OUT instructions are used: Used when more than one processor or an 8087 acceleration, stress, pressure, velocity an also
Subtraction is done as 2’s complement addition: strain.
IN 05H → A = data from port 05H OUT 03H coprocessor shares the system. Microcontrolle r
A - B = A + (2\)’s complement of \(B\) Parameter Microprocessor
→ send A to port 03H The 8086 outputs status signals S2, S1, and S0 instead ◆ The microcontroller is based upon the
The ALU subtracts by taking 2’s complement of the laboratory instruments to measuring the
of directly generating all control signals. An
subtrahend (B) and adding to the minuend (A). voltage, phase angle, energy, frequency and
Memory-mapp ed I/O I/O-mapp ed external bus controller converts these status Processes data in
Feature also power. Controls specific tasks
Flags set after subtraction: general-
I/O signals into bus control signals. in embedded
◆ Traffic light controlling system Main role purpose
systems
Carry (CY): 1 if a borrow is needed from the MSB. ◆ Robot ARM positioning control computing
16. Segment registers and memory
Zero (Z): 1 if result = 0. systems
Separate 8-bit segmentation Segment registers in 8086 are CS, ◆ As a matter of fact, both the stepper
Sign (S): 1 if result is negative (MSB = 1). motor control and DC motor
Address space Shares memory space port DS, SS, and ES. They store the starting address of a
only; memory andCPU, memory, and I/O
SUB B → A = A - B; flags updated accordingly. memory segment, and memory segmentation What is Micro Computer?
(0–64K) space (0– Component s I/O are usually are
12. Explain the instruction set of 8085 divides the 1 MB memory space into 64 KB external integrated on
255 ports) The term microcomputer is associated with computers that
one chip
microprocessors? segments so the 16- bit processor can access the are smaller than minicomputers and are designed
8085 has around 74–78 instructions, classified as: for personal use i.e., they can be used by a
full address space using a segment plus an offset.
Instructio ns memory Only IN / OUT single user at a time. A microcomputer is designed using a External RAM/ROM/cach
On-chip memory
Data transfer (copy data, no arithmetic) Segment registers Memory e needed available
used instructions single-chip microprocessor
MOV A, B → copy B into A CS (Code Segment): holds the segment for * What is the Application of microcomputers?
MVI A, 05H → load immediate into A instructions. ◆ Offered to refer to as a personal
LDA 2500H → load A from memory 2500H ALU computer. External peripherals
Not directly DS (Data Segment): holds the segment for data. ports required
Built-in I/O ports
STA 2050H → store A into memory 2050H. operation s on ◆ Many uses, style, and purpose.
Allowed allowed SS (Stack Segment): holds the segment for stack
I/O data ◆ Use of manage resource of the network.
Arithmetic (8-bit operations) operations. ◆ It uses the real estate sector.
ADD B → A = A + B SUB C → Power consumptio
ES (Extra Segment): used as an additional data * Advantages of microcomputer:
A=A-C n Higher Lower
segment. ◆ This computer is widely used today.
INR H → increment H DCR A Uses Memory segmentation ◆ The microcomputer is small in size.
Uses
→ decrement A ADI Hardware port-select signals The 8086 uses logical address =
◆ The microcomputer is used to design
memory-select Usually higher for Usually optimized for
08H → A = A + 08H different software and app.
control (IO/M, RD, segment:offset form. Speed complex control tasks
signals (RD, ◆ This type of computer is a low cost, so all computation
Logical signals WR)
ANA B → A = A ∧ B (AND) ORA C
The segment value is shifted left by 4 bits, and then the users can easily buy.
WR)

→ A = A ∨ C (OR) XRA D
the offset is added to obtain the 20-bit physical ◆ No need for highly trained staff for
Higher system cost Lower system cost
operating microcomputer to office work.
→ A = A ⊕ D (XOR)
address.
Example: * Basic components of a microcomputer:
This allows 16-bit registers to address up to 1 MB of
CMA → A = A¯ (complement) • Memory-mapped: Port mapped at memory Microcomputer devices are small,
memory. relatively affordable systems with different parts Larger system setup
location 2FF0H; use LDA 2FF0H. Compact
Branching 17. Address calculation in 8086 with depending on their use. Desktop computers and
JMP 2000H → unconditional jump JZ • I/O-mapped: Port 07H; use IN 07H or OUT
examples. Address calculation in 8086 uses the laptops are similar in composition, while tablets
2500H → jump if Z = 1 07H. typically come with no additional hardware, such as Washing machines,
formula: Physical address = Segment × 10H + microwave
JC 3000H → jump if carry = 1 CALL a keyboard. Regardless of their function, these
Offset. laptops, servers ovens, robots,
personal-use devices share these basic components: Applications
4000H → call subroutine RET → automotive
Examples Central processing unit (CPU): This is a computer's ECUs
return from subroutine • If CS = 4042H and IP = 0580H, then physical main component and responsible for processing
address = 40420H + 0580H = 41000H. instructions and data, receiving input and producing
output, and running applications and the operating
• If DS = 3032H and BX = 3040H, then physical
system. A single-chip microprocessor is the CPU of
address = 30320H + 3040H = 33360H. microcomputer devices.
• In general, the offset may come from Operating system (OS): The OS is software that serves as a
registers like IP, BX, SI, DI, BP, or SP platform for other computer programs and enables
depending on the addressing mode. individuals to use the device through an interface.
Its primary task is to manage the computer's
 An 8051 microcontroller has the following 12
major components:
a) ALU (Arithmetic and Logic Unit)
b) PC (Program Counter)
c) Registers
d) Timers and counters
e) Internal RAM and ROM
f) Four general purpose parallel input/output ports
g) Interrupt control logic with five sources
of interrupt
h) Serial date communication
i) PSW (Program Status Word)
j) Data Pointer (DPTR)
k) Stack Pointer (SP)
l) Data and Address bus.
What is TCON?
(Timer Control Register) – At the risk of a slight
oversimplification that we will address later, we
only use half of the TCON register for timing and
counting purposes. This register is used to initialize
the counting and to indicate when the timers have
reached their counting limit.
What is SPI – Serial Peripheral Interface? :
t is a three-wire-based communication system. One wire
each for Master to slave and Vice-versa, and one
for clock pulses. There is an additional SS (Slave
Select) line, which is mostly used when we want to
send/receive data between multiple ICs.
What is Von Neumann Architecture?
Historically, there have been two types of computers:
those that have a very defined function and
cannot be programmed, such as calculators, and
those that can be programmed (these can be
configured to perform a variety of activities, and
they store applications).
he contemporary computer is built on John von
Neumann's concept of stored programmes.
rograms and data are kept in a distinct storage unit
called memories in this stored-program approach,
and they handle the same. A computer developed
with this design would be considerably easier to
reprogram, thanks to this unique notion.
• Here is the basic structure

It’s also known as an IAS computer, and it’s made

up of three fundamental components:
◆ The CPU or Central Processing Unit
◆ The Main Memory Unit (most important part
of the system)
◆ The I/O Device or the Input/Output Device
 Harvard Architecture Suggestions . 3. Interrupt System of 8085 6. Timer and Counter Operations in 8051 9. Types of 8085 Instructions 12. Address Calculation in 8086
In a normal computer that follows von Neumann 1. 8085 Subtraction Program The guide explains that interrupts are requests that The guide explains that the 8051 has two internal The original guide groups 8085 instructions into The physical address in 8086 is obtained by shifting
architecture, instructions, and data both are The original document includes an 8085 assembly temporarily stop the main program and force the 16-bit timer/counter units, Timer 0 and Timer 1, four categories. the segment value left by 4 bits and then adding the
stored in the same memory. So same buses are program to subtract one 8-bit number from another
Physical Address = (Segment Register × 10𝐻)
processor to execute an Interrupt Service Routine controlled by TMOD and TCON registers. In timer offset.
used to fetch instructions and data. This means and store both the result and the flag status in Category Purpose Examples
+ Offset
(ISR). It distinguishes between hardware interrupts mode, counting is driven by the internal clock,
the CPU cannot do both things together (read the memory. A cleaned version of the logic is shown and software interrupts. while in counter mode, the count changes
instruction and read/write data). Harvard below. Hardware interrupts according to transitions on external input pins.
Architecture is the computer architecture that MVI A, 45H ; Load minuend into accumulator TRAP, RST 7.5, RST 6.5, and RST 5.5 are vectored Move data betweenMOV A, B, LDAX
Operating modes Example 1
contains separate storage and separate buses MVI B, 62H ; Load subtrahend into register B Data transfer registers and D, LXI H,

3456𝐻 × 10𝐻 = 34560𝐻

interrupts, meaning each has a fixed service Mode 0: 13-bit Given CS = 3456H and IP = 1200H:
(signal path) for instruction and data. It was SUB B ;A←A-B memory 9000H,
address. timer. Mode 1: 16-
basically MOV L, A ; Save result temporarily MVI C, 45H

34560𝐻 + 1200𝐻 = 35760𝐻

INTR is non-vectored, so the external device must supply bit timer.
developed to overcome the bottleneck of Von PUSH PSW ; Push accumulator and flags the instruction during interrupt acknowledge. Mode 2: 8-bit auto-reload mode.
Neumann’s Architecture. The main advantage POP H ; H ← accumulator, L ← flags Software interrupts Mode 3: Split timer mode. Perform addition,
of having separate buses for instruction and MOV A, L ADD B, SUB C, INR
The document notes that software interrupts are 7. 8085 Program for 16-Bit Addition subtraction, So the physical address is 35760H.
data is that the CPU can access instructions STA 3001H ; Store flags at 3001H Arithmeti c A, DCX H,
generated by RST 0 through RST 7, and theThe attached document also includes a program that increment, Example 2
and read/write data at the same time. MOV A, H ADI 05H

Vector Address = Vector Number × 8 2000𝐻 × 10𝐻 = 20000𝐻

vector address is calculated as: adds two 16-bit numbers from memory and decrement Given DS = 2000H and BX = 0350H:
STA 3000H ; Store result at 3000H stores the result along with the final carry. The
Neumann Harvard Architecture
Parameters HLT
20000𝐻 + 0350𝐻 = 20350𝐻
Architecture cleaned assembly listing is shown below.
Notes Interrupt priority and masking LHLD 4000H ; Load first 16-bit number into HL XCHG
SUB B subtracts register B from accumulator A. The priority order is TRAP, RST 7.5, RST 6.5, RST 5.5, and Perform bitwise
; Move it to DE ANA B, XRA M,
Von Harvard PUSH PSW and POP H are used here to capture the and
Neumann Architecture is a INTR. Interrupt masking is controlled using SIM, LHLD 4002H ; Load second 16-bit number into HL Logical CMP D, So the physical address is 20350H.
flag register along with the accumulator contents. comparison
Architecture is modern type of while interrupt mask and pending status can be MVI C, 00H ; Clear carry tracker CMA, RRC 14. Exam Revision Points
he result is stored at 3000H and the flags byte at operations
ancient type computer read using RIM. DAD D ; HL ← HL + DE • 8085 supports five addressing modes:
computer architecture 3001H. JNC STORE ; If no carry, skip increment INR C immediate, register, direct, indirect, and
Definition
architecture follows the 2. Addressing Modes of 8085 Vector addressTrigger type Maskable status
; Carry occurred JMP 2500H, JC implied.
Interrupt
follows the concept of the The document states that the 8085 supports Change
concept of relay-based STORE: SHLD 4004H MOV Branchin g 3000H, • 8085 hardware interrupt priority is TRAP,
five main addressing modes used to access execution
stored-program model by A, C CALL RST 7.5, RST 6.5, RST 5.5, then INTR.
operands from registers or memory sequence
computer. Harvard Mark I. Edge and level STA 4006H ; Store carry byte HLT 4000H, RET • 8086 uses BIU and EU to support pipelining
Non- maskable
TRAP 0024H sensitive Notes through a 6-byte queue.
Addres 10. Internal Architecture of 8086
Meanin DAD D adds the DE register pair to HL. • 8086 has minimum and maximum modes
It uses two separate sing Example
uses one g The sum is stored at 4004H and 4005H, and the carry The guide describes the 8086 as a 16-bit depending on system configuration.
single physical physical mode
Rising edge byte is stored at 4006H. microprocessor with a 20-bit address bus and a 16-
address for addresses for • 8086 segment registers are CS, DS, SS, and
Physical address storing and 7.5 003CH sensitive Maskable 8. Stack Operations in 8085 bit data path, capable of addressing 1 MB of
accessing and storing ES.
both accessing both
Operan The stack in 8085 is a Last-In, First-Out (LIFO) memory. Its architecture is divided into two major
instructions and • 8051 uses Harvard architecture and
data and
d is part memory structure managed by the Stack Pointer units: BIU and EU.
instructions. data. contains two timer/counter units.
Immed MVI A, 32H, LXI H, High level sensitive (SP). It is used for subroutine calls, interrupts, and BIU functions
of the 6.5 0034H Maskable
iate 2000H temporary storage of register values. Handles memory and bus operations. Contains
instruct
ion PUSH operation segment registers and the instruction pointer.
common
uses separate buses Maintains the 6-byte instruction queue.
signal path High level sensitive For PUSH, the stack pointer is decremented and data is
for the 5.5 002CH Maskable
(bus) helps in EU functions
𝑆𝑃 ← 𝑆𝑃 − 1, [𝑆𝑃] ← High byte
Bus paths transfer of both stored in memory in two steps.
transfer of Operan Decodes and executes instructions.
both instruction data and
Registe d is in a Contains ALU, control logic, flag register, and
𝑆𝑃 ← 𝑆𝑃 − 1, [𝑆𝑃] ← Low byte
data. instructions. MOV A, B, ADD C
CPU Non- vectored High level sensitive
r INTR Maskable working registers.
register 11. Segment Registers and Memory
requires two clock
executes any 4. 8086 Instruction Queue and Pipelining POP operation Segmentation in 8086
cycles for
Number of cycles instruction
executing a 16-bit The rewritten notes describe the 8086 as being For POP, data is read back from memory and the stack The 8086 divides the 1 MB memory space into
using only one
overlapping segments of up to 64 KB each. This
Low byte ← [𝑆𝑃], 𝑆𝑃 ← 𝑆𝑃 + 1
single
single cycle. memor divided into the Bus Interface Unit (BIU) and pointer is incremented.
instruction. Execution Unit (EU), which operate in parallel. The helps a 16-bit processor access a 20-bit address
y
space efficiently.
High byte ← [𝑆𝑃], 𝑆𝑃 ← 𝑆𝑃 + 1
Direct address STA 4500H, LDA 2500H BIU contains a 6-byte instruction queue that
is prefetches instruction bytes while the EU executes
What is meant by serial communication? How it Register Function
explicitl the current instruction.
works:
y given Advantages
ata is sent as a stream of bits (0s and 1s) over one or two
Fetch and execute phases overlap, increasing Holds the base address of the code
signal lines (e.g., TX and RX), usually with start and
throughput. segment
stop bits to frame each byte. Register The BIU and EU can work in parallel for better
Vs parallel communication: pair performance.
Parallel communication sends several bits at once holds MOV A, M, STAX D Holds the base address of the data
Indirec Limitation
over many wires; serial uses fewer wires, is cheaper, the microprocessor_compre segment
t Branch instructions flush the queue, causing a delay
and is preferred for long-distance links (like RS-232, memor hensive_guide.docx while the new instruction stream is fetched.
USB, CAN). y 5. 8051 Memory Organization Holds the base address of the stack
Transmission modes: Simplex (one-way), address The original file states that the 8051 follows segment
alf-duplex (two-way, but not at the same time), or full-
Harvard architecture, which separates code
duplex (both directions simultaneously).
Operan memory and data memory. Program memory can
Common examples: Holds the base address of an extra
d is go up to 64 KB, while internal data RAM is
UART-based links (RS-232, GPS modules, sensors), data segment
implied organized into several functional areas.
I²C, SPI, CAN, and USB all use serial communication Implie
by the CMA, RAR Internal RAM areas
principles. d
instruct Register banks: 00H to
ion 1FH.
itself Bit-addressable RAM: 20H to 2FH.
General-purpose RAM: 30H to 7FH.