Bangalore Institute of Technology, Bangalore

BVL613A-Low Power VLSI

Design
Module - 3
Dr Jalaja S
Associate Professor/EE (VDT)
Module 3: Low Power Circuit Techniques
• Introduction
• Power Consumption in Circuits
• Flip-flops and Latches
• High Capacitance Nodes
• Energy Recovery
• Reversible Pipelines
• High-Performance Approaches ....
Inverter Capacitance Analysis & Dynamic Power Consumption

1. Inverter Capacitance Components

In a CMOS inverter, capacitance arises from multiple sources:
[Link] Capacitances:
1. Gate Capacitance (Cgs,Cgd​):Capacitance between the gate and source/drain
due to the thin oxide layer.
2. Overlap Capacitance (Cov): Due to the gate extending over the source/drain
diffusion regions.
3. Drain-Bulk and Source-Bulk Junction Capacitance (Cdb​,Csb​): Reverse-biased
pn-junction capacitance.
Cont..
Parasitic Capacitances:
• Wiring Capacitance (iC wring): Capacitance due to interconnects.
• Load Capacitance (CL): External capacitance due to fan-out (next-
stage gates).
Total Effective Load Capacitance:
• Ceff=Cint+CL
• where Cint is the internal capacitance of the inverter, and
CL​ is the load capacitance.
Dynamic Power Consumption
Dynamic power in a CMOS inverter is consumed primarily due to charging
and discharging of capacitive loads.
Formula for Dynamic Power

where:
• α = Activity factor (probability of switching per clock cycle, typically 0.5 for
balanced signals),
• CL​ = Load capacitance,
• Vdd​ = Supply voltage,
• f = Clock frequency.
Power Consumption Breakdown
Charging Phase:
• When input transitions from LOW to HIGH, the PMOS charges the load
capacitor.
• Energy drawn from the supply:
•Discharging Phase:
•When input transitions from HIGH to LOW, the NMOS discharges CL to
ground.

•Energy stored in CL is dissipated as heat in the NMOS transistor.

•Total Energy per Cycle:
•The energy per transition is:
Reducing Dynamic Power
[Link] Vdd: Since power scales as Vdd2​, reducing the supply voltage
significantly decreases dynamic power.
[Link] Capacitance (CL​): Optimizing transistor sizing, reducing
interconnect capacitance, and using advanced low-capacitance
materials.
[Link] Switching Activity (α): Implementing clock gating and
power gating techniques to minimize unnecessary transitions.
[Link] Frequency (f): Reducing clock frequency helps limit power
consumption but may impact performance.
Dynamic power consumption
• Capacitance on node f (output):
• Junction cap Cdb,p and Cdb,n
• Gate capacitance Cgd,p and Cgd,n
• Interconnect cap
• Receiver gate cap
CMOS Inverter Gate Capacitances
• Gate capacitances CGD,p and CGD,n:
• Just after the input switches(t = 0+), what regions are transistors in?
• One is in cutoff: CGD = Overlap Cap
• One is in Saturation: CGD = Overlap Cap
• Therefore, gate-to-drain capacitance is due to overlap capacitance :

• However, also need to consider Miller effect

CMOS Inverter Capacitances: Miller Effect
CMOS Inverter Capacitances: Receiver
Inverter Capacitances: Analysis
Dynamic Power Consumption in CMOS Inverter
Dynamic Power Consumption in CMOS Inverter
Dynamic Power Consumption in CMOS Inverter
Dynamic Power Consumption in CMOS Inverter

• The general formula for dynamic power consumption in CMOS

circuits can be expressed as:
 Switching Probabilities

Figure (a) Inverter Capacitances, (b) The Load Capacitance and (c) the Miller Capacitance
Switching Probability and Dynamic Power Consumption
Switching Probability and Dynamic Power Consumption
Switching Probability and Dynamic Power
Consumption
Effective Capacitances

• Figure (a). Capacitances in a MOSFET (b) A CMOS Gate, (c). A

Transmission Gate.
Effective Capacitances
 Cont..
• In Figure b we show a simple static CMOS gate.
• sum all capacitances which are related to the parallel transistor combination (the
p-transistors in Figure b), in the same way as the inverter transistors.
• For the series combination we have two nodes with capacitance, CN1 and CN2.
CNl includes CD of T2 and Cs of T 1 and a Miller capacitance of CGs+CG of Tl and
CGD of T2.
• It is either charged to Vdd-VT (if T1 is conducting and T2 nonconducting when the
p-net is conducting) or not charged at all (if T1 is open when the p-net is
conducting).
• Instead of dealing with this rather complicated model in the following, we will
simplify our model by estimating the extra charge introduced by each series
transistor to be the same as introduced by an extra parallel transistor. We thus
add CD+2CGD from T2 to CN2 and let this be the effective capacitance CL.
• estimate the effective output capacitance of a gate
Cont..

• n is the total number of transistors in the stage and m is the total

number of load transistors.
• If transistors are different in sizes or have different capacitances of other
reasons, the formula will be changed into a sum over all transistors
involved.
• Co and Cj represents effective transistor output and input capacitances
respectively.
Cont..

• For a transmission gate, Figure c, This stage does not amplify the
signal, therefore it do not have a Miller effect.
• For this gate the "input" capacitance on the transistor gates are
CTi = CG + CGS + CGD each and the "output" capacitance at each
source/drains of the transmission gate is CTo = CD + CDS’
however use CTi = Ci and CTo = Co for simplicity.
Short-circuit Power Consumption
•Short-Circuit Current in CMOS Gates
•When an input signal has a nonzero rise or fall time (τ), both nMOS
and pMOS transistors momentarily conduct.
•This leads to a short-circuit current that flows directly from Vdd to
ground, without contributing to charging/discharging the load
capacitance (CL).

•Short-Circuit Power Consumption (Psc)

•A simple static model provides an estimation for Psc.
•A more accurate dynamic model suggests that the static estimation
may overestimate Psc by a factor of three.
 Cont..
Impact of Node Activity
• The probability of a transition occurring is related to the node’s activity:
• For clocked nodes: 1/T=2fe
• For logic signals: 1/T=uafe​ (where ua​ is the activity factor, and fe​ is the operating
frequency).
Practical Implications
• Psc is usually less than 10% of dynamic power (Pd) in well-designed
circuits.
• However, Psc becomes significant when input signals transition slowly
(i.e., large τ).
• This highlights the importance of keeping signal transitions sharp to
minimize short-circuit power dissipation.
Static Power Consumption

Figure (a). A pseudo-nMOS inverter, (b). A precharged inverter

Cont..
•Static power consumption in CMOS circuits arises due to leakage currents in
transistors and pn-junctions.
•Inverter Model: (Refer to Figure a)
•Low Input: Leakage current of the nMOS transistor (IdOn​).
•High Input: Leakage current of the pMOS transistor (IdOp​).

•Assuming equal probability of logic levels , the average static power

consumption simplifies accordingly.
Cont..
• Let us take the pseudo-nMOS inverter in Figure a
• p-transistor behaves as a current generator with current I0, and it is
sized in such a way that its current is much lower than the maximum
current of a conducting n-transistor.
• For a low input, only the p-transistor is conducting, so the output is
high.
• For a high input the n-transistor is conducting, making the output low.
• The low output voltage is here larger than zero, as the p-transistor
current, I0, passes through the n-transistor, giving rise to a voltage
drop of about

• The static power consumption is here given by:

Cont..
• where refers to the output signal.
• Thus, assuming I0, to be much less than the current capability of the
n-transistor means that the speed is given by the rise time, which is

• The so called power-delay product. Ptd. can then be estimated to:

Precharged Circuits
What is Precharging?
• A technique used in dynamic CMOS circuits to save transistors and
increase speed.
• Key Concept:
• The circuit precharges the output to a known state before evaluation.

Example: Precharged Inverter (Figure b)

• Two Phases:
• Precharge Phase (Clock = Low):
• A pMOS transistor charges the output to HIGH.
• Evaluation Phase (Clock = High):
• The output is determined by the input.
• If the input is HIGH, the nMOS pulls the output LOW.
Cont..
• The dynamic power consumption of this stage can be expressed as:
Glitches

• Figure (a) A CMOS XOR gate (b) A glitch observed on the out node
during clock low
Cont..
What are Glitches?
• Uncontrolled signal transitions caused by differences in signal arrival
times.
• Result in unnecessary power consumption and incorrect circuit
behavior in some cases.
• Two main types:
• Glitches in reconverging paths (Logic Hazards).
• Glitches in precharged latches.
Cont..
Glitches Due to Reconverging Paths (Figure a)
• Occurs when parallel signal paths have different delays and merge at
a gate.
• Example: XOR gate with inputs A and B having different arrival
times.
• A glitch occurs when one input changes before the other, causing an
intermediate output transition.
• Final result is correct, but an extra transition occurred.
• Effect:
• Increases power consumption due to unnecessary signal toggles.
Cont..
• This glitch gives rise to an unnecessary power consumption, which we
may express as:

• where we have expressed the glitch power in terms of the dynamic

power.
• Glitches may also be incomplete, that is the node voltage change is
less than Vdd see Figure b.
• This gives rise to a smaller power consumption than the above
expression.
Cont..
Glitch Propagation in Logic Circuits

What are Glitches?

• Uncontrolled signal transitions due to mismatched arrival times of
inputs.
• If glitch duration is long, it may propagate through multiple stages,
increasing power consumption.
• If glitch duration is short, it may be filtered out by the next logic stage.
 Cont..
Impact of Logic Depth on Glitches

• Why do glitches occur more in deep logic circuits?

• Delay variations increase with logic depth.
• Glitches in one stage may propagate to the next until a clocked element is
reached.
• Observed Power Consumption Due to Glitches:
• Vanoostende's Findings: Glitch power is 8–25% of total dynamic power (γ =
0.08–0.25).
• Figueras' Findings: For complex circuits like a 16×16 multiplier (logic depth ~30),
glitch power can be 67% of total power (γ = 0.67).
Cont..
Methods to Reduce Glitches
1. Reducing Logic Depth (Pipelining)
• Decreases delay variations but increases clock power consumption.
2. Balanced Delay Design
• Careful logic design ensures inputs arrive simultaneously, reducing
hazards.
3. Using Precharged (Domino) Logic
• After precharging, each node can switch only once.
• Downside: Precharge power dominates instead of glitch power.
4. Low-Pass Filtering in Logic Stages
• Short glitches may be naturally filtered by circuit properties.
Reduced Voltage Swing

Figure Basic circuits for reduced voltage swing.

Reduced Voltage Swing for Power Optimization
Why Reduce Voltage Swing?

• Power savings technique, especially effective for high-capacitance

nodes (e.g., buses, I/O).

• Two approaches:
• CMOS-like (no static power consumption).
• n-MOS-like (some static power consumption).
CMOS-Like Low Voltage Swing Driver

Circuit Design (Figure a)

• Components:
• T₁ and T₂ act as voltage limiters.
• Limit output voltage to V₂ - Vₜ to V₁ + Vₜ.
• Voltage Swing Reduction:
• Swing is ΔV = V₂ - Vₜ - (V₁ + Vₜ) = V₂ - V₁ - 2Vₜ.

• Advantages:
No static power dissipation.
Effective for high-capacitance nodes.
Power Consumption Calculation
n-MOS-Like Driver & Static Power Consumption
Circuit Overview (Figure b)
• Bottom transistor acts as a current generator with current I0.
• The output swing (ΔV) is controlled by:
I0R=ΔV
• Key Feature:
• Smaller voltage swing reduces dynamic power consumption.
• However, static power dissipation occurs due to continuous current flow.
• static power consumption
Cont..
• where again is related to the output.
• we may estimate the power-delay product by first estimating the
delay, td:

• Using this value of td we may estimate the power delay product:

Power Consumption in the Clocking System of a Synchronous Pipelined
circuit

• Total power consumption of the clocking system (Pck) can be expressed as:
Pck = Pckgen + Pgw + Plw + Pg + Preg
= ( 1 + 1/ k + 1/k2 + ......... + 1/kn ) . Vs 2 . f . [ Cj + Cgw + Clw + Cg ] + Preg ......... (eqn 1)
where, Pgw : Power consumption of global wiring capacitances
Plw : Power consumption of local wiring capacitances
Pg : Power consumption due to total clocked gate capacitance
Preg : Power consumption in the flip-flops,
k : Tapering factor of the clock generator (clock buffer)
Cg : Total gate capacitance of clocked transistors of the clocking system, and
Cj : junction cap. of the source-drain regions of the output node of the clock
generator
 Power Consumption in the Clocking System of
a Synchronous Pipelined circuit
• Pck = 1.11 . Vs 2 . f . [Cj + Cgw + Clw + m . Cgf ] + m . Pgf .......... (eqn 2)
where m : total number of flip-flops in the clocking system
Cgf : Total clocked gate capacitance per flip-flop
Pgf : Power consumption of one flip-flop @ frequency f

Therefore, the power consumption of the clocking system can be minimized by:
1. Reducing Cgw and Clw
E.g. Using True Single Phase clocking techniques (TSPC).
2. Reducing the number of clocked transistors per flip-flop ( Cgf term)
E.g. Using Single Transistor Clocked FF (STC).
3. Utilizing the two edges of the clock e.g. (Dual Edge Triggered FF).
4. Using minimum transistor size, and careful layout design to reduce Pgf .
 Flip-flops
[Link]: A flip-flop captures the input at a specific clock edge (rising or
falling). The output remains constant outside this clock edge.
[Link]:
[Link] Flip-Flops:
[Link]-based: Utilizes logic gates to maintain state.
[Link] Gates: Uses transmission gates to enhance performance
and reduce power consumption.
[Link] Set/Reset: Optionally includes functionality for setting
or resetting the output without relying on the clock.
Flip-flops
2. Dynamic Flip-Flops:
1.C2MOS: A compact design that allows for lower power usage and
higher speed.
[Link] TSPC: True Single-Phase Clock flip-flop that precharges to
prepare for state changes effectively.
[Link]-Precharged TSPC: Similar operation but without the precharging
phase, often used for specific timing requirements.
Latches
[Link]: A latch is transparent during one clock
phase (either when the clock is high or low), which
means the output follows the input during this time.
In the opposite phase, it holds its last state.
[Link]: Generally classified as dynamic, latches
are used to hold values with minimal power
consumption due to their simpler structure compared
to flip-flops.
 Static flip - flops
• Two types of static flip-flops, gate-based and transmission-gate
based flip-flops
• It is designed from 43-input gates and two inverters, and
therefore includes 28 transistors.
• By assuming a data activity of αa we may estimate the dynamic
power consumption of this flip-flop.
• 4 clocked inputs and I inverter, with a total of 10 transistor input
capacitances and 2 output capacitances.
• two And-Or-Inv, and two Or-And-Inv gates, each gate including 6
transistors, and an inverter.
Cont..
• There are 10 inputs driven by data signals, each with 2 transistors and
also one inverter output (with 2 connected transistors) and 4 gate
outputs, each with 6 transistors connected.

Figure (a) A static D flip-flop made from gates

Cont..
• In Figure(b) we have a positive edge-triggered static flip-flop based on
transmission gates.
• This circuit is made from 7 inverters and 4 transmission gates, that is a
total of 22 transistors.
• estimate the power consumption by noting that 12 transistor gates
are clocked, 2 inverter outputs are clocked, and 5 inverters and 4
transmission gates have a data signal on their inputs and outputs.
This gives a total power consumption of:

Figure (b) A static D flip-flop made from transmission gates.

Dynamic flip-flops

Figure - Dynamic MS D flip-flops, (a) C2MOS, (b) TSPC, (c) Non-precharged TSPC
 2
C MOS latches
• One clock signal is available from outside and that
clock buffering is included in each flip-flop.
• An edge-triggered flip-flop made from two C2MOS
latches, Figure(a). This circuit contains 12 transistors,
of which 8 are clocked at their gates and 4 at their
outputs. Further more there are 4 transistors with
data on their inputs and 8 transistors with data on
their outputs.
 Cont..
• From this we may estimate the power consumption as:

• In Figure (b) we have a precharged TSPC (true single phase

clock) flip-flop containing 11 transistors, of which 6 are
clocked on their inputs, 2 are clocked on their outputs,
there are 3 transistors with simple data on their inputs, 2
transistor gates connected to a precharged node, 2 data
nodes with 3 transistors and 1 precharged node with 3
transistors. Totally we estimate the power consumption
to:
Cont..
• An edge-triggered flip-flop from two non-precharged
TSPC latches, see Figure(c). In this case we have 14
transistors, of which 6 are clocked on their inputs, 2
are clocked on their outputs and the others have data
signals. From this we get:
Latches
•A C2MOS latch thus consists of one of the stages
from Figure(a),
•A precharged TSPC latch is made from the two last
stages in Figure(b) and a non-precharged TSPC latch
from the two first (or the two last) stages of Figure
(c).
•The power consumption of these circuits can then
be estimated as above, and a comparison between
the latches will approximately follow a comparison
of the corresponding flip-flops.
Cont..
• For the special case of precharged Cascode Voltage
Switch Logic (CVSL) logic, an RS flip-flop is a suitable
static latch, see Figure (a).
• The particular flip-flop in Figure(a) is set or reset by
low inputs. In this case the two outputs from the logic
stage are precharged high so that the flip-flop holds
its previous data.
• When the clock is made high, one of the outputs of
the logic stage will go low, thus setting or resetting the
flip-flop.
Cont..
The power consumption of this latch can be written:

Figure (a) An RS flip-flop, (b) Double edge triggered flip-flop (c) TSPC Double edge triggered flip-flop
Double-edge triggered flip-flops
• By combining two flip-flops (or latches) and one
multiplexer, it is possible to form a double-edge-
triggered device (DET), which utilizes both clock
phases for timing, see Fig. Figure (b).
• In Figure(c) we show an example of a DET flip-flop [1].
Using the same principles as above, we estimate the
power consumption of this circuit to:
Summary
• Assuming Co = Ci. We may then calculate the power consumption of
each flip-flop above in terms of fcCiVdd2, using a parameter, see Figure.

Figure: Power consumption of timing circuits

• From Figure we can conclude that the gate-based static
flip-flop (OFF) has lower power consumption than the
transmission gate flip-flop (TOFF), in spite of the fact that
it uses considerably more transistors.
• The reason is that it has fewer clocked transistors. Of
the dynamic flip-flops, the non-precharged TSPC
(NPTSPC) consumes least power, about the same power
as the GFF at very low aa and about half of the static
one at high aa’
• The RS-flip-flop latch (RSFF) appears very efficient, but
must be considered in connection with the precharged
CVSL logical gate (in this special case the latch is
indirectly clocked through the logic).
High capacitance nodes
• The high capacitance nodes occur in a number of situations such as example,
Clock networks, in clock drivers, at long busses (or) interconnections & at the
output’s.

• We need extra strong drivers to drive the high capacitance nodes, in order to
keep pace with the required speed.

• In order to reduce the power consumption in connection to large capacitance

nodes, there are two possibilities,
[Link] the activity of these nodes.
[Link] reduce the voltage swing.

• Reducing activity is an algorithm or architecture problem & it will not be treated

here,
• Voltage swing reduction ;
There are two ways of voltage swing reduction,
[Link] for large loads.
[Link] voltage swing.
• Drivers for large loads;
➢ we need to drive the large capacitance loads with responsible speed, or
with short rise & fall times.
➢ a typical example, is clock clock network, where we have quite strong
demand on slopes.
➢The standard method to drive the large loads is to use a tapered inverter
chain and is as shown in below

fig.a driver chain

• Let us study such a chain loaded by ‘Cl’ & using ‘N’ stages and a tape ring
factor of ‘f’.
f is given by fN=Y=cl/2ci
• For such a chain it can be shown that there exists an optimum value of
‘f’ for which the total delay of the chain is minimum.
• For Co=Ci this optimum will occur at f=3.5
• The delay is however a relatively flat function of ‘f’ so larger values of ‘f’
may be acceptable,
• The total switched capacitance of chain can be written as
Cdriver = 2(ci+co)(y-1)/(f-1)
• The total driver capacitance to the load capacitance is given by cdriver /cl
=((1+co)/ci)(1-1/y)/(f-1)
• This expression is the power consumption of the driver chain in terms of
the power consumption in the load.
• For large values of cl we may neglect 1/y , Let co=ci

• Using above optimum value of f=3.5 leads to power consumption of the

driver when is 80% of the power consumption in the load. this is thus
quite a large overhead.

• By instead minimizing the power delay product of the chain we will

arrive to a large of ‘f’ and therefore a lower value of excess power.

• Example : increase ‘f’ from 3.5 to 9, The power consumption over head
will be reduced from 80% to 25% of the load power at the cost of a delay
increasing of 20%
Low voltage swing:

➢An efficient way to save power is to reduce the voltage swing on high
capacitance nodes
➢Figure 3.1 b here we depict an inter connection at which we first
convert the signal to a low swing and then restore it to full swing again

Fig.b Off chip driving

 In this swing we save power in two ways

• The charge needed for charge/discharge Cl is lowered

• As the current to be delivered by the driver to charge/discharge Cl in a
certain time is lowered, the driver size is reduced so the driver itself will
consume less power
We will discuss a few examples of circuit techniques for a low voltage
swing
• One approach for swing limitation is to let the driver limit the voltage
swing.
• A straight forward method is to use an ordinary inverter with special
supply voltages.
• The special supply voltages can be generated on chip with limited power
overhead.
• As the effective drain voltages of the driver transistors are reduced to
actual swing in this case we still need the same transistor sizes for the full
swing driver.

• therefore the power consumption of the driver stage input and on the
pre-drivers will be quite large

• another approach with similar properties is in the 3.5 a

• in this case we may obtain some swing reduction also without extra
voltages

• by letting v1=0(giving a swing of vdd-2vt),v2=Vdd

• also as the drain voltage is larger than the output swing we may use
smaller transistor sizes than in the full swing case.
• on the receiving side we need to amplify the low voltage swing back
to normal again this can be accomplished by normal amplifier

• by using differential amplifier it is easier to set the switch voltage to

an appropriate value.

• it may be used for detecting differential signals directly

• a drawback is that amplifier consumes a static power.

 Differential amplifier

Ordinary inverter with special supply voltage

Energy-Recovery CMOS
•Traditional CMOS circuits dissipate energy as heat.
•Energy-recovery CMOS conserves energy for later reuse.
•No fundamental limit on power reduction in energy-recovery CMOS.

•Energy to flip a bit ≈ (1/2)CV² (fixed amount).

•Energy reduction techniques:

•Minimize number of transitions.

•Reduce capacitance (C) or voltage swing (V).

•Still limited by the (1/2)CV² constraint.

•Field-Effect Transistors (FETs) don't inherently require energy dissipation.
•Gate charge controls source-drain current without mixing channel and gate charges.

•No unavoidable energy loss from recombination.

• 1. When the FET is off, the source and drain are brought to the same
potential.
• 2. When the FET is on, the source potential can vary while the drain
floats. The variations must be sufficiently slow so that the drain
follows fairly closely, with only a small potential difference between
source and drain.
Energy Drawn From Power Supply
Energy Stored on Load Capacitor
Energy Recovery Basics
• Energy stored by placing charge on capacitive circuit nodes
• – Would like to recover that energy and return it to power supply for
use again
• – Adiabatic charging and discharging minimizes losses as charge
moved to and from power supply
• Energy recovery vs. adiabatic charging – Terms sometimes confused
in literature – Adiabatic charging refers to slow (thermodynamically
reversible) movement of charge across vanishingly small voltages for
minimal power dissipation – Energy (charge) recovery means moving
charge back and forth from a power supply or charge reservoir
Figure defines the fundamental relationships between the basic elements of
an energy-recovery computing system.
In this system, a computation consists of charging and discharging the
capacitive circuit nodes, adiabatically or otherwise.
The role of the middle component, labelled the regenerator, is all important
since it determines the ultimate efficiency of the energy-recovery process.
The regenerator is also the governor, in that it determines the length and the
shape of the transitions for the purpose of charging and discharging the logic
circuits' signal capacitances.
It serves the dual purpose of power source for energy and clock source for
timing.

Figure: Basic energy-recovery computing system

• It is possible to build regenerators through a variety of mechanisms
such as commuting the energy between electrical and magnetic
forms!, or using banks of switched capacitors to incrementally step
energy on to and off of the circuit load.
 A Simple Example
• practical energy-recovery circuit, consider the design of a clock-AND gate,
which is an AND gate with one input tied to the clock.
• Figure shows "conventional," non-adiabatic CMOS design.
• The input x is assumed to be well-behaved and only changes when the clock
signal, clk, is low. With the clock low, the output is held low by the n-channel
FET (nFET) attached to clk.
• Changes on the x input do not affect the output. When the clock swings
from low to high and the x input is high, the two p-channel FETs (pFETs)
connected in series between the output and the supply rail at voltage V, will
conduct. The capacitance C , which models the input capacitance of the logic
driven by the output of this circuit, will then charge up to V.
Figure: Clock-AND gate (a) Logic symbol (b) CMOS schematic
The work done by the power supply to do this is simply:
• conservation of energy law, the difference between Ebit and Einj must be
accounted for between the source of the top pFET and the drain of the
bottom pFET.
• Since there are no places to store energy inside the channel of the pFET, it
must therefore be dissipated in the channels of the two transistors. This
leads to the conclusion:

• For the falling clock edge, the pFET path will stop conducting and the out
put capacitance will be discharged through the nFET connected to clk.
• The energy stored on the capacitor changes from Ebit to 0. Similar to
the argument for the pFET, this energy must be dissipated in the nFET.
The energy returned to the power supply is Ertn = Q ·0 = 0. The
energy dissipated per cycle is:

• When the upper two pFETs are on, they form a resistance, R, between
the power-supply rail at voltage V and the output capacitance. With
this configuration, current as a function of time is:
• From resistance and the current, the instantaneous power dissipation
in the resistance is:

• The energy dissipation is the integral of power from 0 to T

• considered is where the regenerator continuously varies the input
voltage V so that current remains constant throughout the entire
charge/discharge process, i.e.,
 Reversible Pipelines
• Practical circuit example of the postponement principle is a shift register.
• The timing for the shift register and its structure can then be generalized
to implement reversible pipelines.
• Figure.1 depicts a block diagram and T-gate circuit for a shift register.
Each of the shift register's cells is composed of two T-gates: one for the
logic circuit and the other for the return circuit.
• The logic-circuits inputs are from the previous stage and the return-circuit
inputs from the successor stage. The overlapping power-clocks establish
three distinct intervals for each data bit: set, hold, and reset.
• The set interval occurs when the power-clock transitions from low to
high while the previous-stage inputs are stable.
• The hold interval occurs while the power-clock signal is high.
• During hold, the output serves two pur poses: to reset the previous
stage when the power-clock signal for the previous stage goes low
and to set the successor stage when the power-clock signal for the
successor stage goes high.
• After the hold interval, the stage is reset when the power-clock goes
low while the successor-stage inputs are stable.
Figure:1. A 4-stage, shift-register cell built from T-gates
Reversible Pipelines
• One way to visualize these general-purpose systems is diagrammed in
Figure.2.
• The lines between the adjacent stages are in fact bundles of data
wires.
• As long as combinational logic is included along the return path that
can undo what was done along the forward path, e.g., computing the
inverse function of the forward logic, the situation is the same as that
of the shift register.
 Reversible Pipelines

Figure.2: Reversible pipeline using the shift register approach

• There is an important complication though, which will increase the

number of power-clocks and possibly the number of signal rails per bit for
pipelines more sophisticated than the shift register.
• Each signal in the shift register goes through the events of set, hold, and
reset.
• Before set and after reset, an output signal is either undefined or held
at a valid logic level called idle.
• The problem can be solved by adding "guard" T-gates [3] (Figure 3)
and more power-clocks to control the guard T-gates.
• These additional power-clocks can be exploited to drive other
pipeline stages.

Figure:3 The reversible logic cell with guard T-gates

High-Performance Approaches
• Dual Vt
• Variable Threshold
 Bangalore Institute of Technology
(Affiliated to Visvesvaraya Technological University – VTU)
K. R. Road, V.V. Pura, Bengaluru – 560 004, India.

Dept. of Electronics Engineering (VLSI Design and Technology)

BVL613A-Low Power VLSI

Design
Module -2
Dr Jalaja S
Associate Professor/EE (VDT)
Associate Dean, BIT
 Switching Power Dissipation
• There exists capacitive load at the output of each gate.
• The exact value of capacitance depends on the fan-out of the
gate, output capacitance, and wiring capacitances and all
these parameters depend on the technology generation in use.
• As the output changes from a low to high level and high to
low level, the load capacitor charges and discharges causing
power dissipation.
• This component of power dissipation is known as switching
power dissipation.
 Switching Power Dissipation
Dynamic Power
Dissipation
Model

❖ For some input combinations, the pMOS network is ON and nMOS network is
OFF.
❖ In this state, the capacitor is charged to Vdd by drawing power from the supply.
❖ For some other input combinations, the nMOS network is ON and pMOS
network is OFF,
❖ In this state, the capacitor discharges through the nMOS network.
❖ For simplicity, let us assume that the CMOS gate is an inverter.
 Switching Power Dissipation
Dynamic Power Dissipation
Model

During the transition of

the output from 0 to
Vdd, the energy drawn
from the power supply is
given by

where i( t) is an instantaneous current drawn from the supply voltage

Vdd, and it can
be expressed as
 Switching Power Dissipation
Dynamic Power
Dissipation
Model

Regardless of the waveform and time taken to charge the

capacitor, C L Vdd 2 is the energy drawn from the power supply
for 0 to Vdd transition at the load capacitance.
 Switching Power Dissipation

❖ The switching power is proportional to the switching frequency and

independent of device parameters.
❖ As the switching power is proportional to the square of the supply
voltage, there is a strong dependence of switching power on the
supply voltage.
❖ Switching power reduces by 56 %, if the supply voltage is reduced from
5 to 3.3 V, and if the supply voltage is lowered to 1 V, the switching
power is reduced by 96 % compared to that of 5V.
❖ This is the reason why voltage scaling is considered to be the most
dominant approach to reduce switching power.
Switching Power Dissipation
• Dynamic Power for a Complex Gate
• Reduced Voltage Swing
• Internal Node Power
• Switching Activity
• Switching Activity of Static CMOS Gates
• Inputs Not Equiprobable
• Mutually Dependent Inputs
• Transition Probability in Dynamic Gates
• Power Dissipation due to Charge Sharing
 Switching Power Dissipation

• Dynamic Power for a Complex Gate

❖ For an inverter having a load capacitance CL, the dynamic
power expression is C L Vdd2 f.
❖ Here, it is assumed that the output switches from rail to rail and input
switching occurs for every clock.
❖ This simple assumption does not hold good for complex gates because
of several reasons.
❖ First, apart from the output load capacitance, there exist capacitances
at other nodes of the gate.
 Switching Power Dissipation
• Dynamic Power for a Complex Gate
➢ As these internal nodes also charge and discharge,
dynamic power dissipation will take place on the internal nodes.
➢ This leads to two components of dynamic power
dissipation-load power and internal node power.
➢ Second, at different nodes of a gate, the voltage swing may
not be from rail to rail.
➢ This reduced voltage swing has to be taken into
consideration for estimating the dynamic power.
 Switching Power Dissipation
• Dynamic Power for a Complex Gate
❖ Finally, to take into account the condition when the
capacitive node of a gate might not switch when the clock is
switching, a concept known as switching activity is
introduced.
Switching activity determines how often switching occurs
on a capacitive node.
❖ These three issues are considered in the following
subsections.
 Switching Power Dissipation
• Reduced Voltage Swing

➢ There are situations where a rail-to-rail swing does not

take place on a capacitive node.
➢ This situation arises in pass transistor logic and when
the pull-up device is an enhancement-type nMOS transistor
in nMOS logic gates
➢In such cases, the output can only rise to Vdd − Vt.
➢ This situation also happens in interval nodes of CMOS
gates.
 Switching Power Dissipation

• Internal Node Power

Switching nodes of a three-input NAND gate

➢ Apart from the output capacitance

CL, two capacitances C1 and C2 are
shown in two interval nodes of the
gate.
➢ For input combination 110, the
output is “1” and transistors Q3, Q4,
and Q5 are ON.
 Switching Power Dissipation
• Internal Node Power
Switching nodes of a three-input NAND gate

➢ All the capacitors will draw energy from the

supply.
➢ Capacitor CL will charge to Vdd through Q3,
capacitor C1 will charge to ( Vdd − Vt)
through Q3 and Q4.
➢ Capacitor C2 will also charge to ( Vdd − Vt)
through Q3, Q4, and Q5.
➢ For each 0-to-Vdd transition at an internal
node, the energy drawn is given by

Where Ci is the internal node capacitance and Vi is internal

voltage swing at node i.
 Switching Power Dissipation
• Switching Activity
➢ For a complex logic gate, the switching activity depends on
two factors—the topology of the gate and the statistical
timing behavior of the circuit.
➢ To handle the transition rate variation statistically, let n( N)
be the number of 0-to-Vdd output transitions in the time
interval [0,N].
➢ Total energy EN drawn from the power supply for this
interval is given by
 Switching Power Dissipation
• Switching Activity

➢ Where α0 is the switching activity at the output node, αi is the switching activity
on the ith internal node, and f is the clock frequency.
➢Here, it is assumed that there are k internal nodes.
 Switching Power Dissipation
• Switching Activity of Static CMOS Gates
➢ The switching activity at the output of a static CMOS gate depends
strongly on the function it realizes.
➢ It is assumed that the inputs are independent to each other and
the probability of occurrence of “0” and “1” is same, let P0 be the
probability that the output will be “0” and P1 is the probability
that the output will be “1.” Then,
 Switching Power Dissipation
• Switching Activity of Static CMOS Gates

➢ For an n-input gate, the total number of input combinations is 2n.

➢ Out of 2n combinations in the truth table, let n0 be the total
number of combinations for which the output is 0 and n1 is the total
number of combinations for which the output is “1,” then
 Switching Power Dissipation
• Switching Activity of Static CMOS Gates
➢ For an n-input gate, the total number of input combinations is 2n.
➢ Out of 2n combinations in the truth table, let n0 be the total
number of combinations for which the output is 0 and n1 is the
total number of combinations for which the output is “1,” then
 Switching Power Dissipation
• Switching Activity of Static CMOS Gates
➢ The variation of the switching activity at the output of NAND, NOR,
and EX-OR gates with the increase in the number of inputs is shown
in Fig.
Variation of
switching
activity with
increase in
the number
of inputs
 Switching Power Dissipation
• Inputs Not Equiprobable
➢ we have assumed that the inputs are independent of each
other and equiprobable.
➢ But, inputs might not be equiprobable.
➢ In such cases, the probability of transitions at the output
depends on the probability of transitions at the primary
inputs.
 Switching Power Dissipation
• Inputs Not Equiprobable
➢ Let us consider a two-input NAND gate with two inputs A and B having
mutually independent signal probabilities of PA and PB.
➢ The probability of logical “0” at the output is P0 = PAPB and the
probability of “1” at the output is P1 = (1− P0 ) = (1− PAPB ) .
 Switching Power Dissipation
Mutually Dependent Inputs

• When a multilevel network of complex gates are considered, the

inputs to a gate at a particular stage might not be independent.
• This can happen because the signal from one input may propagate through multiple
paths and again recombine at a particular stage.
• This problem of re-convergent fan-out is shown with the help of a
simple example given in Fig. 6.12.
 Switching Power Dissipation
• Mutually Dependent Inputs ➢ Provides details of
various gates used for
the realization of the
three implementations.
➢ The table provides the
area in terns of unit area
called cell grid, output
and input capacitances,
and delay in terms of
output capacitance C0 in
picofarad.
➢ For all transistors, Wp =
2Wn = 10 μm.
 Switching Power Dissipation
Transition Probability in Dynamic Gates
➢ The logic style has a strong influence on the node
transition probability.
➢ For static CMOS, we calculated the transition probability as
P0 P1= P0(1- P0 ).
➢ In the case of dynamic gates, the situation is different.
➢ As we have seen, in the case of domino or NORA logic
styles, the output nodes are pre-charged to a high level in
the Pre-charge phase and then are discharged in the
evaluation phase, depending on the outcome of
evaluation.
 Switching Power Dissipation
• Transition Probability in Dynamic Gates
• In other words, the output transition probability will
depend on the signal probability P0, i.e.,

• where P0 is the probability for the output is in the zero

state. For n independent inputs to a gate

• where N0 is the number of zero entries in the truth table

 Switching Power Dissipation
• Power Dissipation due to Charge Sharing
➢ Moreover, in the case of dynamic gates, power dissipation takes
place due to the phenomenon of charge sharing even when
the output is not 0 at the time evaluation, i.e., the output
load capacitance is not discharged, but part of the chargeof
the load capacitance might get redistributed leading to a reduction
in the output voltage level.
➢ In the next pre-charge period, the output is again pre-charged
back to Vdd.
 Short-Circuit Power Dissipation
Short-circuit power dissipation during
input transition

➢ When there are finite rise and fall times at the input of CMOS logic
gates, both pMOS and nMOS transistors are simultaneously ON for a
certain duration, shorting the power supply line to ground.
➢ This leads to current flow from supply to ground.
➢ Short-circuit power dissipation takes place for input voltage in the
range Vtn < Vin < Vdd − | Vtp |, when both pMOS and nMOS
transistors turn ON creating a conducting path between Vdd and
ground (GND).
 Short-Circuit Power Dissipation

Because of the symmetry, we may write

As the nMOS transistor is operating in the saturation region,
 Short-Circuit Power Dissipation

Variation of short-circuit current with load capacitance

Short-circuit current as a function of input rise/fall time

Short-Circuit Power Dissipation
 Glitching Power Dissipation

• In the power calculations so far, we have assumed that

the gates have zero delay.
• In practice, the gates will have finite delay and this delay will
lead to spurious undesirable transitions at the output.
• These spurious signals are known as glitches.
• In the case of a static CMOS circuit, the output node or
internal nodes can make undesirable transitions before
attaining a stable value.
 Glitching Power Dissipation
• If the inputs ABC change value from 101 to 000, ideally for zero gate delay the
output should remain at the 0 logic level.
• However, considering unit gate delay of the first gate stage, output O1 is delayed
compared to the C input
 Glitching Power Dissipation
➢ As a consequence, the output switches to 1 logic level for
one gate delay duration.
➢ This transition increases the dynamic power dissipation
and this component of dynamic power is known as
glitching power.
 Glitching Power Dissipation
• Glitching power may constitute a significant portion of
dynamic power, if circuits are not properly designed.
 Glitching Power Dissipation
• Usually, cascaded circuits as shown in Fig. a exhibit high glitching power.
• The glitching power can be minimized by realizing a circuit by balancing delays,
as shown in Fig. b.
• On highly loaded nodes, buffers can be inserted to balance delays and
cascaded implementation can be avoided, if possible, to minimize
glitching power.
Components of Leakage Power Dissipation

• When the circuit is not in an

active mode of operation,
there is static power
dissipation due to various
leakage mechanisms.
• In deep-submicron devices,
these leakage currents are
becoming a significant
contributor to power
dissipation of CMOS circuits.
Components Leakage Power Dissipation
• I1 is the reverse- bias p–n junction
diode leakage current;
• I2 is the reverse-biased p–n
junction current due to tunneling
of electrons from the valence
bond of the p region to the
conduction bond of the n region;
• I3 is the sub-threshold leakage
current between the source and
the drain when the gate voltage is
less than the threshold voltage Vt;
Components Leakage Power Dissipation
• I4 is the oxide-tunneling
current due to a reduction in
the oxide thickness;
• I5 is gate current due to hot-
carrier injection of elections;
• I6 is the GIDL current due to a
high field effect in the drain
junction; and I7 is the channel
punch-through current due to
the close proximity of the drain Fig. Summary of leakage current
and the source in short-channel mechanisms of deep-submicrometer
transistors.
devices.
TRANSISTOR LEAKAGE MECHANISMS
• pn Junction Reverse-Bias Current
• Band-to-Band Tunneling Current
• Subthreshold Leakage
• Tunneling into and Through Gate Oxide
 p–n Junction Reverse-Biased Current
nMOS Inverter and
its Physical
Structure

❖ Let us consider the physical structure of a CMOS inverter shown in

Fig.
❖ As shown in the figure, source–drain diffusions
and n-well diffusions form parasitic diodes in the bulk of silicon
substrate.
❖ As parasitic diodes are reverse-biased, their leakage currents
contribute to static power dissipation.
 p–n Junction Reverse-Biased Current
nMOS Inverter and its
Physical
Structure

The current for one diode is given by

where Js is the reverse saturation current density (this increases with

temperature),Is is the AJs, Vd is the diode voltage, n is the emission coefficient
of the diode (sometimes equal to 1), q is the charge of an electron (1.602 ×
10−19), K is the Boltzmann constant (1.38 × 10−23 j/k), T is the temperature in K,
VT =KT/q is known as the thermal voltage. At room temperature, VT =26 mV
 Band-to-Band Tunneling Current
BTBT in reverse
biased p–n
junction

✓ When both n regions and p regions are heavily doped, a high

electric field across a reverse biased p–n junction causes a significant
current to flow through the junction due to tunneling of electrons
from the valence band of the p region to the conduction band of n
region.
✓ This is illustrated in Fig. It is evident from this diagram that for
the voltage drop across that junction should be more than the
band gap.
 Band-to-Band Tunneling Current
BTBT in reverse biased p–n
junction

The tunneling current density is given by

where m* is the effective mass of electron, E is the elective field at

the junction, q is the electronic charge, and h is the reduced
Planck’s constant (1/2π times).
 Subthreshold Leakage Current
• The subthreshold leakage current in CMOS circuits is
due to carrier diffusion between the source and the
drain regions of the transistor in weak inversion,
when the gate voltage is below Vt.
 Subthreshold Leakage Current
• The behavior of an MOS transistor in the
subthreshold operating region is similar to a bipolar
device, and the subthreshold current exhibits an
exponential dependence on the gate voltage.
• The amount of the subthreshold current may
become significant when the gate-to-source voltage
is smaller than, but very close to, the threshold
voltage of the device.
Sub-threshold Leakage Current
• The sub-threshold current expression as given by the
BSIM3 model is stated below: Where m is the sub-
threshold swing
coefficient,
VT = KT/q is the
thermal voltage,
μ0 is the zero bias
mobility,
cox is the gate oxide
capacitance per unit
area,
wdm is the maximum
The typical value of this current for depletion layer width,
and tox is the gate
a single transistor is 1–10 nA. oxide thickness.
 Sub-threshold Leakage Current
Various mechanisms which affect the Sub-threshold
leakage current are:
• Drain-induced barrier lowering (DIBL)
• Body effect
• Narrow-width effect
• Effect of channel length and Vth roll-off
• Effect of temperature
 Drain-induced barrier lowering (DIBL)w
• For long-channel devices, the sources and drain region are
separated far apart and the depletion regions around the drain
and source have little effect on the potential distribution in the
channel region.
• So, the threshold voltage is independent of the channel length
and drain bias for such devices.
• However, for short-channel devices, the source and drain depletion
width in the vertical direction and the source drain potential have
a strong effect on a significant portion of the device leading to
variation of the subthreshold leakage current with the drain bias.
This is known as the DIBL effect.
 Drain-induced barrier lowering (DIBL)
• Because of the DIBL effect, the barrier height of a
short-channel device reduces with an increase in
the subthreshold current due to a lower
threshold voltage.
• DIBL occurs when the depletion regions of the
drain and the source interact with each other
near the channel surface to lower the source
potential barrier.
 Body Effect
• As a negative voltage is applied to the
substrate with respect to the source, the well-
to-source junction, the device is reverse-
biased and bulk depletion region is widened.
• This leads to an increase in the threshold
voltage. This effect is known as the body
effect.
 Body Effect
• The threshold voltage equation given below
gives the relationship of the threshold voltage
with the body bias

Where Vfb is the flat-band voltage, Na is the doping density in

the substrate,

is the difference between the Fermi potential and

the intrinsic potential in the substrate.
 Body Effect
• The variation of the threshold voltage with
respect to the substrate bias dVth/dVbs is
referred to as the substrate sensitivity:

Substrate sensitivity is higher for higher bulk doping concentration,

and it decreases as the substrate reverse bias increases.
At Vbs = 0, it is equal to Cdm/Cox or m − 1 where m is also called
the body effect coefficient.
 Narrow-Width Effect
• The width of a gate,
particularly when it
becomes narrow,
affects the threshold
voltage as shown in
Fig.
• The reduction in
threshold voltage also
leads to an increase in
the subthreshold
leakage current Fig.
 Vth Roll-Off
• As the channel length is reduced, the
threshold voltage of metal–oxide–
semiconductor field-effect transistor
(MOSFET) decreases.
• This reduction of channel length is known as
Vth roll-off.
 Vth Roll-Off
• Figure shows the
reduction of threshold
voltage with a
reduction in channel
length.
• This effect is caused
by the proximity of
the source and drain
regions leading to a
2D field pattern rather
than a 1D field pattern
in short-channel
devices.
 Vth Roll-Off
• The bulk change that needs
to be inverted by the
application of gate voltage is
proportional to the area
under the trapezoidal
region, shown in Fig,
given by QB‘ Wdm( L + L) / 2 .
 Temperature Effect
• For a 0.3-μm
technology, St varies
from 58.2 to 81.9
mV/decade.
• As the temperature
varies from − 50 to +
25 °C in the 0.3-μm
technology as shown
in Fig. 6.28, the IOFF
increases from 0.45 to
100 pA, an increase by
a factor of 356, for a
20-μm-wide device
(23 fA/μm to 8
pA/μm)..
 Tunneling Through Gate Oxide
• Device size scaling leads to a reduction in oxide
thickness, which in turn results in an increase in
the field across the oxide.
• The high electric field along with low oxide
thickness leads to the tunneling of electrons from
the substrate to the gate and vice versa, through
the gate.
• The basic phenomenon of tunneling is explained
with the help of a heavily doped n + type poly-
silicon gate and a p-type substrate.
 Tunneling Through Gate Oxide
• Because of higher
mobility, primarily
electrons take part in the
tunneling process.
• An energy band diagram
in flat-band condition is
shown in Fig a.,
where Φ is the Si–SiO2
interface barrier height
for electrons.
 Tunneling Through Gate Oxide
• The energy band diagram
• changes to that of Fig.
b, when a positive bias
is applied to the gate.
• The electrons at the
strongly inverted surface
can tunnel through the
SiO2 because of the small
width of the potential
barrier arising out of
small oxide thickness.
 Tunneling Through Gate Oxide
• Similarly, if a negative gate
bias is applied, the
electrons from the n +
poly-silicon can tunnel
through the oxide layer as
shown in Fig. c.
• This results in gate oxide-
tunneling current, which
violates the classical
infinite input impedance
assumption of MOS
transistors and thus affects
the circuit performance
significantly.
 Hot-Carrier Injection
• Electrons and holes
near the Si–SiO2
interface can gain
sufficient energy due
to the high electric
field in short-channel
MOSFETs and cross
the interface
potential barrier and
enter into the oxide
layer as shown in Fig.
 Hot-Carrier Injection
• This phenomenon is
known as the hot-
carrier injection.
Because of the lower
effective mass and
smaller barrier height
(3.1 eV) for electrons
compared to holes (4.5
eV), the possibility of
an injection due to
electrons is more than
the holes.
 Gate-Induced Drain Leakage
• Due to a high electric field ( Vdg) across the
oxide, a deep depletion region under the drain
overlap region is created, which generates
electrons and holes by band-to band
tunneling.
• The resulting drain to body current is called
GIDL current.
 Gate-Induced Drain Leakage
• When the negative
gate bias is large
( v, gate at zero or
negative voltages
with respect to
drain at Vdd), the n
+ region under the
gate can be
depleted and even
inverted as shown
in Fig.
 Gate-Induced Drain Leakage
• As a consequence,
minority carriers are
emitted in the drain
region underneath the gate.
• As the substrate is at a lower
potential, the minority
carriers at the drain
depletion region are swept
away laterally to the
substrate, creating a GIDL
current.
 Gate-Induced Drain Leakage
• At low drain doping, the electric
field is not high enough to
cause tunneling.
• At very high drain doping,
the depletion width and
hence the tunneling is limited.
• The GIDL is worse for
moderated doping, when
the depletion width and
electric field are both
considerable.
 Punch-Through
• Due to the proximity of the drain and the source
in short-channel devices, the depletion regions at
the source–substrate and drain–substrate
junctions extend into the channel.
• If the doping is kept constant while the channel
length is reduced, the separation between the
depletion region boundaries decreases.
• Increased reverse bias (higher Vds) across the
junction further decreases the separation.
 Punch-Through
• When the depletion region merge, a majority
of the carriers in the source enter into the
substrate and get collected by the drain.
• This situation is known as punch-through
condition.
• The net effect of punch through is an increase
in the subthreshold current.
• Moreover, punch through degrades the
subthreshold slope.
 Punch-Through
• The punch-through voltage VPT estimates the
value of Vds for which punch through occurs at
Vgs = 0:

where NB is the doping concentration at the bulk, L is

the channel length, and Wj is the junction width.
Principles of Low-Power Design
Fundamental Limits
Fundamental Limits
Material Limits
Material Limits
System Limits