Bangalore Institute of Technology, Bangalore

BVL613A-Low Power VLSI

Design
Dr Jalaja S
Associate Professor/EE (VDT)
Module 3: Low Power Circuit Techniques
• Introduction
• Power Consumption in Circuits
• Flip-flops and Latches
• High Capacitance Nodes
• Energy Recovery
• Reversible Pipelines
• High-Performance Approaches ....
Inverter Capacitance Analysis & Dynamic Power Consumption

1. Inverter Capacitance Components

In a CMOS inverter, capacitance arises from multiple sources:
[Link] Capacitances:
1. Gate Capacitance (Cgs,Cgd​):Capacitance between the gate and source/drain
due to the thin oxide layer.
2. Overlap Capacitance (Cov): Due to the gate extending over the source/drain
diffusion regions.
3. Drain-Bulk and Source-Bulk Junction Capacitance (Cdb​,Csb​): Reverse-biased
pn-junction capacitance.
Cont..
Parasitic Capacitances:
• Wiring Capacitance (iC wring): Capacitance due to interconnects.
• Load Capacitance (CL): External capacitance due to fan-out (next-
stage gates).
Total Effective Load Capacitance:
• Ceff=Cint+CL
• where Cint is the internal capacitance of the inverter, and
CL​ is the load capacitance.
Dynamic Power Consumption
Dynamic power in a CMOS inverter is consumed primarily due to charging
and discharging of capacitive loads.
Formula for Dynamic Power

where:
• α = Activity factor (probability of switching per clock cycle, typically 0.5 for
balanced signals),
• CL​ = Load capacitance,
• Vdd​ = Supply voltage,
• f = Clock frequency.
Power Consumption Breakdown
Charging Phase:
• When input transitions from LOW to HIGH, the PMOS charges the load
capacitor.
• Energy drawn from the supply:
•Discharging Phase:
•When input transitions from HIGH to LOW, the NMOS discharges CL to
ground.

•Energy stored in CL is dissipated as heat in the NMOS transistor.

•Total Energy per Cycle:
•The energy per transition is:
Reducing Dynamic Power
[Link] Vdd: Since power scales as Vdd2​, reducing the supply voltage
significantly decreases dynamic power.
[Link] Capacitance (CL​): Optimizing transistor sizing, reducing
interconnect capacitance, and using advanced low-capacitance
materials.
[Link] Switching Activity (α): Implementing clock gating and
power gating techniques to minimize unnecessary transitions.
[Link] Frequency (f): Reducing clock frequency helps limit power
consumption but may impact performance.
Dynamic power consumption
• Capacitance on node f (output):
• Junction cap Cdb,p and Cdb,n
• Gate capacitance Cgd,p and Cgd,n
• Interconnect cap
• Receiver gate cap
CMOS Inverter Gate Capacitances
• Gate capacitances CGD,p and CGD,n:
• Just after the input switches(t = 0+), what regions are transistors in?
• One is in cutoff: CGD = Overlap Cap
• One is in Saturation: CGD = Overlap Cap
• Therefore, gate-to-drain capacitance is due to overlap capacitance :

• However, also need to consider Miller effect

CMOS Inverter Capacitances: Miller Effect
CMOS Inverter Capacitances: Receiver
Inverter Capacitances: Analysis
Dynamic Power Consumption in CMOS Inverter
Dynamic Power Consumption in CMOS Inverter
Dynamic Power Consumption in CMOS Inverter
Dynamic Power Consumption in CMOS Inverter

• The general formula for dynamic power consumption in CMOS

circuits can be expressed as:
 Switching Probabilities

Figure (a) Inverter Capacitances, (b) The Load Capacitance and (c) the Miller Capacitance
Switching Probability and Dynamic Power Consumption
Switching Probability and Dynamic Power Consumption
Switching Probability and Dynamic Power
Consumption
Effective Capacitances

• Figure (a). Capacitances in a MOSFET (b) A CMOS Gate, (c). A

Transmission Gate.
Effective Capacitances
 Cont..
• In Figure b we show a simple static CMOS gate.
• sum all capacitances which are related to the parallel transistor combination (the
p-transistors in Figure b), in the same way as the inverter transistors.
• For the series combination we have two nodes with capacitance, CN1 and CN2.
CNl includes CD of T2 and Cs of T 1 and a Miller capacitance of CGs+CG of Tl and
CGD of T2.
• It is either charged to Vdd-VT (if T1 is conducting and T2 nonconducting when the
p-net is conducting) or not charged at all (if T1 is open when the p-net is
conducting).
• Instead of dealing with this rather complicated model in the following, we will
simplify our model by estimating the extra charge introduced by each series
transistor to be the same as introduced by an extra parallel transistor. We thus
add CD+2CGD from T2 to CN2 and let this be the effective capacitance CL.
• estimate the effective output capacitance of a gate
Cont..

• n is the total number of transistors in the stage and m is the total

number of load transistors.
• If transistors are different in sizes or have different capacitances of other
reasons, the formula will be changed into a sum over all transistors
involved.
• Co and Cj represents effective transistor output and input capacitances
respectively.
Cont..

• For a transmission gate, Figure c, This stage does not amplify the
signal, therefore it do not have a Miller effect.
• For this gate the "input" capacitance on the transistor gates are
CTi = CG + CGS + CGD each and the "output" capacitance at each
source/drains of the transmission gate is CTo = CD + CDS’
however use CTi = Ci and CTo = Co for simplicity.
Short-circuit Power Consumption
•Short-Circuit Current in CMOS Gates
•When an input signal has a nonzero rise or fall time (τ), both nMOS
and pMOS transistors momentarily conduct.
•This leads to a short-circuit current that flows directly from Vdd to
ground, without contributing to charging/discharging the load
capacitance (CL).

•Short-Circuit Power Consumption (Psc)

•A simple static model provides an estimation for Psc.
•A more accurate dynamic model suggests that the static estimation
may overestimate Psc by a factor of three.
 Cont..
Impact of Node Activity
• The probability of a transition occurring is related to the node’s activity:
• For clocked nodes: 1/T=2fe
• For logic signals: 1/T=uafe​ (where ua​ is the activity factor, and fe​ is the operating
frequency).
Practical Implications
• Psc is usually less than 10% of dynamic power (Pd) in well-designed
circuits.
• However, Psc becomes significant when input signals transition slowly
(i.e., large τ).
• This highlights the importance of keeping signal transitions sharp to
minimize short-circuit power dissipation.
Static Power Consumption

Figure (a). A pseudo-nMOS inverter, (b). A precharged inverter

Cont..
•Static power consumption in CMOS circuits arises due to leakage currents in
transistors and pn-junctions.
•Inverter Model: (Refer to Figure a)
•Low Input: Leakage current of the nMOS transistor (IdOn​).
•High Input: Leakage current of the pMOS transistor (IdOp​).

•Assuming equal probability of logic levels , the average static power

consumption simplifies accordingly.
Cont..
• Let us take the pseudo-nMOS inverter in Figure a
• p-transistor behaves as a current generator with current I0, and it is
sized in such a way that its current is much lower than the maximum
current of a conducting n-transistor.
• For a low input, only the p-transistor is conducting, so the output is
high.
• For a high input the n-transistor is conducting, making the output low.
• The low output voltage is here larger than zero, as the p-transistor
current, I0, passes through the n-transistor, giving rise to a voltage
drop of about

• The static power consumption is here given by:

Cont..
• where refers to the output signal.
• Thus, assuming I0, to be much less than the current capability of the
n-transistor means that the speed is given by the rise time, which is

• The so called power-delay product. Ptd. can then be estimated to:

Precharged Circuits
What is Precharging?
• A technique used in dynamic CMOS circuits to save transistors and
increase speed.
• Key Concept:
• The circuit precharges the output to a known state before evaluation.

Example: Precharged Inverter (Figure b)

• Two Phases:
• Precharge Phase (Clock = Low):
• A pMOS transistor charges the output to HIGH.
• Evaluation Phase (Clock = High):
• The output is determined by the input.
• If the input is HIGH, the nMOS pulls the output LOW.
Cont..
• The dynamic power consumption of this stage can be expressed as:
Glitches

• Figure (a) A CMOS XOR gate (b) A glitch observed on the out node
during clock low
Cont..
What are Glitches?
• Uncontrolled signal transitions caused by differences in signal arrival
times.
• Result in unnecessary power consumption and incorrect circuit
behavior in some cases.
• Two main types:
• Glitches in reconverging paths (Logic Hazards).
• Glitches in precharged latches.
Cont..
Glitches Due to Reconverging Paths (Figure a)
• Occurs when parallel signal paths have different delays and merge at
a gate.
• Example: XOR gate with inputs A and B having different arrival
times.
• A glitch occurs when one input changes before the other, causing an
intermediate output transition.
• Final result is correct, but an extra transition occurred.
• Effect:
• Increases power consumption due to unnecessary signal toggles.
Cont..
• This glitch gives rise to an unnecessary power consumption, which we
may express as:

• where we have expressed the glitch power in terms of the dynamic

power.
• Glitches may also be incomplete, that is the node voltage change is
less than Vdd see Figure b.
• This gives rise to a smaller power consumption than the above
expression.
Cont..
Glitch Propagation in Logic Circuits

What are Glitches?

• Uncontrolled signal transitions due to mismatched arrival times of
inputs.
• If glitch duration is long, it may propagate through multiple stages,
increasing power consumption.
• If glitch duration is short, it may be filtered out by the next logic stage.
 Cont..
Impact of Logic Depth on Glitches

• Why do glitches occur more in deep logic circuits?

• Delay variations increase with logic depth.
• Glitches in one stage may propagate to the next until a clocked element is
reached.
• Observed Power Consumption Due to Glitches:
• Vanoostende's Findings: Glitch power is 8–25% of total dynamic power (γ =
0.08–0.25).
• Figueras' Findings: For complex circuits like a 16×16 multiplier (logic depth ~30),
glitch power can be 67% of total power (γ = 0.67).
Cont..
Methods to Reduce Glitches
1. Reducing Logic Depth (Pipelining)
• Decreases delay variations but increases clock power consumption.
2. Balanced Delay Design
• Careful logic design ensures inputs arrive simultaneously, reducing
hazards.
3. Using Precharged (Domino) Logic
• After precharging, each node can switch only once.
• Downside: Precharge power dominates instead of glitch power.
4. Low-Pass Filtering in Logic Stages
• Short glitches may be naturally filtered by circuit properties.