Module-3

Basic Circuit Concepts: Sheet Resistance, Sheet resistance concept applied

to MOS transistors and inverters, Area Capacitances of Layers, Standard
Unit of Capacitance, Some Area Capacitance Calculations, Delay Unit,
Inverter Delays, Driving Large Capacitive Loads, Propagation Delays.

Scaling of MOS Circuits: Scaling Models & Scaling Factors for Device
Parameters.
 Introduction
• The 'wiring-up' of circuits takes place through the various
conductive layers which are produced by the MOS
processing and it is therefore necessary to be aware of
the resistive and capacitive characteristics of each layer.
• Concepts such as sheet resistance Rs and a standard unit
of capacitance Cg, help greatly in evaluating the effects of
wiring and input and output capacitances.
• The delays associated with wiring, with inverters and
with other circuitry may be conveniently evaluated in
terms of a delay unit

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SHEET RESISTANCE Rs

Consider a uniform slab of conducting material of resistivity p,

of width W, thickness t, and length between faces L.

where A = cross-section area= t* W

If L=W then
RS = ohm per square or sheet resistance
Rs is completely independent of the area of the square
EX: A 1 µm per side square slab of material has exactly the same
resistance as a 1cm per side square slab of the same material if the
thickness is the same.
Thus the actual values associated with the layers in a MOS circuit
depend on the thickness of the layer and the resistivity of the material
forming the layer.
For the metal and polysilicon layers, the thickness of a layer is easily
envisaged, and the resistivity of the material is known.
For the diffusion layer, the depth of the diffusion regions -contributes
toward the effective thickness while the impurity concentration (or
doping level) profile determines the resistivity.
 SHEET RESISTANCE CONCEPT APPLIED TO MOS
TRANSISTORS AND INVERTERS
• The thinox mask layout is the union of
diffusion and channel regions and these
regions have differing hatching patterns to
stress the fact that the polysilicon and
underlying silicon dioxide mask the substrate
so that diffusion ,takes place only in the areas
defined by the thinox mask which do not
coincide with the polysilicon mask.
• The simple n-type pass transistor of Figure has
a channel length L = 2λ. and a channel width W
= 2λ. The channel is, therefore, square and
channel resistance (with or without implant)
• The length to width ratio, denoted Z, is 1:1 in this case.

• If channel length L = 8λ. and width W = 2λ, then channel

resistance is

• The channel is regarded as four 2 λ x 2 λ squares in series

giving a resistance of 4RS. This particular way of
approaching the calculation of resistance is often useful,
particularly when dealing with shapes which are not simple
rectangles.
• The pull-up to pull-down ratio of an inverter is determined as follows:
In the nMOS case a simple 4: I Zp.u. :Zp.d. ratio obviously applies. Note, for
example, that a 4: 1 ratio would also be achieved if the upper channel(p.u.)
length L = 4 λ., and width W = 2 λ. with lower channel (p.d.) length L = 2 λ,
and width W = 4 λ.
Silicides
• As the line width becomes smaller, the sheet resistance contribution to RC
delay increases.
• With polysilicon sheet resistance ranging from 15 to 100 ohm it is apparent
that some of the advantages of scaling could be offset by the interconnect
resistance at the gate level.
• The low sheet resistances of refractory silicides (2-4 ohm), which are
formed by depositing metal on polysilicon and then sintering, have been
investigated as an interconnecting medium. Deposition of the metal or
metal/silicon alloy prior to sintering may be done in any one of several
ways:
1. sputtering or evaporation;
2. co-sputtering metal and silicon in the desired ratio from two
independent targets;
3. co-evaporation from the elements.
• Although the properties of silicides make them attractive alternatives to
polysilicon, there are extra processing steps which offset this advantage.
AREA CAPACITANCES OF LAYERS
• Conducting layers are separated from the substrate and each other by
insulating (dielectric) layers, and thus parallel plate capacitive effects
exist.
• For any layer, knowing the dielectric (silicon dioxide) thickness, we can
calculate area capacitance as follows:

• D = thickness of silicon dioxide

• A = area of plates (and it is assumed that Ɛo, A, and D are in compatible
units, for example, Ɛo in farads/cm, A in cm2 , D in cm).
• Ɛins = relative permittivity of Si02 = 4.0
• Ɛo = 8.85 x 10-14 F/cm (permittivity of free space)
STANDARD UNIT OF CAPACITANCE Cg
• It is convenient to employ a standard unit of capacitance that can be
given a value appropriate to the technology but can also be used in
calculations without associating it with an absolute value.
• The unit is denoted Cg and is defined the gate-to-channel capacitance
of a MOS transistor having W = L = feature size, that is, a 'standard' or
'feature size' square as in Figure for example, for lambda-based rules.
• Cg may be evaluated for any MOS process.
• For example, for 5 µm MOS circuits:
Area/standard square = 5 µm x 5 µm = 25 µm2 (= area of minimum size
transistor)
Capacitance value = 4 x 10-4 pF/µm2
Thus, standard value Cg = 25 µm2 x 4 x 10-4 pF/µm2 = .01 pF
• For 2 µm MOS circuits (Orbit):
Area/standard square = 2 µm x 2 µm = 4 µm2
Gate capacitance value = 8 x 10-4 pF/µm2
Thus, standard value Cg = 4 µm2 x 8 x 10-4 pF/µm2 = .0032 pF
• for 1.2 µm MOS circuits (Orbit):
Area/standard square = 1.2 for 1.2 µm MOS circuits (Orbit):
Area/standard square = 1.2 µm x 1.2 µm = 1.44 µm2
Gate capacitance value (from Table 4.2) = 16 x 10-4 pF/µm2
Thus, standard value Cg =1.44 µm2 x 16 x 10-4 pF/µm2 = .0023 pF
Typical sheet resistances Rs of MOS layers for 5 um (in ohm per square)
 SOME AREA CAPACITANCE CALCULATIONS

• Consider the area as metal 1. Capacitance to substrate = relative area x

relative C value = 15 X 0.0750Cg = 1.125Cg
• Consider the same area in polysilicon. Capacitance to substrate= 15 x
0.1Cg = 1.5Cg
• Consider the same area in n-type diffusion. Capacitance to substrate =
15 x 0.25Cg = 3.75Cg
Calculate the capacitance of the multilayer shown below
Calculate the capacitance of the multilayer shown below
THE DELAY UNIT Ʈ
• The concept of sheet resistance Rs and standard gate capacitance unit
Cg for calculation of delay
• If we consider the case of one standard (feature size square) gate area
capacitance being charged through one feature size square of n channel
resistance that is, through Rs for an nMOS pass transistor channel we
have:
• Time constant Ʈ =(1Rs (n channel) x 1Cg) seconds
• In practice, circuit wiring and parasitic capacitances must be allowed
for so that the figure taken for t is often increased by a factor of two
or three
• For 5µm circuit
Ʈ = 0.2 to 0.3 nsec is the typical design figure used in assessing likely
worst case delays.
• Note that Ʈ thus obtained is not much different from transit time tsd
calculated

• Note that Vds varies as Cg charges from 0 volts to 63% of VDD in period
Ʈ so that an appropriate value for Vds is the average value = 3V
• For 5 µm technology

• Since the transition point of an inverter or gate is 0.5 VDD which is close to 0.63
VDD it appears to be common practice to use transit time and time constant
interchangeably and 'stray' capacitances are usually allowed for by doubling
the theoretical values calculated.
• In view of this, Ʈ is used as the fundamental time unit and all timings in a
system can be assessed in relation to t.
• For 5 µm MOS technology Ʈ = 0.3 nsec
• For 2 µm Orbit MOS technology, Ʈ = 0.2 nsec
• For 1.2 µm Orbit MOS technology, Ʈ = 0.1 nsec
INVERTER DELAYS
• Consider the basic 4: 1 ratio nMOS inverter. In order to achieve the 4:1
Zp.u. to Zp.d. ratio, Rp.u. will be 4 Rp.d. and if Rp.d. is contributed by the
minimum size transistor then, clearly, the resistance value associated
with Rp.u.
Rp.u. = 4Rs = 40 kohms
• Meanwhile, the Rp.d. value is 1Rs = 10 kohm so that the delay associated
with the inverter will depend on whether it is being turned on or off.
• However, if we consider a pair of cascaded inverters, then the delay over
the pair will be constant irrespective of the sense of the logic level
transition of the input to the first. This is clearly seen from Figure and,
assuming t = 0.3 nsec and making no extra allowances
• for wiring capacitance, we have an overall delay of Ʈ + 4 Ʈ = 5 Ʈ.
nMOS inverter pair delay
• Delay through a pair of similar nMOS inverters is

• Thus, the inverter pair delay for inverters having 4: 1 ratio is 5 Ʈ.

• However, a single 4: 1 inverter exhibits undesirable asymmetric
delays since the delay in turning on is, for example, Ʈ , while the
corresponding delay in turning off is 4 Ʈ.
• Quite obviously, the asymmetry is worse when considering an
inverter with an 8:1 ratio.
• When considering CMOS inverters, the nMOS ratio rule no longer
applies, but we must allow for the natural (Rs ) asymmetry of the
usually equal size pull-up p-transistors and the n-type pull-down
transistors.
• Figure shows the theoretical delay associated with a pair of minimum
size (both n-and p-transistors) lambda-based inverters.

CMOS inverter pair delay

• Note that the gate capacitance =2Cg ,double that of the comparable
nMOS inverter since the input to a CMOS inverter is connected to both
transistor gates.
• Note also the allowance made for the differing channel resistances.
• The asymmetry of resistance values can be eliminated by increasing the
width of the p-device channel by a factor of two or three, but it should
be noted that the gate input capacitance of the p-transistor is also
increased by the same factor.
• This, to some extent, offsets the speed-up due to the drop in resistance,
but there is a small net gain since the wiring capacitance will be the
same.
Formal Estimation of CMOS Inverter Delay
Rise time Estimation
• the p-device stays in saturation for the
entire charging period of the load
capacitor CL.
• The saturation current for the p-transistor
is given by

• This current charges CL and the output

volatge of the capacitor is

Rise-time model.
• Substituting for ldsp and rearranging we
have
• When t = Ʈ r when Vout = + VDD

• with IVtpl = 0.2VDD

Fall-time estimation
• During fall time CL discharges
through the n transistor in the
saturation region
• Similar to rise time the fall time can
be estimated as

• Using these expressions we may

deduce that: Fall - time model.
• But µn = 2.5 µp and hence βn * 2.5βP so that the rise-time is
slower by a factor of 2.5 when using minimum size devices for
both 'n' and 'p’.
• In order to achieve symmetrical operation using minimum
channel length, we would need to make WP = 2.5Wn and for
minimum size lambda-based geometries this would result in the
inverter having an input capacitance of 1Cg (n-device) + 2.5Cg(p-
device) = 3.5Cg in total.
• Factors which affect rise-times and fall-times as follows:
1. Ʈr and Ʈf are proportional to 1/VDD;
2. Ʈr and Ʈf are proportional to CL
3. Ʈr =2.5 Ʈf for equal n-and p-transistor geometries.
DRIVING LARGE CAPACITIVE LOADS
• Comparatively large capacitive loads arises when signals must be
propagated from the chip to off chip destinations .
• Generally, typical off chip capacitances may be several orders higher
than on chip Cg values.
• For example, if the off chip load is denoted CL then
• Clearly capacitances of this order must be driven through low
resistances, otherwise excessively long delays will occur.
Cascaded Inverters as Drivers
f is the rate and which
width increases

• Inverters intended to drive large capacitive loads must have low pull-up and pull-
down resistance.
• For MOS circuits, low resistance values for Zp.d. and Zp.u. imply low L: W ratios
• Channels must be wide to reduce resistance value and, in consequence, an
inverter needs large area.
• Moreover, because of the large L: W ratio and since length L cannot be reduced
below the minimum feature size, the gate region area L x W becomes significant
and a comparatively large capacitance is presented at the input, which in tum
slows down the rates of change of voltage which can take place at the input.
• The remedy is to use N cascaded inverters, each one of which is larger than the
preceding stage by a width factor f as shown in Figure
• As width of the gate increases, gate Capacitance value increases
• The rate at which the width increases will influence the number of
stages N which must be cascaded to drive a particular value of CL.
Thus, an optimum solution must be sought as follows
• To determine the value of f which will minimize the overall delay for a
given value of y and from the definition of y

• Total delay is minimized if f assumes the value e (base of natural ·

logarithms); that is, each stage should be approximately 2.7* times wider
than its predecessor for CMOS as well as nMOS inverters.
PROPAGATION DELAYS -Cascaded Pass Transistors
• Pass transistors are used as series or parallel switches in logic arrays.
Thus,logic signals must pass through a number of pass transistors in
series.
• A chain of four such transistors is shown in Figure (a) in which all gates
have been shown connected to VDD (logic 1), which would be the
case for a signal to be propagated to the output.
• The circuit thus formed may be modeled as in Figure (b) and it is then
possible to evaluate the delay through the network.
Design of Long Polysllicon Wires
• Long polysilicon wires also contribute distributed series R and C as was
the case for cascaded pass transistors and, in consequence, signal
propagation is slowed down.
• For long polysilicon runs, the use of buffers is recommended.
• In the diagram the slow rise-time of the signal at the input of the
inverter (to which the signal emerging from the long polysilicon
line is connected) means that the input voltage spends a relatively
long time in the vicinity of Vinv so that small disturbances due to
noise will switch the inverter state between '0' and '1' as shown at
the output point.
• Thus it is essential that long polysilicon wires be driven by suitable
buffers to guard against the effects of noise and to speed up the
rise-time of propagated signal edges.
 Super Buffers
• The asymmetry of the conventional inverter is clearly
undesirable, and gives rise to significant delay problems when
an inverter is used to drive more significant capacitive loads.
• A common approach used in nMOS technology to alleviate this
effect is to make use of super buffers
• Considering a positive going logic transition Vin at the input, it
will be seen that the inverter formed by T1 and T2 is turned on
and, thus, the gate of T3 is pulled down toward 0 volt with a
small delay. Thus, T3 is cut off while T4 (the gate of which is also
connected to Vin) is turned on and the output is pulled down
quickly.
• Now consider the opposite transition: when Vin drops to 0 volt,
then the gate of T3 is allowed to rise quickly to V DD· Thus, as
T4 is also turned off by Vin
• T3 is made to conduct with VDD on its gate, that is, with twice
the average voltage that would apply if the gate was tied to the
source as in the conventional nMOS inverter.
• Since Ids is proportional Vgs then doubling the effective Vgs will
increase the current and thus reduce the delay in charging any
capacitance on the output.
• The corresponding non-inverting
nMOS super buffer circuit is given
at Figure
BICMOS Drivers
• The availability of bipolar transistors in BiCMOS technology presents the
possibility of using bipolar transistor drivers as the output stage of inverter
and logic gate circuits.
• Bipolar transistors have transconductance gm and current/area
characteristics that are greatly superior to those of MOS devices. This
indicates high current drive capabilities for small areas in silicon.
• Bipolar transistors have an exponential dependence of the output current Ic
on the input base to emitter voltage Vbe· This means that the device can be
operated with much smaller input voltage swings, much better switching
performance, primarily as a result the smaller input voltage swings..
• Vbe is logarithmically dependent on base width, doping level NA, electron
mobility and collector current Ic it is only linearly dependent on T.
• The switching performance of a transistor driving a capacitive load may
be visualized initially from the simple model given in Figure
• The time necessary to change the output voltage by an amount that is
equal to the input change is given by

• learly, since the bipolar transistor has a relatively

high transconductance, the value of is small.
• A more exacting appraisal of the bipolar transistor delay reveals that it
comprises two main components:
1. Tin -an initial time necessary to charge the base emitter junction of
the bipolar (npn) transistor. Typically is in the region of 2ns.
2. TL-the time taken to charge the output load capacitance CL and it
will be noted that this time is less for the bipolar driver by a factor
of hfe where hfe is the bipolar transistor gain.