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Unit IV (Design Examples)

The document provides an overview of arithmetic circuits in digital electronics, detailing their functions and components such as half adders, full adders, and subtractors. It explains the implementation and logic behind these circuits, including truth tables and logical expressions. Additionally, it covers code converters like binary to decimal and BCD to seven-segment decoders, illustrating their importance in digital systems.

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0% found this document useful (0 votes)
3 views61 pages

Unit IV (Design Examples)

The document provides an overview of arithmetic circuits in digital electronics, detailing their functions and components such as half adders, full adders, and subtractors. It explains the implementation and logic behind these circuits, including truth tables and logical expressions. Additionally, it covers code converters like binary to decimal and BCD to seven-segment decoders, illustrating their importance in digital systems.

Uploaded by

shlokparekh08
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Unit-IV

Design Examples
Arithmetic Circuits
An arithmetic circuit in digital electronics is a type of combinational circuit that is designed to perform arithmetic operations on
binary numbers. These operations can include addition, subtraction, incrementing, decrementing, multiplication, and division.

Basic Concept
● Arithmetic circuits are built using basic building blocks such as logic gates (AND, OR, NOT, XOR, etc.) and more complex
components like:

○ Half Adder

○ Full Adder

○ Subtractors

○ Multiplexers

○ Arithmetic Logic Unit (ALU)


Common Arithmetic Circuits

1. Half Adder

2. Full Adder

3. Ripple Carry Adder

4. Carry Look-Ahead Adder (CLA)

5. Subtractor Circuits

6. Multipliers & Dividers

7. Arithmetic Logic Unit (ALU)


Half Adder in Digital Logic
A half adder is a combinational logic circuit that performs binary addition of two single-bit inputs, A and B,
producing two outputs: SUM and CARRY. The SUM output which is the least significant bit (LSB) is obtained
using an XOR gate while the CARRY output which is the most significant bit (MSB) is generated using an
AND gate.
The half adder is a fundamental building block for more complex adder circuits, such as full adders and
multi-bit adders. It allows the addition of two binary digits but does not account for carry-in from a previous
stage. The circuit requires one XOR gate and one AND gate for implementation.

Truth Table of Half Adder


Logical Expression of Half Adder

For Carry
For Sum

Sum = A XOR B Carry = A AND B

Implementation of Half Adder


Full Adder in Digital Logic
Full Adder is a combinational circuit that adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the
normal output is designated as S which is SUM.

● The C-OUT is also known as the majority 1's detector, whose output goes high when more than
one input is high.
● A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to another.
● We use a full adder because when a carry-in bit is available, another 1-bit adder must be used
since a 1-bit half-adder does not take a carry-in bit.
● A 1-bit full adder adds three operands and generates 2-bit results.
Full Adder Truth Table

A Full Adder takes three binary inputs:


● A (first bit)
● B (second bit)
● C-IN (carry input)

And it produces two outputs:


● Sum (S)
● Carry Out (C-OUT)
Logic Circuit of Full Adder

To implement a Full Adder using basic logic gates:


1. Sum (S) is implemented using XOR gates:
● Use two XOR gates:
○ First XOR gate: A ⊕ B
○ Second XOR gate: (A ⊕ B) ⊕ C-IN to get the final sum S.
2. Carry (C-Out) is implemented using XOR,AND and OR gates:
● First AND gate: This gate calculates A AND B.
● Second AND gate: This gate calculates C-IN AND (A ⊕ B). To do this, you need the result of the first XOR
gate (A ⊕ B) as an input to the second AND gate.
Implementation of Full Adder using Half Adders

2 Half Adders and an OR gate is required to implement a Full Adder.

With this logic circuit, two bits can be added together, taking a carry from the next lower order of magnitude,
and sending a carry to the next higher order of magnitude.
Half Subtractor in Digital Logic

- A half subtractor is a digital logic circuit that performs the binary subtraction of two single-bit binary
numbers.
- It has two inputs, A and B, and two outputs, Difference and Borrow.
- The Difference output represents the result of subtracting B from A, while the Borrow output
indicates whether a borrow is needed when A is smaller than B.
- The half subtractor can be implemented using basic logic gates such as XOR, AND, and NOT gates.
- It is a fundamental building block for more complex arithmetic circuits like full subtractors and
multi-bit subtractors.
Logical Expression of Half Adder

For Carry
For Sum

Sum = A XOR B Carry = A AND B

Implementation of Half Adder


Truth table for half subtractor Logical Expression of Half Subtractor
For Difference

The SOP form of the Difference is as follows:

Logical Expression of Half Subtractor Difference = A'B+AB'


For Borrow

The SOP form of the Borrow is as follows:


Borrow = A'B
Full Subtractor in Digital Logic

A Full Subtractor is a combinational circuit used to perform binary subtraction. It has three inputs:
● A (Minuend)
● B (Subtrahend)
● B-IN (Borrow-in from the previous stage)

It produces two outputs:

● Difference (D): The result of the subtraction.


● Borrow-out (B-OUT): Indicates if a borrow is needed for the next stage.

The full subtractor is essential because a half-subtractor can only subtract the least significant bit (LSB) of
binary numbers. However, if a borrow is generated during the subtraction of the LSBs, it will affect the
subtraction in the next stages. A full subtractor handles this situation by considering the borrow from the
previous stage, ensuring accurate subtraction even when a borrow is present.
Truth Table of Full Subtractor K-Map for Difference
Logical expression for difference
The basic expression is:
D = A'B'Bin + A'BBin' + AB'Bin' + ABBin
Factoring common terms:
D = Bin(A'B' + AB) + Bin'(AB' + A'B)
Recognizing XOR and XNOR properties:
A'B' + AB = A XNOR B
AB' + A'B = A XOR B
Substituting these values:
D = Bin(A XNOR B) + Bin' (A XOR B)
Using XNOR identity:
D = Bin ⊕ (A ⊕ B)
Thus, the final simplified expression for the difference in a full subtractor is:
D = (A ⊕ B) ⊕ Bin
Logical expression for borrow

K-Map for Borrow The borrow (Bout) output is derived as follows:


The basic expression:
Bout = A'B'Bin + A'BBin' + A'BBin + ABBin

Factoring common terms:


Bout = A'Bin(B + B') + A'B(Bin + Bin') + BBin(A + A')

Simplifying:
Bout = A'Bin + A'B + BBin

Alternatively, using another approach:


Bout = A'B'Bin + A'BBin' + A'BBin + ABBin

Factoring common terms:


Bout = Bin(AB + A'B') + A'B(Bin + Bin')

Using XOR and XNOR properties:


AB + A'B' = A XNOR B
Substituting these values:
Bout = Bin(A XNOR B) + A'B
Using XNOR identity:
Bout = Bin (A XOR B)' + A'B
Logic Circuit for Full Subtractor
BCD-to-7 segment decoder:
- The Seven segment display is most frequently used the digital display in calculators, digital counters,
digital clocks, measuring instruments, etc.
- Seven Segment display is an electronic device which consists of seven Light Emitting Diodes (LEDs)
arranged in a some definite pattern (common cathode or common anode type), which is used to display
Hexadecimal numerals(in this case decimal numbers, as input is BCD i.e., 0-9).
- Two types of seven segment LED display:
1. Common Cathode Type: In this type of display all cathodes of the seven LEDs are connected
together to the ground or -Vcc(hence, common cathode) and LED displays digits when some 'HIGH'
signal is supplied to the individual anodes.
2. Common Anode Type: In this type of display all the anodes of the seven LEDs are connected to
battery or +Vcc and LED displays digits when some 'LOW' signal is supplied to the individual
cathodes.
BCD-to-7 segment decoder:
- Seven segment display does not work by directly supplying voltage to different segments
of LEDs.
- First, our decimal number is changed to its BCD equivalent signal then BCD to seven
segment decoder converts that signals to the form which is fed to seven segment display.
- This BCD to seven segment decoder has four input lines (A, B, C and D) and 7 output
lines (a, b, c, d, e, f and g), this output is given to seven segment LED display which
displays the decimal number depending upon inputs.
Truth Table for BCD-to-7 segment decoder:

For common cathode type BCD to seven segment decoder: Explanation -


-For combination where all the inputs
(A, B, C and D) are zero (see Truth
Table), our output lines are a = 1, b = 1,
c = 1, d = 1, e = 1, f = 1 and g = 0. So 7
segment display shows 'zero' as output.
-Similarly, for combination where one of
the input is one (D = 1) and rest are
zero, our output lines are a = 0, b = 1, c
= 1, d = 0, e = 0, f = 0 and g = 0. So
only LEDs 'b' and 'c' will glow and 7
segment display shows 'one' as output.
K-Maps:

For a: For b: For c:

f(A,B,C,D)=C+A+BD+B’D’ f(A,B,C,D)=B’+C’D’+CD f(A,B,C,D)=B+D+C’


K-Maps:

For d: For e: For f:

f(A,B,C,D)=A+B’D’+B’C+CD f(A,B,C,D)=B’D’+CD’ f(A,B,C,D)=A+BC’+BD’+C’D’


’+BC’D
K-Maps:

For g: 7-Segment Display Decoder Circuit

f(A,B,C,D)=A+BC’+B’C+CD’
Code Converters

-A code converter is a digital electronic circuit that is used to convert a digital code from one form to
another. A digital code is nothing but a piece of data or information represented in binary format, i.e., in the
form of strings of 0s and 1s.

-A code converter is simply a translator which translates a code from one format to another. For example,
binary to decimal converter, BCD to Excess-3 converter, binary to decimal converter, etc.

-Code converters are essential components in various digital systems that use different encoding schemes.
They help to make two different digital systems compatible with each other.

Function of a Code Converter


The primary function of a code converter is to accept code in one format and translate it into a different
format.

A code converter reads and interprets the input code and produces an equivalent output code according to
its functionality. For example, a binary-to-decimal code converter takes a binary code as input and
generates an equivalent decimal code as output.
Types of Code Converters

Depending on the conversion task that a code converter performs, the following are some common types of
code converters −

1. Binary to Decimal Converter


2. Decimal to BCD Converter
3. BCD to Decimal Converter
4. Binary to Gray Code Converter
5. Gray Code to Binary Converter
6. BCD to Excess-3 Converter
7. Excess-3 to BCD Converter
Binary to Decimal Converter

A type of code converter used to convert data from binary format to decimal format is called a
binary-to-decimal converter.

The input to the binary-to-decimal converter is a number represented in a format of 0s and 1s. Then, the
converter uses an algorithm to convert the input binary number into an equivalent decimal number. Finally,
it generates a decimal code as output.

Truth Table: Expressions A B


Q0=A’B’
Binary Input Decimal
Output Q1=A’B
A B Q2=AB’

0 0 Q0 Q3=AB

0 1 Q1

1 0 Q2

1 1 Q3
Decimal to BCD Converter
A decimal-to-BCD (Binary Coded Decimal) converter is a type of code convert that converts a decimal
number into its equivalent 4-bit binary code, called BCD code.
Decimal BCD Code The Boolean expressions
B3 B2 B1 B0 B0=D1+D3+D5+D7+D9
B1=D2+D3+D6+D7
0 0 0 0 0 B2=D4+D5+D6+D7
1 0 0 0 1 B3=D8+D9
The logic circuit implementation
2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1
BCD to Decimal Converter
- A digital circuit that can convert a binary-coded decimal (BCD) number into an equivalent decimal
number is referred to as a BCD-to-decimal converter.
Boolean Expression: The logic circuit implementation
BCD Code Decimal

B3 B2 B1 B0

0 0 0 0 D0

0 0 0 1 D1

0 0 1 0 D2

0 0 1 1 D3

0 1 0 0 D4

0 1 0 1 D5

0 1 1 0 D6

0 1 1 1 D7

1 0 0 0 D8

1 0 0 1 D9
Binary to Gray Code Converter
A binary-to-gray code converter is a type of code converter that can translate a binary code into its
equivalent gray [Link] binary-to-gray code converter accepts a binary number as input and produces a
corresponding gray code as output.
Binary to Gray Code Converter

Boolean Expression: The logic circuit implementation:

G0=B’1B0+ B1B’0=B0⊕B1
G1=B’2B1+ B2B’1=B1⊕B2
G2=B’3B2+ B3B’2=B2⊕B3
G3=B3
Gray Code to Binary Converter
A gray code-to-binary converter is a digital circuit that can translate a gray code into an equivalent pure
binary code. Thus, a gray code to binary converter takes a gray code as input and gives a pure binary code
as output.

Truth Table:
Boolean Expression: The logic circuit implementation

Gray Code Binary Code B0=G0⊕G1⊕G2


B1=G1⊕G2
G2 G1 G0 B2 B1 B0
B2=G2
0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 1

0 1 1 0 1 0

1 0 0 1 1 1

1 0 1 1 1 0

1 1 0 1 0 0

1 1 1 1 0 1
BCD to Excess-3 Converter

A type of code converter in


digital electronics that is used
to convert a binary-coded
decimal number into an
equivalent excess-3 code is
called a BCD to excess-3
converter.

Hence, in the case of a BCD


to excess-3 code converter,
the input is an 8421 BCD
code and the output is an
XS-3 code.
BCD to Excess-3 Converter

K-Map for XS-3 Bit X0 K-Map for XS-3 Bit X1 K-Map for XS-3 Bit X2
The K-map simplification for the The K-map simplification for the The K-map simplification for the
XS-3 bit X0 is shown in the XS-3 bit X1 is shown in the XS-3 bit X2 is shown in the
following figure − following figure − following figure −

Boolean expression, X0=B’0 Boolean expression, Boolean expression,

X1=B’0B’1 +B0B1 X2=B’2B1 +B’2B0 +B2B’1B’0


BCD to Excess-3 Converter
The logic circuit diagram of the BCD to XS-3 converter is
K-Map for XS-3 Bit X3 shown in the following figure −

The K-map simplification for the


XS-3 bit X3 is shown in the
following figure −

Boolean expression,

X3=B3+B2B1 +B2B0
Excess-3 to BCD Converter

An excess-3 to BCD converter is a


type of code converter in digital
electronics used to translate an
XS-3 code into an equivalent
binary-coded decimal.

Therefore, an XS-3 to BCD code


converter accepts a digital code in
XS-3 format and produces an
equivalent digital code in BCD
format.
Excess-3 to BCD Converter

K-Map for BCD Bit B0 K-Map for BCD Bit B1 K-Map for BCD Bit B2
The following figure shows the The K-map simplification for the BCD
The following figure shows the
K-map simplification for the BCD bit bit B2 is shown below −
K-map simplification for the BCD
B1.
bit B0.

Boolean expression,
Boolean expression,
Boolean expression, B0=X’0 B2=X’2X’1 +X’2X’0 +X2X1X0
B1=X’1X0 +X1X0
BCD to Excess-3 Converter
The logic circuit diagram to convert an XS-3 code into
K-Map for BCD Bit B3 equivalent BCD code i.e., Excess-3 to BCD converter is shown
in the following figure −
The K-map simplification for the BCD
bit B3 is shown in the following
figure −

Boolean expression,

B3=X3X2+X3X1 X0
Subtractor Using n-bit Adders
1. Background:

○ When subtracting two numbers A and B, they can be either both positive/negative (same sign) or one
positive, one negative (opposite signs).

○ If the subtraction result is too large to be represented with the given number of bits (n-bits), it’s called
overflow.

○ If the result is too small to be represented, it’s called underflow.

2. Purpose of the Circuit:


The circuit in Figure shows how subtraction can be done using two n-bit adders. It also checks for overflow
and underflow, and gives the correct magnitude and sign of the result.
Subtractor Using n-bit Adders
How the Circuit Works:
● Inputs:
○ AAA and BBB are the two numbers to be subtracted.
○ Each number has n bits.
● n-bit Adders:
○ The circuit uses two n-bit adders (AD1 and AD2) to calculate the difference.
○ AD1 helps to find the sum/difference when A and B are in normal order.
○ AD2 is used to handle the magnitude output in case overflow/underflow occurs.
● Logic Indicators:
○ Overflow Indicator: Turns on if the result is too large to represent.
○ Underflow Indicator: Turns on if the result is too small to represent.
● Output:
○ Sign Bit: Shows whether the result is positive (0) or negative (1).
○ Magnitude: Gives the absolute value of the result.
● Extra Logic:
XOR gates are used to handle the differences in bit signs when numbers have different signs.
The circuit ensures the subtraction is correct even if overflow or underflow occurs.
Multiplexer
A multiplexer is a combinational circuit that has many data inputs and a single output, depending on control
or select inputs. For N input lines, log2(N) selection lines are required, or equivalently, for 2n input lines, n
selection lines are needed.
● Multiplexers are also known as "N-to-1 selectors," parallel-to-serial converters, many-to-one
circuits, and universal logic circuits.
● They are mainly used to increase the amount of data that can be sent over a network within a
certain amount of time and bandwidth.

● Table gives the truth table of a 4:1 multiplexer with active-low enable input(G)

Its output Y will be

● Realisation of equation using NAND gate


Adders and Their Use as Subtractors:
(a) shows a Ripple-Carry n-bit adder built from n
full adders (FA0, FA1, ... FA(n−1)).

● Inputs: A and B

● Outputs: Sum bits (S) and final carry (Cₙ)

(b) shows a block diagram of an n-bit adder — a


simplified version that takes all A and B inputs, plus
a carry-in, and gives the sum and final carry-out.
Adders and Their Use as Subtractors:
1. Basic Idea
Adders are circuits that add binary numbers.
But — they can also be used for subtraction, because subtraction can be done by adding the 2’s complement of a number.
So instead of designing separate subtractor circuits, we can perform both addition and subtraction using the same adder circuit.

2. What is an n-bit Adder?


An n-bit adder is made up of n full adders connected in series.
Each full adder can add two bits and a carry input, and gives a sum and a carry output.
It takes:
● Two n-bit binary numbers:

● And gives an (n+1)-bit result (sum + carry out).

3. Ripple-Carry Adder
In the ripple-carry adder:
● The carry output of each full adder goes to the next full adder as carry input.
● This means the carry ripples (moves) from the least significant bit (LSB) to the most significant bit (MSB).

Limitation:
This process is slow because each adder has to wait for the carry from the previous one — this is called propagation delay.
Adders and Their Use as Subtractors:
4. Look-Ahead Carry Technique
To make it faster, we use look-ahead carry adders.
These circuits predict the carry for each stage in advance, so the adder can work faster.

5. Using Adders as Subtractors


So, subtraction can be done by:
1. Taking 1’s complement of B (inverting all bits)

2. Adding 1 to it (carry input = 1)

3. Then adding this to A using the same adder

Thus, a single adder circuit can perform both addition and subtraction — just by changing how we input B and the initial carry.

Adders can also be used as subtractors. Binary subtraction can be performed using the 2’s complement method, where subtraction
A−BA - BA−B is done by adding the 2’s complement of B to A. The 2’s complement of B is obtained by inverting all bits of B (1’s
complement) and adding 1 to it. Thus, the same adder circuit can perform both addition and subtraction by controlling whether B is
inverted and whether the initial carry input is set to 1 or 0.
Look ahead carry adder-
- A carry-lookahead adder (CLA) or fast adder is a type of electronics adder used in digital logic.
- A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits.
- It is different from the simpler but slower ripple-carry adder (RCA), where each stage has to wait for the
previous carry bit to be calculated before it can find its own sum and carry bits.
- The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time
to calculate the result of the larger-value bits of the adder.
Look ahead carry adder-
-Consider the full adder circuit shown above with corresponding truth table. We
define two variables as 'carry generate' Gi and 'carry propagate' Pi then,
Pi =Ai ⊕ Bi
Gi =Ai Bi
-The sum output and carry output can be expressed in terms of carry generate Gi
and carry propagate Pi as

Si=Pi⊕Ci
Ci+1=Gi+PiCi
-where Gi produces the carry when both Ai,Bi are 1 regardless of the input carry.
Pi is associated with the propagation of carry from Ci to Ci+1.
-The carry output Boolean function of each stage in a 4 stage carry look-ahead
adder can be expressed as
Arithmetic Logic Unit (ALU)
A very popular and widely used combinational circuit is ALU which is capable of performing arithmetic as well
as logical operations. This is the heart of any microprocessor. Figure shows the block diagram of 74181 ALU
and Table gives its function table
The functions of various input, output and control lines are given
below:

● A and B: 4-bit binary data inputs


● C’n: Carry input (active-low)
● F: 4-bit binary data output
● C’n+4: Carry output (active-low)
For subtraction operation, it indicates the sign of the output. Logic
0 indicates positive result and logic 1 indicates negative result
expressed in 2’s complement form.
● A=B: Logic 1 on this line indicates A=B
● G: Carry generate output
● P: Carry propagate output
● G and P outputs are used when a number of 74181 circuits are used
in cascade along with 74182 Look-ahead Carry-generator circuit to
make the arithmetic operations faster.
● Select input (S): Used to select any operation (Table 6.6)
Mode Control (M):
M = 0 Arithmetic operations
M = 1 Logic operations
● The 74181 can be cascaded by connecting the carry-out of a stage
to the carry-in of the succeeding stage.
Function table of 74181 ALU:
Parity Generator /Checker:
-The concept of parity, wherein an additional bit known
as the parity-bit is added to a binary word to make the
number of 1’s, in the new word formed, even (even
parity) or odd (odd parity).

-Because of its wide use, an 8-bit parity


generator/checker circuit has been designed and is
available as a MSI chip (74180).

-Figure gives the block diagram of 74180 in which there


are eight parity inputs A through H and two cascading
inputs. There are two outputs Σ EVEN and Σ ODD.
Function table of 74180(Parity Checker):

Function table of 74180 as a 9-bit Parity Generator:

The cascading inputs must not be equal and the unused parity inputs must be tied
to logic 0 level.
Digital Comparators:
A digital combinational circuit used to compare the magnitude of two binary numbers to determine the equality
or non-equality is called a comparator.

Therefore, the main function of a comparator is to compare the values of input numbers and produce an output
indicating whether the numbers are equal or specifies which of the numbers is greater.

Consider two 3-bit binary numbers A2A1A0 and B2B1B0. These two binary numbers are said to be equal if all their
corresponding bits coincide. In other words, these two binary numbers are equal if A 2 = B2, A1 = B1, and A0 =
B0.

The block diagram of a typical comparator is shown in the following figure −

Here, A and B are the input bits,


and L, E, and G are the output
lines, where L indicates which
number is smaller, E indicates
equality, and G indicates the
greater number.
Types of Comparators
1-Bit Magnitude Comparator
2-Bit Magnitude Comparator
4-Bit Magnitude Comparator
1-Bit Magnitude Comparator
A 1-bit magnitude comparator is a logic circuit which can compare two binary numbers of one bit each. It
produces an output that indicates the relationship between the two input numbers.

In other words, a 1-bit magnitude comparator is one that compares two 1-bit binary numbers and generates an
output showing whether one number is equal to or greater than or less than the other.

The block diagram of a 1-bit magnitude comparator is shown in the following figure −

Here, A and B are the 1-bit input numbers, and L, E, and G are the output lines indicating less than or equal to
or greater than relationship between A and B respectively.
Let us understand the working this type of comparator.

If A = 0 and B = 0 or if A = 1 and B = 1, then A = B. It indicates that the two binary numbers are equal.

Therefore,

If A = 0 and B = 1, then A < B. This indicates that the binary number A is less than the binary number B. Therefore, L=A’ B

If A = 1 and B = 0, then A > B. It indicates that the binary number A is greater than the binary number B. Therefore, G=A B’

The 1-bit magnitude comparator compares the corresponding bits of the input numbers A and B. For this, it uses different
types of logic gates.

The truth table of the 1-bit magnitude comparators is given below − Expressions:-
2-Bit Magnitude Comparator
A digital combinational circuit used to compare the magnitudes of two 2-bit binary numbers and determine
the relationship between them is called a 2-bit magnitude comparator.

Hence, the 2-bit magnitude comparator compares the values represented by two 2-bit binary numbers and
then generates an output that indicates whether one number is equal to or greater than or less than the
other.

The block diagram of a typical 2-bit magnitude comparator is shown in the following figure −

Here, the lines A0A1 and B0B1 represents two 2-bit binary number inputs and the lines L, E, and G
represents the less than, equal to, and greater than output lines.
We can understand the operation of the 2-bit magnitude comparator with the help of its truth table given
below −
4-Bit Magnitude Comparator
The 4-bit magnitude comparator is used in more complex digital circuits like microprocessors,
microcontrollers, and many more.

It is a type of comparator that can compare the values or magnitudes of two 4-bit binary numbers and
produce an output indicating whether one number is equal to or less than or greater than the other.

The block diagram of the 4-bit magnitude comparator is shown in the following figure −

Let us now understand the working of this 4-bit magnitude comparator. For that consider A = A 3A2A1A0 is
the first 4-bit binary number and B = B3B2B1B0 is the second 4-bit binary number.

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