Superscalar Example
30 April 2026 12:38
Tip for Question Solving - Solve later stages first and earlier stages later
Superscalar Pipeline
• IF
• ID
• Dispatch (Allocate)
• Wake-up
• Select
• EX - Simple ALU x2
• EX - Complex ALU x1 - Depth 3
• EX - MEM x2 - Depth 2
• EX - Branch - Depth 1
• WB
• Commit
Issue width = 4
• 32 Architectural Registers
• 56 Physical Registers
• Renaming done using Physical Mapping and Architectural Mapping Table (PMT, AMT)
• RS Width = 32 INST
• RoB = 64 Inst
• Fetch width = 16 byte (4 byte instruction)
• PC = 64 bit
• Assume that every inst fetch and data fetch will be cache hit.
Branch Prediction:
• Type Gas
○ Global History
○ Adaptive
○ Per-set PHT
• 6-bit Global History (BHR = 001111)
• PHT - 1 KB, so it will have 4K entries
• All entries are initially 10 (Weakly Taken State)
• There would be 12 index bits from the BHT, 6 bits from the PC, and 6 bits from the
BHR.
BTAC
IA TA
0x0010 0x1200004
0x202C 0x02008
0x12000C0 0x1200100
0x1200400 0x2000
BTAC compare will happen in every cycle for IF, and instruction will assumed to be a branch
instruction in case of cache hit.
AMT
Arch Phy Cycle Enter Which register released
R4 P32 9 P4
R5 P33 10 P5
R2 P34 10 P2
Superscalar Example Page 1
R2 P34 10 P2
R3 P35 11 P3
R6 P36 15 P6
R7 P37 18 P7
PRF
Index Valid Old Reg Value VValid New Entry Updat Releas
e e
0 1 4 R0 0x1000 1 10
1 1 5 R1 0x2000 1 10
2 1 3 R2 R9 0x0 101 101 11 16 10
0x300C
3 1 3 R3 0x1 0x74 1 0 1 101 11 18 11
R12
4 1 3 R4 R2 0x2 0x8 101 101 12 19 9
5 1 3 R5 R3 0x3 0x9 101 101 12 20 10
6 1 4 R6 0x4 1 10 15
7 1 4 R7 0x5 1 10 18
8 1 R8 0x0C00 1 1
9 1 5 R9 0x3000 1 10
10 1 R10 0x6 1 1
11 1 R11 0x7 1 1
12 1 5 R12 0x8 1 10
13 1 R13 0x9 1 1
14 1 R14 0xA 1 1
15 1 R15 0xB 1 1
Index Valid Old Reg Value VValid New Entry Updat Releas
e e
16 1 R16 0x1 1 1
17 1 R17 0x3 1 1
18 1 R18 0x0 1 1
19 1 R19 0x1 1 1
20 1 R20 0x2 1 1
21 1 R21 0x3 1 1
22 1 R22 0x4 1 1
23 1 R23 0x5 1 1
24 1 R24 0x4 1 1
25 1 R25 0x3 1 1
26 1 R26 0x6 1 1
27 1 R27 0x7 1 1
28 1 R28 0x8 1 1
29 1 R29 0x9 1 1
30 1 R30 0xA 1 1
Superscalar Example Page 2
30 1 R30 0xA 1 1
31 1 R31 0xB 1 1
Index Valid Old Reg Value VValid New Entry Updat Releas
e e
32 1 R4 1080 01 1 3 8
33 1 R5 0x1 01 1 3 9
34 1 6 R2 0x2 01 10 3 9
35 1 6 R3 0x3 01 10 3 10
36 1 7 R6 0x2 01 10 4 14
37 1 7 R7 0x5 01 10 4 17
38 1 7 R0 1004 01 10 4 9
39 1 8 R1 2004 01 10 5 10
40 1 8 R9 3004 01 10 5 10
41 1 8 R12 0x7C 01 10 5 12
42 1 9 R2 0x4 01 10 6 13
43 1 9 R3 0x5 01 10 6 14
44 1 10 R6 0x4 0 10 7 18
45 1 10 R7 0 10 7
46 1 10 R0 0x1008 01 10 7 12
47 1 11 R1 0x2008 01 10 8 13
Index Valid Old Reg Value VValid New Entry Updat Releas
e e
48 1 11 R9 0x3008 01 10 8 13
49 1 11 R12 0x78 01 10 8 15
50 1 12 R2 0x6 01 10 9 16
51 1 12 R3 0x7 01 10 9 17
52 1 R6 0 1 10
53 1 R7 0 1 10
54 1 R0 0x100C 01 1 10 15
55 1 R1 0x200C 0 1 11 16
• Entry, Update and Release are not valid PRF entries, they are used here only to keep
track of the cycles in which table is updated.
• Old column marks the cycle when the previous value was discarded and a new register
was mapped.
RS
Inst Src1 Valid Src2 Valid Dst Offs Ente Wak Sele exit
et r eup ct
I1 0x1000 1 - - P32 80 4 5 6 7
I2 0x0C00 1 - - P33 - 4 5 6 7
I3 0x1000 1 - - P34 - 4 5 6 7
I4 0x2000 1 - - P35 - 4 5 7 8
I5 (0) P33 01 P34 01 P36 - 5 9 10 11
0x1 0x2
I6 P36 0 P35 01 P37 5 14 15 16
0x2 0x3
I7 P37 01 0x3000 1 - 5 17 18 19
Superscalar Example Page 3
I7 P37 01 0x3000 1 - 5 17 18 19
0x5
I8 0x1000 1 - - P38 4 5 6 7 8
I9 0x2000 1 - - P39 4 6 7 8 9
I10 0x3000 1 - - P40 4 6 7 8 9
I11 P32 01 P38 01 P41 - 6 9 10 11
1080 0x1004
I12 P41 01 - - - - 6 12 13 14
0x7C
I3 (1) P38 01 - - P42 - 7 9 10 11
0x1004
I4 P39 01 - - P43 - 7 10 11 12
0x2004
I5 P33 01 P42 01 P44 - 8 13 14 15
0x1 0x4
I6 P44 0 P43 0 P45 - 8 18 19 20
0x4 0x5
Inst Src1 Valid Src2 Valid Dst Offs Ente Wak Sele exit
et r eup ct
I7 P45 0 P40 01 - - 8
0x3004
I8 P38 01 - - P46 4 8 9 10 11
0x1004
I9 P39 01 - - P47 4 9 10 11 12
0x2004
I10 P40 01 - - P48 4 9 10 11 12
0x3004
I11 0x1080 1 P46 01 P49 - 9 12 13 14
0x1008
I12 P49 0 - - - - 9 15 16 17
0x78
I3 (2) P46 01 - - P50 - 10 12 13 14
0x1008
I4 P47 01 - - P51 - 10 13 14 15
0x2008
I5 0x1 1 P50 01 P52 - 11 16 17 18
0x6
I6 P52 0 P51 01 P53 11
0x7
I7 P53 - P48 01 - - 11
0x3008
I8 P46 01 - - P54 4 11 12 13 14
0x1008
I9 P47 01 - - P55 4 12 13 14 15
0x2008
I10 P48 01 - - P2 4 12 13 14 15
0x3008
I11 0x1080 1 P54 01 P3 - 12 15 16 17
0x100C
I12 (2) P3 0 - - - - 12 18 19 20
0x74
I3 (3) P54 01 - - P4 - 13 15 16 17
Superscalar Example Page 4
I3 (3) P54 01 - - P4 - 13 15 16 17
0x100C
I4 (3) P55 01 - - P5 - 13 16 17 18
0x200C
I5
I6
I7
I8
RoB
Inst Spec Status Valid Enter Execute Finish Exit
I1 0 WEF 1 4 7 8 9
I2 0 WEF 1 4 7 9 10
I3 0 WEF 1 4 7 9 10
I4 0 WEF 1 4 8 10 11
I5 0 WE 1 5 11 14 15
I6 0 WE 1 5 16 17 18
I7 0 W 1 5 19
I8 0 WEF 1 5 8 9
I9 0 WEF 1 6 9 10
I10 0 WEF 1 6 9 10
I11 0 WEF 1 6 11 12
I12 0 WEF 1 6 14 15
I3 10 WE 1 7 11 13
I4 10 WE 1 7 12 14
I5 10 WE 1 8 15 18
I6 10 W 1 8
Inst Spec Valid Enter Execute Finish Exit
I7 10 W 1 8
I8 10 WEF 1 8 11 12
I9 10 WE 1 9 12 13
I10 10 WE 1 9 12 13
I11 10 WEF 1 9 14 15
I12 10 W 1 9 17 18
I3 21 WEF 1 10 14 16
I4 21 WE 1 10 15 17
I5 21 WE 1 11 18
I6 21 W 1 11
I7 21 W 1 11
I8 21 WEF 1 11 14 15
I9 21 WEF 1 12 15 16
I10 21 WEF 1 12 15 16
I11 21 WEF 1 12 17 18
I12 21 W 1 12
Superscalar Example Page 5
I12 21 W 1 12
I3 32 WEF 1 13 17 19
I4 32 WE 1 13 18 20
I5
I6
I7
I8
W means Wait in RoB
Ref. to Slides for Initial PRF Values
RS has two slides of 16 entries each.
RoB has a speculation tag, it would be a 4-bit tag, so we would have a speculation depth of
16 instructions.
Doubt - What would happen if speculation tag has two bits and depth = 4?
Instructions
Implementing zi = a*xi + yi through the instructions, where a is a constant.
I1 DADDIU R4, R0, #80 0x2000
I2 LD R5, (R8) 0x2004
L: I3 LD R2, (R0) 0x2008
I4 LD R3, (R1) 0x200C
I5 MUL R6, R5, R2 0x2010
I6 ADD R7, R6, R3 0x2014
I7 ST R7, (R9) 0x2018
I8 ADDIU R0, R0, #4 0x201C
I9 ADDIU R1, R1, #4 0x2020
I10 ADDIU R9, R9, #4 0x2024
Superscalar Example Page 6
I10 ADDIU R9, R9, #4 0x2024
I11 SUB R12, R4, R0 0x2028
I12 BNEZ R12, L 0x202C
I13 ADD R20, R21, R22 0x2030
I14 R24, R22, R23 0x2034
I15 AND R25, R20, R24 0x2038
I16 OR R26, R20, R24 0x203C
Doubt - This is MIPS64 ISA, so R0 should always be 0?
DADDIU - Double Word Add Immediate Unsigned
Cycle 1:
IF I1, I2, I3, I4
• During the fetch of these instructions, all of these instructions addresses will be
checked for in the BTAC (Branch Target Address Cache) to check if instructions are
branch are not. There will be a cache miss for these instructions in the BTAC, but all of
these instructions will have a hit in the BHT and BHT will have a Weakly-Taken State.
• So it will continue to fetch from the next address.
Cycle 2:
IF I5, I6, I7, I8
ID: I1, I2, I3, I4
Again, we have no hit in the BTAC for I5-I8.
Cycle 3:
IF I9,I10,I11, I12
ID: I5, I6, I7, I8
Rename: I1, I2, I3, I4
Here, index 32-35 of PRF will be filled and updated for I1-I4.
Also, there will be a BTAC hit for I12 (address 0x202C), so the instructions will be fetched
from the target address 0x2008.
Also, since this is a non-aligned access and no T-logic is present, we would be able to only
fetch two instructions in the next cycle.
• Here, PC would be 0x202C, so last 6-bits (excluding the last two bits) would be 001011.
• The BHR (00 11 11) would be used as the first 6-bits in the PHT index.
• Hence the PHT index of {BHR,PC[7:2]} will be used to index PT.
• 0011 1100 1011 in hex will be 3CB. So Branch Predictor in address 3CB will be used
(Weakly Taken), which will tell us that we are taking the branch.
Doubt - What will happen if ache hit in BTAC happens for I11 and not I12? Will I12 be
flushed immediately?
Cycle 4:
IF I3, I4 (Tag 1)
ID I9, I10, I11, I12
Rename I5, I6, I7, I8 Entry for this will be made into the PRF.
Dispatch I1, I2, I3, I4 Entry for this will be made into the RS as well as the RoB
Cycle 5:
Superscalar Example Page 7
Cycle 5:
IF I5, I6, I7, I8(Tag
1)
ID I3, I4 (Tag 1)
Rename I9, I10, I11, I12 Entry for this will be made into the PRF.
Dispatch I5, I6, I7, I8 Entry for this will be made into the RS as well as the RoB
Wakeup I1, I2, I3, I4 All instructions are available for wakeup. Entry updated in RS
and RoB
Cycle 6:
IF I9, I10, I11, I12 (Tag This will result in hit in BTAC, so branch will be considered
1) as taken.
ID I5, I6, I7, I8 (Tag 1)
Rename I3, I4 (Tag 1) Entry for this will be made into the PRF.
Dispatch I9, I10, I11, I12 Entry for this will be made into the RS as well as the RoB
Wakeup I8 Only I8 available for wakeup
Select I1, I2, I3 Only I1, I2, I3 can be selected because only two MEM units
available.
Cycle 7:
IF I3, I4 (Tag 2)
ID I9, I10, I11, I12 (Tag
1)
Rename I5, I6, I7, I8 (Tag 1) Entry for this will be made into the PRF.
Dispatch I3, I4 (Tag 1) Entry for this will be made into the RS as well as the RoB
Wakeup I9, I10 Only I9 and I10 available for wakeup
Select I4, I8 Only I1, I2, I3 can be selected because only two MEM units
available.
EX I1, I2, I3 I1 (1/1), I2(1/2), I3 (1/2)
Cycle 8:
IF I5, I6, I7, I8 (Tag 2)
ID I3, I4 (Tag 2)
Rename I9, I10, I11, I12 (Tag 1) Entry for this will be made into the PRF.
Dispatch I5, I6, I7, I8 (Tag 1) Entry for this will be made into the RS as well as the RoB
Wakeup No wakeup
Select I9, I10 I9 and I10
EX I4, I8, I2, I3 I2(2/2), I3 (2/2), I4 (1/2), I8 (1/1)
WB I1 PRF and RoB will be updated
Cycle 9
IF I9, I10, I11, I12 (Tag 2) This will result in hit in BTAC, so branch will be
considered as taken.
ID I5, I6, I7, I8 (Tag 2)
Rename I3, I4 (Tag 2) Entry for this will be made into the PRF.
Superscalar Example Page 8
Rename I3, I4 (Tag 2) Entry for this will be made into the PRF.
Dispatch I9, I10, I11, I12 (Tag 1) Entry for this will be made into the RS as well as the RoB
Wakeup I5, I11 (Tag 0), I3, I8 Only I5, I3, and I8 available for wakeup
(Tag 1)
Select No wakeup so no instruction can be selected here.
EX I4 (2/2), I9 (1/1), I10
(1/1)
WB I2, I3, I8 PRF and RoB Updated
Commit I1 Update AMT, PRF and RoB
Cycle 10
IF I3, I4 (Tag 3)
ID I9, I10, I11, I12 (Tag 2)
Rename I5, I6, I7, I8 (Tag 2) Entry for this will be made into the PRF.
Dispatch I3, I4 (Tag 2) Entry for this will be made into the RS as well as the
RoB
Wakeup I4, I9, I10 (Tag 1)
Select I5, I11 (Tag 0), I3, I8 (Tag All of I5, I11, I3, and I8 available for select
1)
EX No EX since no instruction selected.
WB I4, I9, I10 PRF and RoB Updated
Commit I2, I3 If commit width = 2. Update AMT, PRF (release) and
RoB
Cycle 11
IF I5, I6, I7, I8 (Tag 3)
ID I3, I4 (Tag 3)
Rename I9, I10, I11, I12 (Tag 2) Entry for this will be made into the PRF.
Dispatch I5, I6, I7, I8 (Tag 2) Entry for this will be made into the RS as well as the
RoB
Wakeup No wakeup
Select I4, I9, I10 (Tag 1) All EX units available
EX I5, I11 (Tag 0), I3, I8 (Tag I5 (1/3), I11(1/1), I3(1/2), I8 (1/1)
1)
WB No WB
Commit I4 Update AMT, PRF (release) and RoB
Cycle 12
IF I9, I10, I11, I12 (Tag 3) Cache hit in BTAC
ID I5, I6, I7, I8 (Tag 3)
Rename I3, I4 (Tag 3) Entry for this will be made into the PRF.
Dispatch I9, I10, I11, I12 (Tag 2) Entry for this will be made into the RS as well as
the RoB
Wakeup I12 (Tag 0), I11 (Tag 1), I3, I8
(Tag 2)
Select No select
Superscalar Example Page 9
EX I5 (Tag 0), I3, I4, I9, I10 (Tag 1) I5 (2/3), I3 (2/2), I4 (1/2), I9 (1/1), I10 (1/1)
WB I11 (Tag 0), I8 (Tag 1) PRF and RoB updated
Commit No commit
Cycle 13
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename No rename registers available
Dispatch I3, I4 (Tag 3) Entry for this will be made into the RS as well as
the RoB
Wakeup I5 (Tag 1), I4, I9, I10 (Tag 2)
Select I12 (Tag 0), I11 (Tag 1), I3, I8 EX units available for all
(Tag 2)
EX I5 (Tag 0), I4 (Tag 1) I5 (3/3), I4 (2/2)
WB I3, I9, I10 (Tag 1) PRF and RoB updated
Commit No commit
Cycle 14
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Renam No rename registers available
e
Dispatc No inst in rename in last cycle
h
Wakeu I6 (Tag 0)
p
Select I5 (Tag 1), I4, I9, I10 (Tag 2) EX units available for all
EX I12 (Tag 0), I11 (Tag 1), I3, I8 (Tag 2) I12 (1/1), I11 (1/1), I3 (1/2), I8 (1/1)
Also update PHT entry from 10 to 11 (ST) -
Prediction at Address 0x3CB in PHT updated.
Speculation for Tag 1 made 0 in RoB.
WB I5 (Tag 0), I4 (Tag 1) PRF and RoB updated
Commi No commit
t
Cycle 15
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename No rename registers available
Dispatch No inst in rename in last cycle
Wakeup I12 (Tag 1), I11 (Tag 2), I3 (Tag 3)
Select I6 (Tag 0) EX units available for all
EX I5 (Tag 1), I3, I4, I9, I10 (Tag 2) I5 (1/3), I3 (2/2), I4 (1/2), I9 (1/1), I10 (1/1)
WB I12 (Tag 0), I11 (Tag 1), I8 (Tag 2) PRF and RoB updated,
Commit I5 (Tag 0) Update AMT, PRF (release) and RoB
Doubt - Is Tag and Speculation decremented after Branch executed?
Superscalar Example Page 10
Doubt - Is Tag and Speculation decremented after Branch executed?
Cycle 16
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename Not enough rename registers available
Dispatch No inst in rename in last cycle
Wakeup I5 (Tag 2), I4 (Tag 3)
Select I12 (Tag 1), I11 (Tag 2), I3 (Tag 3) EX units available for all
EX I6 (Tag 0), I5 (Tag 1), I4 (Tag 2) I6 (1/1), I5 (2/3), I4 (2/2)
WB I3, I9, I10 (Tag 2) PRF and RoB updated,
Commit No commits
Cycle 17
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename Not enough rename registers available
Dispatch No inst in rename in last cycle
Wakeup I7 (Tag 0)
Select I5 (Tag 2), I4 (Tag 3) EX units available for all
EX I5, I12 (Tag 1), I11 (Tag 2), I3 (Tag 3) I5 (3/3), I12 (1/1), I11 (1/1), I3 (1/2) - PHT prediction will remain at 11.
WB I6 (Tag 0), I4 (Tag 2) PRF and RoB updated,
Commit No commits
Cycle 18
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename Not enough rename registers available
Dispatch No inst in rename in last cycle
Wakeup I6 (Tag 1), I12 (Tag 2)
Select I7 (Tag 0) EX units available for all
EX I5 (Tag 2), I3, I4 (Tag 3) I5 (1/3), I3 (2/2), I4 (1/2)
WB I5, I12 (Tag 1), I11 (Tag 2) PRF and RoB updated,
Commit I6 (Tag 0)
Cycle 19
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename Not enough rename registers available
Dispatch No inst in rename in last cycle
Wakeup No wakeup possible
Select I6 (Tag 1), I12 (Tag 2) EX units available for all
EX I7 (Tag 0), I5 (Tag 2), I4 (Tag 3) I7 (1/2), I5 (2/3), I4 (2/2)
WB I3 (Tag 3) PRF and RoB updated,
Commit
Superscalar Example Page 11
Commit
Cycle 20
IF I9, I10, I11, I12 (Tag 3) Stall
ID I5, I6, I7, I8 (Tag 3) Stall
Rename Not enough rename registers available
Dispatch No inst in rename in last cycle
Wakeup No wakeup possible
Select EX units available for all
EX I7 (Tag 0), I6 (Tag 1), I5, I12 (Tag 2) I7 (2/2), I6 (1/1), I12 (1/1), I5 (3/3),
WB I4 (Tag 3) PRF and RoB updated,
Commit
Superscalar Example Page 12