ADVANCED VERILOG (PART2)
ADVANCED VERILOG (PART 2)
CONTENT
Stratified event queue
Code coverage types
Pipeline coding examples
RAM modelling
Frequency division and
timing diagrams
Interview Questions
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Stratified event queue:
Verilog simulation uses a stratified event queue to manage event execution order in each
simulation time step. It ensures predictable simulation results and helps avoid race
conditions.
Queue Levels:
Active Events – Executes blocking assignments and procedural statements.
Inactive Events – Delayed events executed at the end of the current time slot (#0).
Non-Blocking Assign (NBA) – Executes non-blocking assignments after active events.
Monitor Events – Executes display/monitor tasks.
Reactive/Postponed – Executes tasks like $strobe and $finish.
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Ac ve
Inac ve
NBA
Monitor
Postponed
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Active:
Where:
Blocking assignments (=)
always @(...) triggers
if, case, procedural code
RHS of non-blocking assignments (<=)
Example:
Actual updates for blocking assignments happen here.
Simulation output:
Value of a =1, b = 0
Samples current RHS of a and b,
displays and then updates.
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Inactive:
Scheduled by:
#0 delay statements
Used for:
forcing order without advancing time
Example:
Executes after all current Active events.
Example 1: Ordering Two Assignments Without Changing Time
initial begin Execution Timeline (time = 0):
a = 1; // Active region Active Region: a=1 Final Value at time 0:
#0 a = 2; // Inactive Inactive Region: a = 2 a=2
region NBA Region: (none)
end
Note: Inactive region is used to force execution after active but in the same time unit.
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Example 2: Two Parallel Always Blocks Racing
reg a, b;
always @(posedge clk) begin
Timeline:
a = 5; // Active region
Active: a = 5
end
Inactive: b = a (b = 5)
always @(posedge clk) begin
#0 b = a; // Inactive region
end
Note:
If you removed #0, then:
The order of execution of the two always blocks is unknown
b might get old or the new value of a (race condition)
Using #0 guarantees reading the updated 'a'.
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NBA Region (Non-Blocking Assign):
Where:
<= updates propagate
Key Point:
LHS update of <= happens after the Active region finishes.
Allows sequential logic to behave predictably.
Example:
always @(posedge clk)
begin
a <= b; // old b
b <= a; // old a
end
This is why registers update simultaneously.
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Simulation output:
Value of a =101
Value of a =000
Value of a =111
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Monitor Region:
Contains:
$monitor
$strobe
$display (after all updates)
Used for:
These tasks observe the final stable value of signals after all Active, Inactive, and NBA updates
have completed.
Example:
Simulation output :
Value of a = x
All assignments to a are non-blocking, so they schedule updates in the NBA
Region, which executes after Active and Inactive regions.
Since $display executes in the Active Region, it prints the value of a before
the NBA update at time 0 occurs, resulting in the old or unknown value.
If $strobe or $monitor were used instead, they would execute in the Monitor
Region, printing the value after the NBA update.
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Applications:
Avoid race conditions and ensure predictable simulation behavior.
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Code coverage types:
Code coverage is the metric generated automatically from the design source in
RTL or gates.
While a high level of code coverage is required by most verification plans, it
does not necessarily indicate correctness of your design.
It only measures how often certain aspects of the source are exercised while
running a suite of tests.
Missing code coverage is usually an indication of one of two things either
unused code or holes in the tests.
Code coverage is tool-dependent.
It’s usually expressed in %.
Code Coverage Types:
Line Coverage:
Whether each line of code in RTL has executed at least once in simulation.
It does not check correctness—only whether the line ran.
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Note:
It answers the ques on:
“Was this line of RTL ever executed?”
Application:
1. Identify untested or unreachable lines.
2. Ensure no dead code remains.
3. Validate that testbench basic stimulus is working.
Example:
always @(posedge clk) begin
if (enable)
count <= count + 1;
else
count <= count - 1;
end
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Scenario:
If your test enabled only enable = 1, then the "else" line was never executed.
Advantages:
1. Simple to measure.
2. Quickly highlights unreachable code.
3. First metric to verify testbench completeness.
Branch Coverage:
Branch coverage checks whether all possible paths of a decision statement were executed.
Examples of decision points:
if / else
o It includes “true” branch and “False” branches.
o If else is missing, a hidden branch “All False” is added.
Case
o It includes case items as branches.
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unique case
priority case
for / while loopsApplication
Ensure that each logical path is validated.
Verify corner-case behavior.
Confirm safety-critical logic (e.g., FSM error handling).
Note:
It answers:
“Did we test all decision outcomes?”
Example:
Stimulus applied: Branch coverage:
if (mode == 0)
mode = 0 mode==0 → HIT
out = a;
mode = 1 mode==1 → HIT
else if (mode == 1)
else → NOT HIT
out = b;
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else
out = c;
Advantages:
Ensures coverage of alternative logic paths.
Helps catch untested decision outcomes.
Expression Coverage:
The metric for expression coverage is the count of activity of expressions on the
right-hand side of assignment statements.
Expressions not supported for vectors
Expression coverage analyzes:
o Complex Boolean expressions
o Ensures each sub-condition (operand) toggles to all possible values (0/1)
Note:
It answers:
“Did each operand in a Boolean expression toggle and influence the decision?”
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Example: Expression coverage:
assign y = ((a && b) || c); All combinations of a, b, and c
Application: Whether each operand affected
1. Safety-critical logic the outcome
2. Priority logic (like mux select signals)
3. Complex decision-making expressions
Toggle Coverage:
Toggle coverage is the ability to count and collect changes of state on
specified nodes.
Standard Toggle: 0 to 1 , 1 to 0
Extended Toggle: Covers 3 states “ 0, 1, z”.
Covers:
o Registers
o Wires
o Ports
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o Internal DUT signals
Note:
It answers:
“Did this net ever toggle?”
Example: Stimulus: Toggle coverage:
reg [2:0] addr; addr = 3’d0 → 3’d3 bit[0]: 0→1 HIT, 1→0 NOT HIT
bit[1]: toggled fully HIT
bit[2]: did NOT toggle
Outcome:
addr[2] is stuck-at, or testbench did not exercise upper addresses.
Advantages:
1. Detects stuck-at bits.
2. Helps verify full bus utilization.
3. Ensures correct stimulus spread across bit-width.
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Pipeline coding examples:
Pipelining is a digital design technique where a long operation is split into multiple smaller
stages, and each stage is executed in different clock cycles using registers between stages.
It is similar to an assembly line:
Stage 1 does first part
Stage 2 processes the output of stage 1
Stage 3 processes the output of stage 2 and so on
All stages work in parallel, each on a different piece of data.
Advantages:
1. Higher Clock Frequency (More Speed) - Because complex logic is divided into smaller
blocks, each stage has less delay → clock period becomes smaller → higher
performance.
2. Throughput - Even though each operation takes multiple cycles to finish, you get one
output every clock cycle once the pipeline is full.
3. Better Timing Closure - Smaller combinational logic per stage helps meet timing easily
especially in:
ASICs
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FPGA designs
High-speed datapaths
4. Allows Parallel Processing - Multiple inputs are processed simultaneously at different
stages.
5. Reduces Critical Path Delay - The longest logic path is shortened → improves speed and
robustness.
Applications:
1. DSP (Digital Signal Processing) - Filters, multipliers, FFTs, FIR, IIR
2. CPU Microarchitecture - Instruction execution pipeline (Fetch → Decode → Execute →
Writeback)
3. Video & Image Processing - Pixel pipelines, convolution pipelines
4. Networking / Data Path - Routers, packet inspectors
5. High-Speed Arithmetic - MAC units, multipliers, adders
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RTL Code for Pipeline: Block Diagram:
module pipeline (input clk, reset
clk
input reset,
input [7:0] a,
Stage 1 Stage 2 Stage 3
input [7:0] b,
input [7:0] c, a
+ * y y
output reg [16:0] y b
); c c_r1 c_r2
// Stage 1 registers
reg [8:0] sum_r; // a+b
reg [7:0] c_r1; // pipeline c
// Stage 2 registers
reg [16:0] mult_r; // (a+b)*c (intermediate)
reg [7:0] c_r2;
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always @(posedge clk)
begin Waveform:
if (reset)
begin
sum_r <= 9'd0;
c_r1 <= 8'd0;
mult_r <= 17'd0;
c_r2 <= 8'd0;
y <= 17'd0;
end
else
begin
// Stage 1
sum_r <= a + b;
c_r1 <= c;
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// Stage 2
mult_r <= sum_r * c_r1;
c_r2 <= c_r1;
// Stage 3
y <= mult_r;
end
end
endmodule
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Lint Warnings:
Below Warnings has been Waived because those are intention in the design aspects:
EDA Link: [Link]
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RAM Modelling: Synchronous Dual-port RAM
Dual Port has two separate ports to perform write and read operations on the respective
address ports based on the input enable signal(write enable/read enable).
o we(write enable=1)---> write Operation
o re(read enable=1)---> read Operation
Block Diagram
clk
rst
we
din Dual Port RAM dout
waddr
re
raddr
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RTL Code for Synchronous Dual-Port RAM:
module sync_ram_16to8#(parameter depth=16, // Location size
parameter width=8, // Data Size
parameter addr_bus=4 // Address Size
) (input [width-1:0] din,
input clk,
input rst,
input [addr_bus-1:0] waddr,
input [addr_bus-1:0] raddr,
input we,
input re,
output reg [width-1:0]dout
);
reg [width-1:0] mem [depth-1:0]; // 2D Memeory
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integer i;
always@(posedge clk)
begin
if(rst)
begin
dout<=8'b0;
for(i=0;i<16;i=i+1)
mem[i]<=8'b0;
end
else
begin
if(we)
mem[waddr]<=din;
else
mem[waddr]<=mem[waddr];
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if(re)
dout<=mem[raddr];
else
dout<=dout;
end
end
endmodule
Lint Warnings:
Below Warnings has been Waived because those are intention in the design aspects:
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Waveform:
EDA Link: [Link]
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Frequency division and timing diagrams:
A Frequency Divider is a digital or analog circuit that reduces the frequency of an input
clock signal by an integer or fractional factor.
If the input clock is f_in, and you divide by N, the output clock becomes:
𝒊𝒏
𝒐𝒖𝒕
Applications:
1. Clock Generation in Digital Systems - Generating slow clocks from fast system clocks.
2. PLL Feedback Path - In PLLs, a frequency divider provides feedback to match VCO
frequency with reference.
3. Watchdog / Timer Circuits - Very slow clocks (Hz range) are produced from MHz clocks.
4. Frequency Scaling for Power Saving - Dynamic Frequency Scaling uses dividers to
reduce CPU frequency to save power.
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RTL Code Frequency Divided by 7(Odd number) 50% duty cycle:
module freq_divider(input clk, Circuit:
input rst,
output out
);
reg [2:0] q;
reg q1;
always@(posedge clk)
begin
if(rst)
q <= 3'b0;
else if( q == 3'd6)
q <= 3'b0;
else
q <= q + 3'b1;
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end
always@(negedge clk) Waveform:
begin
if(rst)
q1 <= 1'b0;
else
q1 <= q[2];
end
assign out = q[2] | q1;
endmodule
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Lint Warnings:
Below Warnings has been Waived because those are intention in the design aspects:
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RTL Code Frequency Divided by 10(Even number) 50% duty cycle:
module freq_divider(input clk,
input rst, Circuit:
output out
);
reg [3:0] q;
reg q1;
always@(posedge clk)
begin
if(rst)
q <= 4'b0;
else if( q == 4'd9)
q <= 4'b0;
else
q <= q + 4'b1;
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end Waveform:
always@(posedge clk)
begin
if(rst)
q1 <= 1'b0;
else
q1 <= q[2];
end
assign out = q[2] | q1;
endmodule
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Lint Warnings:
Below Warnings has been Waived because those are intention in the design aspects:
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RTL Code Frequency Divided by 3.5(Odd fractional integer number) 40% duty cycle:
module freq_divider(input clk,
input rst, Circuit:
output out
);
reg [6:0] q;
reg q3n,q6n;
wire w3,w6;
always@(posedge clk)
begin
if(rst)
q <= 7'b1000000;
else if(q == 7'b0000001)
q <= 7'b1000000;
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else
q <= q >>1; Waveform:
end
always@(negedge clk)
begin
if(rst)
begin
q6n <= 1'b0;
q3n <= 1'b0;
end
else
begin
q6n <= q[6];
q3n <= q[3];
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end
end
assign w6 = q[6] | q6n;
assign w3 = q[2] | q3n;
assign out = w6 | w3;
Lint Warnings:
Below Warnings has been Waived because those are intention in the design aspects:
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EDA Link: [Link]
Pearl Script(makefile):
#.ONESHELL:
.PHONY : all
all : compile simulation clean rpt_clean lint
#all : clean rpt_clean
RPT_DIR := Freqdiv
compile :
irun -sv -access +rwc -f filelist.f
simulation :
simvision &
svn_update:
svn up ../../../
svn_info:svn_update
svn info ../../../
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clean :
rm -rf fv jgproject genus.* --force
rpt_clean :clean
rm -rf ../${RPT_DIR}_cdc/${RPT_DIR}_cdc_report \
../freqdiv_lint/freqdiv_lint_report \
--force
lint :
jg -superlint /home/navaneethan/RTL_Content/Freqdiv/[Link] &
Interview Questions:
[Link] are the different regions in Verilog’s stratified event queue?
[Link] is the purpose of the Inactive Region? Why do designers use #0?
[Link] is expression coverage important for safety-critical logic?
[Link] is toggle coverage important for CDC and low-power design?
[Link] does toggle coverage help detect stuck-at faults?
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[Link] does pipelining improve maximum clock frequency?
[Link] happens if one stage produces data faster than the next stage consumes it?
[Link] happens when read and write occur at the same address simultaneously?
[Link] do you ensure glitch-free clock division?
[Link] must frequency dividers avoid combinational logic loops in clock path?
Learnings:
[Link] follows a strict event execution order for deterministic simulation.
[Link] coverage reveals which RTL portions were actually exercised.
[Link] reduces combinational delay and increases performance.
[Link]-port RAM allows simultaneous read/write operations.
[Link] dividers often sit in power-critical paths → must be glitch-free.
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