Module III

Instruction Set Architecture and CPU

Organization
Instruction set architecture

• Instruction set architecture serves as an interface between the software and the
hardware.

•Typically consists of information regarding programmer’s view of the

architectures, that is, the registers, address and data buses, etc. and it also consists
of the instruction set.

Many ISA’s are not specific to a particular computer architecture

They survive across generations

Classic examples: IBM 360 series, Intel *86 series etc.
Instruction Set Design Issues

a) Number of Explicit Operands

- 0 operand → Stack-based (ADD)
- 1 operand → Accumulator-based (ADD R1)
- 2 operands → ADD R1, R2
-3 operands → ADD R1, R2, R3

b) Location of Operands
- Example: ADD R1, LOC A
-Operands may be in registers or memory.

c) Addressing Modes
- Register
- Immediate
- Direct
- Indirect
d) Size of Operands
- Byte (8-bit)
- Half word (16-bit)
- Word (32-bit)
-Double word (64-bit)

e) Supported Operations
- ADD, SUB, MUL, AND, OR, JMP etc.
Evolution of Instruction Set

a) Accumulator-Based (1960s)
Example: ADD X → ACC = ACC + Mem[X]

b) Stack-Based (1960–70)
- 0-address instructions
ADD → TOS = TOS + NEXT

c) Memory-Memory Based (1970–80)

- 2 or 3 address instructions
ADD A, B → Mem[A] = Mem[A] + Mem[B]
ADD A, B, C → Mem[A] = Mem[B] + Mem[C]

d) Register-Memory Based (1970–present)

Example: LOAD R1, X → R1 = Mem[X]

e) Register-Register Based
Example: ADD R1, R2, R3 → R1 = R2 + R3
 General-Purpose Registers

•Older architectures have large number of special-purpose register like we

talked about program counter, stack pointer, some index register, flag registers,
accumulator, etc.
•But in newer architectures we have more number of general-purpose registers.
And instead of using special purpose registers, most of the operations are
performed using general purpose registers.

And why that is so?

The compiler can assign some variables to registers.

There are so many variables that can be used and they can be assigned it to
registers, and registers are much faster than memory.
Once can load the data into the registers and can perform the operation
within the register it will be much faster.
But first have to load the data from your memory to register and then only
can perform the operation within register.
Instruction Formats

Instruction format defines how instructions are represented in a computer’s

memory. There are different types of instruction formats, including zero, one,
two, and three-address instructions.

Opcode: This field specifies the operation to be performed by the CPU, such as
addition, subtraction, or data transfer.

Operands: These fields contain the data or references (addresses) to data on

which the operation acts.

Addressing Mode: This specifies how to interpret or locate the operand, such as
direct, indirect, or immediate addressing.
Types of Instruction Formats

Zero Address Instructions

These instructions do not specify any operands or addresses. Instead, they
operate on data stored in registers or memory locations implicitly defined by
the instruction. For example, a zero-address instruction might simply add the
contents of two registers together without specifying the register names.
Two Address Instructions

These instructions specify two operands or addresses, which may be memory

locations or registers. The instruction operates on the contents of both
operands, and the result may be stored in the same or a different location. For
example, a two-address instruction might add the contents of two registers
together and store the result in one of the registers.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location
One Address Instructions

These instructions specify one operand or address, which typically refers to

a memory location or register. The instruction operates on the contents of
that operand, and the result may be stored in the same or a different
location. For example, a one-address instruction might load the contents of
a memory location into a register.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location
Three Address Instructions

These instructions specify three operands or addresses, which may be memory

locations or registers. The instruction operates on the contents of all three
operands, and the result may be stored in the same or a different location. For
example, a three-address instruction might multiply the contents of two
registers together and add the contents of a third register, storing the result in a
fourth register.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location
CPU Organization and Instruction Formats
Generally, CPU organization is of three types based on the number of address
fields:

Single Accumulator Organisation: Uses one special register (called an

accumulator) to store and process data for operations.

General Register Organisation: Uses several general-purpose registers to hold

operands (data) for operations.

Stack Organisation: Works with a stack, processing data using the top elements
without directly specifying operands.
Primary Types of Machine Instructions

1. Data Transfer Instructions :

Instructions that transfer data from one location (Register/Memory) to another

location (Register/Memory) without changing the data. Data transfer operations
supported are as follows :

LOAD : Data transfers from memory to register.

STORE : Data transfers from register to memory.
MOVE : Data transfers from register to register.
IN : Transfers data from input device to register.
OUT : Transfers data from register to output device.
PUSH : Gets data from register or memory on to the top of the stack.
POP : Gets data from Top of the stack to memory or register.
XCHG : Exchanges the data between memory and registers.
2. Data Manipulation Instructions :

a. Arithmetic Instructions :
Performs an arithmetic operation such as addition, subtraction, multiplication,
division, increment, decrement etc.
Example : ADD, SUB, MUL, DIV, INC, DEC etc.

b. Logical Instructions :
Performs bit-wise logical operation such as AND, OR, Exclusive-OR, NOT, shift,
rotate etc.
Example : AND, OR, NOT, XOR, SHL, SHR, ROL, ROR etc.

c. Arithmetic and Logical Instructions :

Performs operations such as arithmetic shift left, arithmetic shift right.
Example : SAL, SAR etc.
3. Program Control Instructions :

Carry flag (C) : It indicates a carry from an addition and borrow from a
subtraction
Overflow flag (V) : CPU sets 'V' flag to a logic '1' when the result of an
operation is beyond of the range that can be represented.
Negative Flag (N) : It is also called as Sign flag. Indicates that whether previous
result is negative or positive.
Half Carry (H) : Used only for BCD (Binary Coded Decimal) operations.
Zero Flag (Z) : Z bit is set to a logic '1' when the result is '0' otherwise Z=0. Note
that zero is a positive number
Register Transfer Language (RTL)

Register Transfer Language (RTL) is a design abstraction used to describe the

behavior and structure of digital circuits, specifically focusing on the transfer of
data between registers and the operations performed on that data—such as
addition, subtraction, shifting, and logical operations.
It defines how data moves from one register to another and how it is processed
within a digital system.
RTL enables a high-level representation of circuit behavior, linking algorithmic
design with low-level hardware implementation for purposes such as simulation,
synthesis, and verification.
It is primarily applied to the representation of synchronous circuits, which are
controlled by clock signals.
RTL designs are typically captured using hardware description languages (HDLs)
such as Verilog or VHDL.
General Register Organization
The CPU bus system is managed by the control unit. The control unit explicit the
data flow through the ALU by choosing the function of the ALU and components
of the system.

Consider R1 ← R2 + R3, the following are the functions implemented within the
CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.
ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).
Decoder Destination Selector (SELD) − It can transfers the result into R1.

The multiplexers of 3-state gates are performed with the buses. The state of 14
binary selection inputs determines the control word. The 14-bit control word
defines a micro-operation.
The encoding of register selection fields is specified in the table.
Encoding of Register Selection Field

Binary Code SELA SELB SELD

000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
Encoding of ALU Operations

OPR Select Operation Symbol

00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 ADD A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Memory Reference Instructions

Types:

1. Memory Reference Instructions:

Opcode = 000 to 110

2. Register Reference Instructions:

Opcode = 111 and I = 0

3. I/O Reference Instructions:

Opcode = 111 and I = 1
Basic Computer Registers Common Bus System
Three control lines S2, S1, S0 select the register for
Registers: bus input.
- IR (Instruction Register): 16-
Selection Table:
bit
S2 S1 S0 -> Register
- DR (Data Register): 16-bit 000 -> None
- TR (Temporary Register): 16- 001 -> AR
bit 010 -> PC
- INPR / OUTR: 8-bit 011 -> DR
- AR (Address Register): 12-bit 100 -> AC
- PC (Program Counter): 12-bit 101 -> IR
(holds address of next 110 -> TR
111 -> Memory
instruction)
Registers involved:
- AC (Accumulator)
- General Purpose Registers
Control Unit

Control Unit (CU):

- Translates machine instructions into control signals.
- Controls micro-operations.

Types of Control Units:

1. Hardware Control:
- Uses sequential and combinational circuits.
- Generates control signals directly.

2. Microprogrammed Control:
- Uses control memory.
- Stores microprograms to generate control signals.
Timing and Control

Fig. 5-7 Example of control timing signals

Instruction Cycle

Fig. Register transfers for the fetch phase

Fig. Register transfers for the fetch phase
Data Path

The Data Path consists of all hardware elements involved in data processing,
including ALU, registers, and buses. It executes instructions by moving and
transforming data based on control signals. Implements the actual operations of
the CPU. Works with the control unit to execute instructions in steps.

One Bus Organization

•In a one-bus organization, a single bus

is used for all data transfers among CPU
components, including registers and the
ALU.
•his design is simple and cost-effective
but can lead to slower execution due to
sequential operations.
•Only one data movement can occur at a
time.
•Requires temporary registers for
intermediate values during ALU
operations.