Overview & Motivation

What is Time Division Switching (TDS)? — A technique where a single switching element is shared
by multiple speech circuits in a time-multiplexed fashion.
In space division switching, one crosspoint is dedicated to one circuit for its entire duration. TDS
removes this limitation.
Key Principle: With 8 kHz sampling, a speech sample occurs every 125 μs. Passing one sample
through a switching element takes only a few microseconds — leaving the element idle for ~120 μs.
TDS exploits this idle time.
📌 Note: If t_s = 2 μs per sample transfer, switching capacity SC = 125 / 2 = 62.5 ≈ 62 simultaneous
circuits from one element!
Two forms of TDS:
• Time Division Space Switching (TDSS) — uses a shared bus; physical connection exists
momentarily
• Time Division Time Switching (TDTS) — uses a data memory block; no physical connection;
information is stored and delayed

6.1 Basic Time Division Space Switching (TDSS)

6.1.1 What Is It?
An N × N switch where N inlets and N outlets are interconnected by a single shared bus. See Figure
6.1(a) for the switching structure and Figure 6.1(b) for its two-stage equivalent (N×1 followed by 1×N
matrices).
Two signal types: PAM samples → Analog Time Division Space Switching. PCM binary words →
Digital Time Division Space Switching.

6.1.2 What Does It Do?

Connects any inlet to any outlet by placing them on the shared bus for the duration of one sample
transfer. Multiple inlet-outlet pairs share the bus across the 125 μs frame.

6.1.3 Key Formula — Switching Capacity

SC = number of simultaneous conversations the switch can support:
SC = 125 / t_s ...... (6.1)
where t_s = time (μs) to set up a connection and transfer one sample.
📝 Example — SC calculation: If t_s = 1 μs: SC = 125 / 1 = 125 circuits. If t_s = 5 μs: SC = 125 / 5 =
25 circuits.

6.1.4 Control Mechanisms

Inlet/outlet selection can be organized in three ways:
• Cyclic Control (no memory) — inlets and outlets scanned in sync (1,2,...,N,1,2,...). Fixed 1-to-1
mapping, no true switching, nonblocking but not fully available.
 • Input-Controlled (memory on output side) — inlet side cyclic; outlet addresses stored in control
memory. See Figure 6.2. Inlet i is connected to whichever outlet address is in location i of the
CM.
• Output-Controlled (memory on input side) — outlet side cyclic; inlet addresses stored in CM.
See Figure 6.3. Supports broadcast (one inlet → all outlets).
📌 Note: Output-controlled switches support broadcast connections; input-controlled ones do NOT.

6.1.5 Control Memory Organization (Input/Output Controlled)

Control memory (CM) has N words, each ⌈log₂ N⌉ bits wide:
k = ⌈log₂ N⌉ ...... (6.1a)
The modulo-N counter acts as the Memory Address Register (MAR). Clock rate = 8N kHz so that all N
samples are transferred in 125 μs:
Clock rate = 8N kHz ...... (6.3)

6.1.6 General Formula for N (Input/Output Controlled)

N (= SC) accounts for all timing components:
N = SC = 125 / (t_i + t_m + t_d + t_t) ...... (6.2)
t_i = time to increment modulo-N counter t_m = time to read control memory t_d = time to
decode address and select inlet/outlet t_t = time to transfer sample from inlet to outlet All in
microseconds.
📝 Example — N calculation: If t_i = 0.2, t_m = 0.5, t_d = 0.3, t_t = 0.5 μs: t_s = 1.5 μs → N = SC =
125/1.5 ≈ 83 circuits.

6.1.7 Generalised (Memory-Controlled) Switch

When both input and output are memory-controlled, the switch is called a memory-controlled time
division space switch (Figure 6.4).
• Each CM word holds TWO addresses: inlet address + outlet address
• CM width = 2⌈log₂ N⌉ bits
• Modulo-SC counter (not modulo-N) drives the MAR
• SC and clock rate:
SC = 125 / t_s, Clock rate = 8·SC kHz ...... (6.4)
SC and N are now decoupled — more subscribers than SC can be served (N >> SC). This is more
general and versatile.

6.1.8 Cost Comparison — TDSS vs. Space Division

For a nonfolded TDSS network:
Parameter Value
Switching elements (input side) N
Switching elements (output side) N
Total switching elements 2N
Switching capacity SC N
 Traffic handling capacity TC 1
Cost of network 2N + N = 3N (elements + CM)
Cost-Capacity Index (CCI = SC/Cost) N / 3N = 1/3 ≈ 0.33
CCI for equivalent space-division switch 0.5 (fixed, regardless of N)

📌 Note: CCI for TDSS = 1/3 < 0.5 (space division). Wait — higher CCI is better. TDSS CCI grows
with memory efficiency; time division networks are more cost-effective at scale.

6.2 Basic Time Division Time Switching (TDTS)

6.2.1 What Is It?
A memory-block-based switch where incoming PCM data is written into a Data Memory (DM), held
briefly, then read out to the appropriate outlet — introducing a controlled time delay. See Figure 6.5(a)
for the switching structure and Figure 6.5(b) for its equivalent circuit (N×1 → Delay → 1×N).
📌 Note: There is NO physical connection between inlet and outlet, even momentarily. This is the key
difference from TDSS.

6.2.2 What Does It Do?

Transfers a PCM sample from inlet i to outlet j by:
• Writing the sample into DM location i (or a location determined by control memory)
• Reading the sample from the appropriate DM location and sending it to outlet j
The switching is achieved entirely through memory read/write operations — hence called time
switching.

6.2.3 Three Control Modes

Control Mode Description
Sequential Write / Random Read Inlets scanned in order → written sequentially to
DM. CM holds outlet addresses; DM read
randomly for each outlet.
Random Write / Sequential Read CM read first → inlet data written to random DM
location. DM then read sequentially for outputs.
(Mirror of mode 1)
Random Input / Random Output Only active subscribers scanned. Two CMs (CM1,
CM2) hold active inlet and outlet addresses
respectively. Allows N >> SC. Switch is blocking.

6.2.4 Two Operational Modes

• Phased Operation — 125 μs split into 2 phases: Phase 1 (DM write) + Phase 2 (DM read).
Counter goes through 2 cycles.
• Slotted Operation — 125 μs split into N subperiods of 125/N μs each. In each subperiod i: (1)
Read inlet i → write DM[i]; (2) Read CM[i] = j; (3) Read DM[j] → send to outlet i. Counter goes
through 1 cycle.
6.2.5 Mathematical Formulas
Phased Operation (Sequential Write / Random Read):
Time for two-phase operation:
t_s = N·t_d + N·(t_d + t_c) ...... (6.5)
If t_d = t_c = t_m:
t_s = 3N·t_m ...... (6.6)
Number of subscribers:
N = 125 / (3·t_m) ...... (6.7)
📝 Example — N from t_m: If t_m = 0.5 μs: N = 125 / (3 × 0.5) = 125 / 1.5 ≈ 83 subscribers.

Overlapped Phased Operation (Figure 6.6a):

By overlapping DM and CM reads in Phase 2:
N = 125 / (2·t_m) ...... (6.8)
📝 Example — Overlapped: If t_m = 0.5 μs: N = 125 / (2 × 0.5) = 125 subscribers — a 50%
improvement over non-overlapped.
📌 Note: Slotted operation (Figure 6.6b) also satisfies Eq. (6.8) since the two operations within each
subperiod are simultaneous.
Random Input / Random Output (Figure 6.8):
Two memory read/write per phase → 4 memory accesses total:
SC = 125 / (4·t_m) ...... (6.9)
With overlapping of CM and DM operations:
SC = 125 / (2·t_m) ...... (6.10)
With dual-port memories (simultaneous read+write):
SC = 125 / t_m ...... (6.11)
📌 Note: Dual-port memories introduce 1 sample delay (output corresponds to previous 125 μs cycle).
📝 Example — Dual-port SC: If t_m = 0.25 μs: SC = 125 / 0.25 = 500 simultaneous conversations
from one switch.

6.2.6 Control Memory Management (Random I/O)

Three strategies to manage CM entries:
Strategy Description & Formula
Free List only Linked list of free CM locations. All SC locations
scanned every cycle (including null/empty ones).
Time: T = 4s₁t_m + 2(SC − s₁)t_m ...(6.12)
Free List + Occupied List Only occupied locations scanned. Time: T =
4s₁t_m ...(6.13)
Compaction Active entries compacted to front of CM on each
call termination. Access stops at first null. Time: T
= 4s₁t_m + 2t_m ...(6.14)
In all formulas, s₁ = number of active subscriber pairs.
Figures Reference Summary
Figure Description
Figure 6.1 Simple PAM time division space switching — (a)
N×N switching structure with shared bus; (b) two-
stage equivalent (N×1 and 1×N matrices).
Figure 6.2 Input-controlled TDSS — output side has control
memory; modulo-N counter-cum-MAR drives
selection; inlet side is cyclic.
Figure 6.3 Output-controlled TDSS — input cyclic; control
memory on input side stores inlet addresses per
outlet slot.
Figure 6.4 Generalised (memory-controlled) TDSS — both
inlets and outlets selected via CM; modulo-SC
counter; CM word = 2⌈log₂N⌉ bits.
Figure 6.5 Basic TDTS — (a) DM (N words × 8 bits) with
MAR, CM, S/P and P/S converters; (b) equivalent
circuit with delay block.
Figure 6.6 Two operational modes — (a) Overlapped
DM/CM reads in Phase 2; (b) Slotted:
simultaneous DM write + CM read in each slot.
Figure 6.7 Random write/sequential read — overlapping DM
write and CM read across 125 μs cycle.
Figure 6.8 Random input/random output switch — CM1
holds active inlet addresses, CM2 holds active
outlet addresses; DM has SC words.