Nanoelectronics
Module 3
Strained Si Devices
• Strained silicon technology enhances transistor performance by
deliberately modifying the silicon crystal lattice structure.
• Mechanical strain is introduced to improve carrier mobility without
reducing device dimensions.
• This technique became essential as conventional scaling began facing
mobility degradation issues.
• Strained Si is widely adopted in advanced CMOS technologies below
90 nm.
Need for Strain Engineering
• As channel lengths shrink, carrier scattering increases, reducing
mobility.
• Traditional scaling improves speed but increases leakage and short-
channel effects.
• Strain engineering enhances drive current without aggressive
geometric scaling.
• It provides performance improvement while maintaining
compatibility with existing CMOS processes.
Tensile Strain (nMOS Enhancement)
• Tensile strain stretches the silicon lattice, increasing the spacing
between atoms.
• This reduces electron effective mass and enhances electron mobility.
• Conduction band valley splitting occurs, allowing electrons to occupy
lower energy states.
• As a result, nMOS devices exhibit higher drive current and improved
switching speed.
Compressive Strain (pMOS Enhancement)
• Compressive strain squeezes the silicon lattice structure.
• This modifies the valence band structure, improving hole mobility.
• Band splitting reduces hole scattering and enhances current
conduction.
• Compressive strain is particularly effective for improving pMOS
transistor performance.
•
Methods to Introduce Strain
• Strain can be introduced using silicon-germanium
(SiGe) substrates.
• Embedded SiGe in source/drain regions induces
compressive stress.
• Stress liners such as silicon nitride films are used
to apply tensile or compressive strain.
• Advanced process techniques allow localized
strain engineering in modern CMOS nodes.
• A SiGe (Silicon-Germanium) layer is first grown
on a silicon wafer.
• SiGe has a larger lattice constant than pure
silicon.
• When a thin silicon layer is grown on relaxed SiGe,
the silicon layer stretches to match the lattice.
• This creates biaxial tensile strain in the silicon
channel.
Effect on Band Structure
• Strain alters the energy band diagram by splitting conduction and
valence bands.
• Reduced band degeneracy leads to improved carrier transport.
• Lower effective mass results in higher mobility.
• These changes directly improve transistor transconductance and
current drive capability.
•
Advantages of Strained Silicon
• Improves carrier mobility without reducing gate length.
• Enhances device speed and switching performance.
• Maintains compatibility with existing fabrication infrastructure.
• Provides a cost-effective alternative to extreme scaling.
Applications
• Used in high-performance microprocessors and mobile processors.
• Integrated in advanced CMOS, FinFET, and nanosheet devices.
• Essential for achieving performance targets in sub-45 nm technology
nodes.
• Widely adopted in both high-speed and low-power VLSI circuits.
CARBON NANOTUBES (cnt)
• A Carbon Nanotube (CNT) is a cylindrical
nanostructure formed by rolling a single
layer of graphene into a seamless tube.
Graphene is a two-dimensional sheet of
carbon atoms arranged in a hexagonal
lattice.
• CNTs are considered one-dimensional (1D)
materials because electrons are confined in
two directions and can move freely only
along the tube axis. This quantum
confinement gives CNTs unique electrical
properties.
• Typical dimensions:
Diameter: ~0.4 nm to 3 nm (for SWCNT)
Length: Up to several micrometers
Aspect ratio: Very high (length ≫ diameter
Types of CNT
• 1. Single-Walled Carbon Nanotube (SWCNT)
• Consists of a single graphene cylinder.
• Used in electronic devices.
• Can be metallic or semiconducting.
• 2. Multi-Walled Carbon Nanotube (MWCNT)
• Consists of multiple concentric graphene cylinders.
• More mechanically robust.
• Less commonly used in transistor applications.
•
Chirality and Electrical Properties
• The electrical behavior of CNTs depends on the way graphene is
rolled, defined by the chiral vector (n, m).
• If (n − m) is divisible by 3 → Metallic CNT
• Otherwise → Semiconducting CNT
• Only semiconducting CNTs are used in CNTFETs.
•
CNTFET
• A CNTFET is a nano-scaled device that
can provide low-power integrated
circuits with high performance and high
power density.
• Instead of the bulk silicon material used
in traditional metal-oxide
semiconductor field-effect transistors
(MOSFETs), CNTFETs use carbon
nanotubes (CNTs) in between the
source and the drain of a MOSFET
structure. This enables higher current
carrier mobility, enabling CNTFETs to
provide a superior drive current density.
Types of CNTFET
• 1. Schottky Barrier CNTFET
• Metal contacts directly form junction with CNT.
• Current is controlled by Schottky barrier height.
• Operation depends on tunneling through barriers.
• 2. MOSFET-like CNTFET
• Source and drain are doped.
• Channel operates like inversion in MOSFET.
• Better ON/OFF ratio.
• Preferred for digital circuits.
•
Operation of CNTFET
• Principle of Operation
• The gate voltage controls the electrostatic potential of the CNT
channel.
• When:
• Gate voltage is low → Channel is OFF → No conduction
• Gate voltage exceeds threshold → Channel forms → Current flows
• Because CNT is 1D:
Carrier scattering is minimal.
Transport can be ballistic over short lengths.
• Ballistic Transport
• In conventional silicon: Carriers scatter due to phonons and impurities.
• In CNTs:
Channel length can be smaller than mean free path.
Electrons travel without scattering.
Current approaches theoretical maximum.
• This leads to: Ballistic transport is a mode of charge carrier movement in
which electrons travel through a channel without scattering
High switching speed from impurities, phonons, or lattice vibrations.
High drive current In simple terms:
Electrons move from source to drain like a bullet without
collisions.
• Band Structure Perspective
• Semiconducting CNT has a direct bandgap.
• Bandgap depends on diameter:
• Eg ≈ 0.8 / d (nm) eV
• Smaller diameter → Larger bandgap
Larger diameter → Smaller bandgap
• This tunability is a major advantage.
Contact Resistance in CNTFET
• Source and drain metals must inject carriers into the carbon
nanotube.
• The interface between metal and CNT is not always perfectly
conducting.
• A potential barrier may form at this junction.
• This resistance at the metal–CNT interface is called contact
resistance.
Why Contact Resistance Becomes Important
at Sub-5 nm
• At extreme scaling:
Channel length becomes very short.
Channel resistance becomes very small (especially due to ballistic
transport).
Now the contact resistance can become comparable to or even
larger than channel resistance.
This causes the current to be limited by poor carrier injection at the
contacts.
Why Contact Resistance Occurs in CNTFET?
• If metal work function is not aligned properly with CNT band
structure,
• A Schottky barrier forms at the interface.
• In Schottky Barrier CNTFET
• CNTFET:
• Current depends on tunneling through this barrier.
• Large barrier → poor injection → high resistance.
Structural / Material-Level Modifications to
Reduce Contact Resistance
Use Doped Source/Drain Regions (MOSFET-like CNTFET)
• Instead of relying purely on metal contact:
• Dope the CNT near source and drain.
• This reduces barrier height.
• Makes contact more Ohmic.
Select Proper Contact Metal
• Choose metal based on carrier type:
• High work-function metal → good for p-type CNT
• Low work-function metal → good for n-type CNT
• Proper alignment reduces barrier formation.
Use Parallel CNT Arrays
• Instead of a single CNT: Use multiple aligned semiconducting CNTs. Even if one contact has resistance:
Total effective resistance reduces.
Drive current increases.
Advantages of CNTFET
• High carrier mobility
• Near-ballistic transport
• High ON current (Ion)
• Low OFF current (Ioff)
• Excellent subthreshold slope
• Reduced short channel effects