MicroController Introduction

The 8051 Microcontroller is designed by Intel in 1981. 8051 is 40 pin DIP IC. This is an 8-bit
microcontroller.
It is a very famous Microcontroller of Intel family. As we know Microprocessor like 8085, Z-
80 or M6800 contains the ALU, control unit and some registers, but there were no internal
storages. The Microcontroller contains the RAM and ROM, IO ports inside it. Some
microcontroller also contains the ADC in it. As most of the required components are inside
the chip, so the cost of application is also reduced.
These kinds of microcontrollers are used in different appliances like televisions, washing
machines, telephones or some other electronic gadgets. The microcontroller is more complex
than microprocessors based on their architecture. The first generation Intel Microcontroller
was 8048. The 8051 is successor of that. So it is treated as the second generation
microcontroller. 8051 belongs to MCS-51 family of Intel Microcontrollers.

RISC and CISC are two different types of computer architectures that are used to design the
microprocessors that are found in computers. The fundamental difference between RISC and
CISC is that RISC (Reduced Instruction Set Computer) includes simple instructions and
takes one cycle, while the CISC (Complex Instruction Set Computer) includes complex
instructions and takes multiple cycles.
.
What is RISC?
In the RISC architecture, the instruction set of the computer system is simplified to reduce
the execution time. RISC architecture has a small set of instructions that generally includes
register-to-register operations.
The RISC architecture uses comparatively a simple instruction format that is easy to decode.
The instruction length can be fixed and aligned to word boundaries. RISC processors can
execute only one instruction per clock cycle.

The following are some important characteristics of a RISC Processor ?

• A RISC processor has a few instructions.
• RISC processor has a few addressing modes.
• In the RISC processor, all operations are performed within the registers of the CPU.
• RISC processor can be of fixed-length.
• RISC can be hardwired rather than micro-programmed control.
• RISC is used for single-cycle instruction execution.
• RISC processor has easily decodable instruction format.
RISC architectures are characterized by a small, simple instruction set and a highly efficient
execution pipeline. This allows RISC processors to execute instructions quickly, but it also
means that they can only perform a limited number of tasks.

What is CISC?
The CISC architecture comprises a complex instruction set. A CISC processor has a
variable-length instruction format. In this processor architecture, the instructions that require
register operands can take only two bytes.
In a CISC processor architecture, the instructions which require two memory addresses can
take five bytes to comprise the complete instruction code. Therefore, in a CISC processor, the
execution of instructions may take a varying number of clock cycles. The CISC processor
also provides direct manipulation of operands that are stored in the memory.
The primary objective of the CISC processor architecture is to support a single machine
instruction for each statement that is written in a high-level programming language.
The following are the important characteristics of a CISC processor architecture ?
• CISC can have variable-length instruction formats.
• It supports a set of a large number of instructions, typically from 100 to 250
instructions.
• It has a large variety of addressing modes, typically from 5 to 20 different modes.
• CISC has some instructions which perform specialized tasks and are used
infrequently.
CISC architectures have a large, complex instruction set and a less efficient execution
pipeline. This allows CISC processors to perform a wider range of tasks, but they are not as
fast as RISC processors when executing instructions.
Difference between RISC and CISC
The following table highlights all the important differences between RISC and CISC
architectures ?
[Link]. RISC CISC

It stands for Reduced Instruction Set

1. It stands for Complex Instruction Set Computer.
Computer.

It is a microprocessor architecture that

This offers hundreds of instructions of different
2. uses small instruction set of uniform
sizes to the users.
length.

This architecture has a set of special purpose

These simple instructions are executed in
3. circuits which help execute the instructions at a
one clock cycle.
high speed.

These chips are relatively simple to

4. These chips are complex to design.
design.

5. They are inexpensive. They are relatively expensive.

Examples of RISC chips include SPARC, Examples of CISC include Intel architecture,
6.
POWER PC. AMD.

7. It has less number of instructions. It has more number of instructions.

It has fixed-length encodings for

8. It has variable-length encodings of instructions.
instructions.

The instructions interact with memory using

9. Simple addressing formats are supported.
complex addressing modes.

It has a large number of instructions. It supports

10. It doesn't support arrays.
arrays.

11. It doesn't use condition codes. Condition codes are used.

Registers are used for procedure The stack is used for procedure arguments and
12.
arguments and return addresses. return addresses.
The most significant difference between RISC and CISC architectures is the size and
complexity of the instruction set. RISC is a microprocessor architecture that uses a small
instruction set of uniform length that allows fast execution, while the CISC architecture is
one that offers hundreds of instructions of different sizes that allows the users to perform a
wider range of tasks.

Difference between Von Neumann and Harvard Architecture

There are two distinct varieties of digital computer architectures, each of which provides a
description of the functioning and execution of computer systems
• The first is known as the Von Neumann Architecture, which was designed by the
well-known physicist and mathematician John Von Neumann in the late 1940s.
• The second is known as the Harvard Architecture, which was based on the original
Harvard Mark relay-based computer and used separate memory systems to store data
and instructions. Both of these computer architectures were developed in the 1950s.
In the original Harvard architecture, data and instructions were both stored in electro-
mechanical counters, while the instructions were punched into tape. Modern computing is
predicated on the Von Neumann architecture, which also has the advantage of being simpler
to put into practise.
This article takes a detailed look at both of these computer architectures and highlights the
points that differentiate them.
What is Von Neumann Architecture?
This is a hypothetical architecture that is derived from the idea of stored-program computers,
in which the memory is used for storing both the program data and the instruction data.
• Prior to the introduction of the Von Neumann idea of computer design, computing
machines were developed for a single predetermined function, and their level of
sophistication was limited as a result of the need for human rewiring of the circuitry.
• The ability to keep instructions in the memory along with the data that the instructions
operate on is the central tenet of the Von Neumann architectures.
• In a nutshell, when people talk about the Von Neumann architecture, they are
referring to an overarching structure that the hardware, programming, and data of a
computer should adhere to
Components of Von Neumann Architecture
There are three major components that make up the Von Neumann architecture. These
components are the CPU, the memory unit, and the I/O interfaces.
• The control unit (CU), the Arithmetic and Logic Unit (ALU), and the registers make
up the other two main parts of the CPU, which serves as the beating heart of the
computer system.
• The arithmetic and logic operations on data are the responsibility of the ALU,
whereas the control unit is responsible for determining the order of flow of
instructions that need to be executed in programs by issuing control signals to the
hardware. The ALU is responsible for carrying out all of these operations.
• The registers are essentially short-term storage sites that are used to hold the
addresses of the instructions that have to be carried out. RAM, or Random Access
Memory, is the primary memory that is used to store program data and instructions.
The memory unit consists of AM. Users are given the ability to communicate with the
outside world, such as storage devices, by means of the I/O interfaces.
What is Harvard Architecture?
It is a type of computer architecture that keeps programme data and instructions in storage
and signal channels that are physically independent from one another.
• In contrast to the Von Neumann design, which retrieves instructions from memory
using a single bus while simultaneously moving data from one component of a
computer to another, the Harvard architecture keeps data and instructions in their own
distinct memory spaces.
• Both ideas are comparable, with the exception of the means through which they
access memory. The Harvard architecture is based on the concept of separating the
memory into two distinct sections, with one section dedicated to storing data and the
other to storing programmes. The concept was derived from the first Harvard Mark
relay-based computer, which used a technology that enabled simultaneous execution
of data transfers, instruction fetches, and both types of data transfers. The word was
named after this machine.
• Real-world computer designs are really based on a modified version of the Harvard
architecture, which is frequently utilised in digital signal processors and
microcontrollers (Digital Signal Processing).

Difference between Von Neumann and Harvard Architecture

Von Neumann and Harvard architectures are the two basic models in the field of computer
architecture, explaining the organization of memory and processing units in a computer
system. For those involved in Computer Science or working in companies providing
computing technologies, it is essential to understand the characteristics of these architectures.
There are two models of multiprocessing architectures: Von Neumann and Harvard. While
the former occupies a dominant position. From the its principal differences from the latter,
along with their respective advantages and disadvantages, we can understand which
architecture is more suitable for a given application.
Von Neumann Architecture
Von Neumann Architecture is a digital computer architecture whose design is based on the
concept of stored program computers where program data and instruction data are stored in
the same memory. This architecture was designed by the famous mathematician and
physicist John Von Neumann in 1945.
Advantages of Von Neumann Architecture
• Simplicity: The fact that all data and instructions are stored in a single memory space
helps the process of designing a computer system as there is no need to create
complicated systems of routing since pathways may coincide.
• Cost-Effective: A smaller number of components is needed as compared to the other
architectural designs hence more economical.
• Flexibility: A program can Always be changed or altered without experiencing a
change in some underlying physical aspects such as the circuitry.
Disadvantages of Von Neumann Architecture
• Bottleneck Issues: The shared bus can be a problem because the data and control
instructions cannot be obtained simultaneously and therefore it becomes slow.
• Memory Corruption: Since the data and instructions reside in the same memory,
then there is a temptation of one erasing the other thereby producing system faults.
Harvard Architecture
Harvard Architecture is the digital computer architecture whose design is based on the
concept where there are separate storage and separate buses (signal path) for instruction and
data. It was basically developed to overcome the bottleneck of Von Neumann Architecture.
Features
• Separate memory spaces
• Fixed instruction length
• Parallel instruction and data access
• More efficient memory usage
• Suitable for embedded systems
• Limited flexibility
Advantages of Harvard Architecture
• Faster Processing: The availability of two buses for data and instructions avoids a
problem of contention where only one bus is used and this enhances the velocity of
the system.
• Improved Security: In this way the chance of memory corruption is at least cut in
half since data is not stored in the same locations as instructions.
• Efficient Use of Resources: It enables the use of different memory for data and for
instructions of different sizes as this help in optimal utilization of the buses and other
resources.
Disadvantages of Harvard Architecture
• Complexity: The design and the implementation of this type are more intricate, thus
necessitating other hardware facilities.
• Higher Cost: Since the concept of Harvard architecture calls for two sets of memory
and two separate buses, their implementation costs are comparatively high than Von
Neumann architecture.
• Less Flexibility Competitors : Changing or even improving the system can also be a
little tricky because of the different memory regions.

The Von Neumann and Harvard architectures are fundamental concepts in computer
organization, each with distinct memory and processor setups.

Difference between Von Neumann and Harvard Architecture

VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE

It is ancient computer architecture based It is modern computer architecture based on

on stored program computer concept. Harvard Mark I relay based model.

Same physical memory address is used for Separate physical memory address is used
instructions and data. for instructions and data.

There is common bus for data and Separate buses are used for transferring data
instruction transfer. and instruction.

Two clock cycles are required to execute

An instruction is executed in a single cycle.
single instruction.
VON NEUMANN ARCHITECTURE HARVARD ARCHITECTURE

It is cheaper in cost. It is costly than Von Neumann Architecture.

CPU can not access instructions and CPU can access instructions and read/write
read/write at the same time. at the same time.

It is used in personal computers and small It is used in micro controllers and signal
computers. processing.

8051 Microcontroller architecture

• 8051 microcontroller is designed by Intel in 1981.
• It is an 8-bit microcontroller.
• It is built with 40 pins DIP (dual inline package),
• 4kb of ROM storage and 128 bytes of RAM storage,
• 2 16-bit timers.
• It consists of are four parallel 8-bit ports, which are programmable as well as
addressable as per the requirement.

An on-chip crystal oscillator is integrated in the microcontroller having crystal frequency of

12 MHz. In lab we will be using 11.0592MHZ

Let us now discuss the architecture of 8051 Microcontroller.

In the following diagram, the system bus connects all the support devices to the CPU.
The system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals.
All other devices like program memory, ports, data memory, serial interface, interrupt
control, timers, and the CPU are all interfaced together through the system bus.
The pin diagram of 8051 microcontroller looks as follows −
 • Pins 1 to 8 − These pins are known as Port 1. This port doesnt serve any other
functions. It is internally pulled up, bi-directional I/O port.
• Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial
values.
• Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like
interrupts, timer input, control signals, serial communication signals RxD and TxD,
etc.
• Pins 18 & 19 − These pins are used for interfacing an external crystal to get the
system clock.
• Pin 20 − This pin provides the power supply to the circuit.
• Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order
address bus signals are also multiplexed using this port.
• Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a
signal from the external program memory.
• Pin 30 − This is EA pin which stands for External Access input. It is used to
enable/disable the external memory interfacing.
• Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to
demultiplex the address-data signal of port.
• Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order
address and data bus signals are multiplexed using this port.
• Pin 40 − This pin is used to provide power supply to the circuit.

8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or
output. Hence, total 32 input/output pins allow the microcontroller to be connected with the
peripheral devices.
• Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per
the logic state.
o Input/Output (I/O) pin − All the circuits within the microcontroller must be
 connected to one of its pins except P0 port because it does not have pull-up
resistors built-in.
o Input pin − Logic 1 is applied to a bit of the P register. The output FE
transistor is turned off and the other pin remains connected to the power
supply voltage over a pull-up resistor of high resistance.
• Port 0 − The P0 (zero) port is characterized by two functions −
o When the external memory is used then the lower address byte (addresses
A0A7) is applied on it, else all bits of this port are configured as input/output.
o When P0 port is configured as an output then other ports consisting of pins
with built-in pull-up resistor connected by its end to 5V power supply, the pins
of this port have this resistor left out.
Input Configuration of Ports
If any pin of this port is configured as an input, then it acts as if it floats, i.e. the input has
unlimited input resistance and in-determined potential.
Output Configuration
When the pin is configured as an output, then it acts as an open drain. By applying logic 0 to
a port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the
external output will keep on floating.
In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup
resistor.
Port 1
P1 is a true I/O port as it doesnt have any alternative functions as in P0, but this port can be
configured as general I/O only. It has a built-in pull-up resistor and is completely compatible
with TTL circuits.
Port 2
P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.
Port 3
In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.
Pins Current Limitations
• When pins are configured as an output (i.e. logic 0), then the single port pins can
receive a current of 10mA.
• When these pins are configured as inputs (i.e. logic 1), then built-in pull-up resistors
provide very weak current, but can activate up to 4 TTL inputs of LS series.
• If all 8 bits of a port are active, then the total current must be limited to 15mA (port
P0: 26mA).
• If all ports (32 bits) are active, then the total maximum current must be limited to
71mA.

Interrupts are the events that temporarily suspend the main program, pass the control to the
external sources and execute their task. It then passes the control to the main program where
it had left off.
8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled
or disabled by setting bits of the IE register and the whole interrupt system can be disabled by
clearing the EA bit of the same register.
IE (Interrupt Enable) Register
This register is responsible for enabling and disabling the interrupt. EA register is set to one
for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their
meanings are shown in the following figure.

It disables all interrupts. When EA = 0 no interrupt will be

EA IE.7
acknowledged and EA = 1 enables the interrupt individually.

- IE.6 Reserved for future use.

- IE.5 Reserved for future use.

ES IE.4 Enables/disables serial port interrupt.

ET1 IE.3 Enables/disables timer1 overflow interrupt.

EX1 IE.2 Enables/disables external interrupt1.

ET0 IE.1 Enables/disables timer0 overflow interrupt.

EX0 IE.0 Enables/disables external interrupt0.

IP (Interrupt Priority) Register

We can change the priority levels of the interrupts by changing the corresponding bit in the
Interrupt Priority (IP) register as shown in the following figure.
• A low priority interrupt can only be interrupted by the high priority interrupt, but not
interrupted by another low priority interrupt.
• If two interrupts of different priority levels are received simultaneously, the request of
higher priority level is served.
• If the requests of the same priority levels are received simultaneously, then the
internal polling sequence determines which request is to be serviced.

- IP.6 Reserved for future use.

- IP.5 Reserved for future use.

PS IP.4 It defines the serial port interrupt priority level.

PT1 IP.3 It defines the timer interrupt of 1 priority.

PX1 IP.2 It defines the external interrupt priority level.

 PT0 IP.1 It defines the timer0 interrupt priority level.

PX0 IP.0 It defines the external interrupt of 0 priority level.

TCON Register
TCON register specifies the type of external interrupt to the microcontroller.

Microcontrollers are the key components of several electronic devices and embedded
systems, and they are brain behind their automated functioning or operation. Today,
microcontrollers are being used in devices, ranging from simple home appliances to complex
industrial automation systems.
Microcontrollers use several different types of instructions to perform operations; these
instructions are collectively known as instruction set.

What is an Instruction Set?

In microcontrollers, an instruction set is defined as a collection of codes or commands
written in machine-level language and processed by the processor of the microcontroller to
perform operations.
The primary function of instruction sets is to direct the microcontroller to perform tasks like
data processing, comparison of values, shifting or moving data from one register to another,
performing arithmetic and logic operations, etc.
Different types of microcontrollers such as ARM, AVR, STM32, etc. employes different
types of instruction sets to enable flexible and efficient computing.

Internal Data Memory Organization of Intel 8051

The internal data memory of 8051 is divided into two groups. These are a set of eight
registers and a scratch pad memory. These eight registers are R0 toR7. The address range
00H to 07H is used to access the registers, and the rest are scratch pad memory.
8051 Provides four register bank, but only one register bank can be used at any point in time.
To select the register bank, two bits of PSW (Program Status Word) are used.

So the following addressing can be used to select register banks.

Address Range Register Bank

00H to 07H Register Bank 0

 Address Range Register Bank

08H to 0FH Register Bank 1

10H to 17H Register Bank 2

18H to 1FH Register Bank 3

The concept of four register banks is very useful. For servicing the interrupts, this feature is
very good. The interrupt program can use one bank, and the interrupt Service Subroutine
(ISS) can access another bank for better performance. As there are four banks, so for nested
interrupts these can be used

When all of the register banks are being used, the scratch pad area will be 20H to 7FH. But
from 20H to 2FH (16 bytes or 128 bits) can be used as bit addressable RAM. By using some
simple instructions with 8-bit memory address we can check the bit addressing. For an
example the instruction CLR 6FH, using this instruction it clears the location 6FH. As we
know the8-bit address can locate 256 different locations, but here only128-bits are
addressable. Another section of bit addressable locations is 80H to FFH. The remaining
locations (30H to 7EH) of the RAM can be used to store variable data and stack.

Stack Area
The stack area in 8051always can be implemented in the internal data memory. Here the
stack pointer (SP) is an only 8-bit register, because the internal RAM area is only in range
00H to 7FH, and when all register banks are being used, the stack location will be in range
30H to 7FH. So in such a case, the SP will be initialized with 2FH.
The stack pointer SP increases before each PUSH operation and decreases after each pop
instruction.
When the 8051 is reset, the Stack Pointer will point to 07H. It means the location 08H to
7FHcan be used as a stack. We are assuming that the register bank 0 is in use and 20H to 27H
are not like bit-addressable area.

External Memory Interfacing in 8051 Microcontroller

The 8051 microcontroller is one of the most widely used type of microcontrollers in various
embedded systems, ranging from small electronic devices to complex industrial systems. One
of the key drawbacks of the 8051 microcontroller is that it has limited internal memory that
makes it essential to interface with an external memory like RAM or ROM. This external
memory interfacing allows the 8051 microcontroller to store larger programs, perform
complex operations, and handle large amount of data.

In this chapter, we will learn about External Memory Interfacing in 8051

Microcontroller and its need.
What is External Memory Interfacing?
External Memory Interfacing is defined as the process of connecting a microcontroller with
an external memory device like RAM or ROM. External memory interfacing is used in
embedded systems to allow the microcontroller to access data stored in a memory unit
outside the microcontroller.
Why External Memory Interfacing is Required in 8051 Microcontroller?
The following are some major reasons that arise the need for external memory interfacing in
the 8051 microcontroller −
• The 8051 microcontroller has a limited internal memory, which is 128 bytes of RAM
and 4 kB of ROM. This small memory is not sufficient for complex applications and
thus require an external memory.
• The 8051 microcontroller is sometimes used in applications that involve complex
algorithms, large programs, or multiple functions. Hence, an additional memory is
 needed in such applications.
• When the 8051 microcontroller is used in applications that require large storage
capacity, then it has to be interfaced with an external memory.
• Sometimes the 8051 microcontroller-based embedded systems are need to be
customized for different applications. This purpose also requires external memory
interfacing.
• External memory devices are less expensive as compared to on-chip memory. Hence,
the external memory interfacing also increases the cost-effectiveness of the 8051
microcontroller.
Memory Organization in 8051 Microcontroller
The organization of the 8051 microcontroller is done based on the Harvard Architecture.
Thus, it has a separate program memory (ROM) from data memory (RAM), whose
description is as follows −
• Program Memory − It is a ROM (Read Only Memory), which can be of 4 kB as
internal memory and up to 64 kB as external memory.
• Data Memory − It is a RAM (Random Access Memory), which is of 128 Bytes as
internal memory and of up to 64 kB as external memory.
How External Memory is Connected with 8051 Microcontroller?
In the 8051 microcontroller, the external memory devices are connected with the
microcontroller through −
• Data Bus − It transfers data between the microcontroller and the external memory
devices.
• Address Bus − It transfers the address of specific memory locations which are
selected for data exchange.
• Control Signals − These signals control the read/write operations of the memory.
After getting an overview of external memory interfacing and its needs, let us now
understand how the external program memory and the external data memory are interfaced
with the microcontroller.
Interfacing External Program Memory with 8051
The 8051 microcontroller is capable in accessing an external program memory or external
ROM of size up to 64 kB. For this purpose, it uses the PSEN (Program Store Enable) pin.
The connections of external ROM with the microcontroller are done as follows −
• Address bus (A0 to A15) are connected to the ROM address lines.
• Data bus (D0 to D7) are connected to the ROM data lines.
• PSEN (Pin 29) is connected to the Output Enable (OE) of the external ROM.
• ALE (Pin 30) is connected to latch the lower byte of the address.

The following instructions are used to access the external ROM interfaced with the 8051
microcontroller −
Mnemonic Operation

MOVC A, @ This instruction copies the content of external ROM address at

A+DPTR (A+DPTR) to A.

MOVC A, @ This instruction copies the content of external ROM address at (A +

A+PC PC) to A
Interfacing External Data Memory with 8051
As we know, the 8051 microcontroller can access an external data memory which is an
external RAM of size up to 64 kB using the RD (Read) and WR (Write) control signals. The
connections for external RAM interfacing with the 8051 microcontroller are explained here −
• Address bus (A0 to A15) are connected to address lines of the RAM.
• Data bus (D0 to D7) are connected to data lines of the RAM.
• RD (Pin 17) is connected to the Output Enable (OE) of the external RAM.
• WR (Pin 16) is connected to Write Enable (WE) of the external RAM.
• ALE (Pin 30) is connected to latch lower byte of the address.
The instructions used to access the external data memory or external RAM in 8051
microcontroller are given in the following table −
Mnemonic Operation

MOVX A, @Rp This instruction copies the content of external RAM at address Rp to A.

MOVX A, @DPTR This instruction copies the content of external RAM at address DPTR to A.

MOVX @Rp, A This instruction copies the data from A to external address in Rp.

MOVX DPTR, A This instruction copies the data from A to external address in DPTR

Address Decoding in External Memory Interfacing

Address decoding is one of the important processes which ensures that the correct memory
device is selected. As we know, the 8051 microcontroller has a 16-bit address bus (A0 to
A15), hence address decoding becomes a necessary process for correct memory mapping.
Issues in External Memory Interfacing in 8051 Microcontroller
When interfacing external memory devices with the 8051 microcontroller, several issues can
arise, some very common of them are as follows –
• If the timing signals which are used to control the external memory access are
incorrect, then they can cause errors in transfer or program execution.
• Interferences like electromagnetic interference or radio frequency interference can
cause errors or data corruption in external memory access.
• If the signal integrity of the address and data lines is not maintained, then it can cause
inaccurate data transfer between the microcontroller and the external memory device.
• The external memory devices require a stable and reliable power supply for proper
communication.
• The external memory devices used to interface with the 8051 microcontroller must be
compatible in terms of voltage, timing, and interface protocol specifications.

Conclusion

In conclusion, the 8051 microcontroller needs external memory interfacing for complex
applications that require additional memory for program and data storage. It allows
developers to expand the capabilities of the 8051 microcontroller by connecting external
memory devices.

Data Movement Between Big-Endian and Little-Endian Devices

This section addresses problems programmers and designers may encounter when working
with big-endian Power Architecture™ processors in conjunction with other devices that are
little-endian. The problems arise because a big-endian (BE) system stores the most significant
byte (MSB) of the data at the starting (or lowest) address, but a little-endian (LE) system
stores the least significant byte (LSB) of the data at the starting address. Examples and
explanations of data versus address invariance policies are provided throughout this
document. The terms ‘PCI bus’ and ‘agent’ are used synonymously because an agent add-in
card (a little-endian agent is considered in this application note) and the PCI bus of a
motherboard into which the agent is inserted are both little-endian, so data appears identically
on both.

What is Endianness? Big-Endian & Little-Endian

Computers operate using binary code, a language made up of 0s and 1s. This binary code
forms the foundation of all computer operations, enabling everything from rendering videos
to processing complex algorithms. A single bit is a 0 or a 1, and eight bits make up a byte.
While some data, such as certain English characters, can be represented by a single byte,
other data types require multiple bytes. The concept of endianness is crucial in understanding
how these bytes are read and interpreted by computers.
What is Endianness?
Endianness refers to the order in which bytes are arranged in memory. Different languages
read their text in different orders. for example, English reads from left to right, while Arabic
reads from right to left. Endianness works similarly for computers. If one computer reads
bytes from left to right and another reads them from right to left, issues arise when these
computers need to communicate.
Endianness ensures that bytes in computer memory are read in a specific order. Each
computer system is internally consistent with its own data, but the advent of the internet has
led to more data sharing than ever before, and not all systems read data in the same order.
Endianness comes in two primary forms: Big-endian (BE) and Little-endian (LE).
• Big-endian (BE): Stores the most significant byte (the "big end") first. This means
that the first byte (at the lowest memory address) is the largest, which makes the most
sense to people who read left to right.
• Little-endian (LE): Stores the least significant byte (the "little end") first. This means
that the first byte (at the lowest memory address) is the smallest, which makes the
most sense to people who read right to left.
What is Big-endian?
In a big-endian system, the most significant byte (MSB) is stored at the lowest memory
address. This means the "big end" (the most significant part of the data) comes first. For
instance, a 32-bit integer 0x12345678 would be stored in memory as follows in a big-endian
system:
Address: 00 01 02 03
Data: 12 34 56 78
Here, 0x12 is the most significant byte, placed at the lowest address (00), followed by 0x34,
0x56, and 0x78 at the highest address (03).
What is Little-endian?
A little-endian system stores the least significant byte (LSB) at the lowest memory address.
The "little end" (the least significant part of the data) comes first. For the same 32-bit
integer 0x12345678, a little-endian system would store it as:
Address: 00 01 02 03
Data: 78 56 34 12
Here, 0x78 is the least significant byte, placed at the lowest address (00), followed
by 0x56, 0x34, and 0x12 at the highest address (03).
Significance of Most Significant Byte (MSbyte) in Little and Big Endian:
Understanding the concept of the Most Significant Byte (MSbyte) helps clarify endianness
further. Let's use a decimal number to illustrate.
Consider the decimal number 2,984. Changing the digit 4 to 5 increases the number by 1,
while changing the digit 2 to 3 increases the number by 1,000. This concept applies to bytes
and bits as well.
• Most Significant Byte (MSbyte): The byte that holds the highest position value.
• Least Significant Byte (LSbyte): The byte that holds the lowest position value.
In big-endian format, the MSbyte is stored first. In little-endian format, the MSbyte is stored
last.
When Might Endianness Be an Issue?
Endianness must be considered in various computing scenarios, particularly when systems
with different byte orders need to communicate or share data.
1. Unicode Characters: Unicode, the character set used universally across devices, uses
a special character byte sequence called the Byte Order Mark
(BOM). The BOM informs the system that the incoming stream is Unicode, specifies
which Unicode character encoding is used, and indicates the endian order of the
incoming stream.
2. Programming Languages: Some programming languages require specifying the byte
order sequence. For instance, in Swift, used for iOS development, you can define
whether data is stored in big-endian or little-endian format.
3. Network Protocols: Different protocols have emerged historically, leading to the
need for interaction. Big-endian is the dominant order in network protocols and is
referred to as network order. Conversely, most PCs use little-endian format. Ensuring
interoperability between these formats is critical in network communication.
4. Processor Design: Processors can be designed to be either little-endian, big-
endian, or bi-endian (capable of handling both). Consumer choice and the resulting
market trends have influenced what is considered "normal" in computer systems
today.
Why is Endianness an Issue?
Endianness becomes an issue primarily due to the interaction between different systems and
protocols. Historical protocol development led to varying byte order conventions,
necessitating data conversion for compatibility. In higher-level languages and abstracted
environments, endianness is often managed behind the scenes, reducing the need for
developer concern. However, understanding endianness remains crucial for low-level
programming, network protocol design, and data interoperability.
Conclusion
Endianness is how bytes are ordered in computer data. Big-endian and little-endian are two
ways to arrange bytes, each with advantages. Understanding endianness is very important for
developers dealing with low-level data, networking, and system interoperability. While little-
endian is common, both formats remain important as technology evolves. Strategies for
managing data across endian conventions will continue developing to ensure compatibility
and performance.

Module -2
Types of Microcontroller Instructions
Microcontroller instructions can be classified into several categories depending on their
functionality, they are −
• Data processing instructions
• Arithmetic instructions
• Logical instructions
• Multiply instructions
• Comparison instructions
• Move instructions
• Barrel shifter instructions
Each of these types of microcontroller instructions are explained below in detail.
Data Processing Instructions
As the name implies, those microcontroller instructions which are used for manipulating data
withing registers are referred to as data processing instructions. These instructions make the
processor capable to perform operations.
The following is a simple example of data processing instruction −
This is a simple subtraction instruction which subtracts the value stored in the
register r2 from a value stored in the register r1, and stores the result of subtraction in the
register r0.
Before execution of the instruction, we have,
r0 = 0x00000000; Register r0 is empty before execution of the instruction.
r1 = 0x00000005; Register r1 holds a value 5.
r2 = 0x00000002; Register r2 holds a value 2.
SUB r0, r1, r2; r0 = r1 r2
After execution of this instruction, we get,
r0 = 0x00000003;
This is the output of the instruction.
Arithmetic Instructions
Microcontroller instructions which are used to perform and handle basic mathematical
operations, i.e., addition, subtraction, and multiplication are termed as arithmetic instructions.
The following table highlights all the key arithmetic instructions used in microcontrollers −
Instruction Description Operation Expression

ADD Add two values Rd = Rn + N

SUB Subtract two values Rd = Rn N

RSB Reverse subtraction Rd = N Rn

ADC Addition with carry Rd = Rn + N + Carry

Let's see an example of reverse subtraction to understand these instructions.
The reverse subtraction instruction or RSB subtracts the value stored in the register r1 from a
constant value, let #0, and write the result to the register r0.
Before execution of the instruction, we have,
r0 = 0x00000000; Empty output register.
r1 = 0x00000058; Register with value to be reverse subtracted.
RSB r0, r1, #0; Rd = 0x- - r1;
After execution of the instruction, we get,
r0 = -r1 = -0x00000058; Reverse output generated and stored in r0.
Logical Instructions
In microcontrollers, logical instructions are used to perform bitwise logical operations or
Boolean operations to manipulate bits within two source registers.
The following table gives common logical instructions used in microcontrollers −
Instruction Description Operation

AND Bitwise AND Rd = Rn & N

ORR Bitwise OR Rd = Rn | N

EOR Bitwise XOR Rd = Rn ^ N

BIC Bit clear (AND NOT) Rd = Rn & ~N

The following example explains the working of logical instructions in microcontrollers −
This instruction performs logical OR operation on values stored in registers r1 and r2 and
stores the result in r0.
Before execution of the instruction,
r0 = 0x00000000;
r1 = 0x05040207;
r2 = 0x20207050;
ORR r0, r1, r2;
After execution of the instruction, we get,
r0 = 0x25247257;
Multiply Instructions
The microcontroller instructions which are used to perform multiplication of values stored in
registers and accumulate results withing another register or across multiple registers.
The following are some common multiply instructions used in microcontrollers −
Instruction Description Operation

MUL Multiply two registers Rd = Rm * Rs

MLA Multiply and accumulate Rd = (Rm * Rs) + Rn

SMULL Signed multiplication long [RdHi, RdLo] = Rm * Rs

SMLAL Signed multiply accumulate long [RdHi, RdLo] = [RdHi, RdLo] + (Rm * Rs)

UMULL Unsigned multiply long [RdHi, RdLo] = Rm * Rs

UMLAL Unsigned multiply accumulate long [RdHi, RdLo] = [RdHi, RdLo] + (Rm * Rs)
Let's understand multiply instructions in microcontrollers with the help of an example.
This example shows a simple multiply instruction of two registers namely, r1 and r2, and it
stores the result in another register r0.
Before execution of the instruction,
r0 = 0x00000000;
r1 = 0x00000005;
r2 = 0x00000002;
MUL r0, r1, r2; r0 = r1 * r2;
After execution of the instruction, we get,
r0 = 0x00000010;
Comparison Instructions
Comparison instructions in microcontrollers are used to test or compare values within a
register. They also update the cpsr flags in the status register of the processor, without
affecting other registers.
After setting up the flag bits, information can then be utilized for altering the flow of program
execution. Some common comparison instructions used in microcontrollers are given below
−
Instruction Description Operation

CMN Compare negated Flags set as a result of Rn + N

CMP Compare Flags set as a result of Rn N

TEQ Test for quality of two 32-bit values Flags set as a result of Rn ^ N

TST Test bits of a 32-bit value Flags set as a result of Rn & N

Let us see an example to understand comparison instructions in microcontrollers.
Before execution of the instruction,
cpsr = nzcvqift_USER
r0 = 2;
r9 = 2;
CMP r0, r9;
After execution of the instruction, we get,
cpsr = nzcvqift_USER; Output produced after comparison.
Move Instructions
Move instructions are those instructions in microcontrollers which used to copy or transfer
data between registers.
The following are some common types of move instructions used in microcontrollers −
Instruction Description Operation

MOV Move value into a register Rd = N

MVN Move NOT of value into register Rd = ~N

Let us see an example to understand the working of move instructions in microcontrollers.
Before execution of instruction,
r1 = 2; value stored in register r1.
r2 = 7; value stored in register r2.
MOV r1, r2; r2 = r1;
After execution of instruction, we get,
r1 = 2;
r2 = 2;
Barrel Shifter Instructions
In microcontrollers, the barrel shifter instruction is used for efficient shifting and rotating bits
within a register. The following table provides some common barrel shifter instructions used
in microcontrollers −
Mnemonics Description Shift Result
 LSL Logical shift left xLSLy x << y

LSR Logical shift right xLSRy (Unsigned) x >> y

ASR Arithmetic right shift xASRy (Signed) x >> y

ROR Rotate right xRORy [(Unsigned) x >> y] | (x << (32 y))

RRX Rotate right extended xRRX (c flag << 31) | [(unsigned) x >> 1]
Here, x is the register being shifted and y is the shift amount.
Here is an example to explain the working of barrel shifter instructions in microcontrollers −
Before execution of instruction,
cpsr = nzcvqiFt_USER
r0 = 0x00000000;
r1 = 0x50000002;
MOVS r0, r1, LSL #1;
After execution of the instruction, we get,
cpsr = nzcvqiFt_USER
r0 = 0x00000005;
r1 = 0x50000002;
Advantages of Microcontroller Instruction Sets
The following are some key benefits of instruction sets of a microcontroller –
• Microcontroller instruction sets are efficient and enables fast execution or processing.
• Microcontroller instructions require low power to perform tasks, hence they are best
suited for embedded systems.
• Microcontroller instruction sets are versatile, as they support a wide range of
operations.
Disadvantages of Microcontroller Instruction Sets
Despite several advantages, the instruction sets of microcontrollers also have some
disadvantages, which are as follows −
• Microcontroller instruction sets offer limited flexibility. Thus, some operations need
more than one instruction.
• Microcontroller instruction sets are hardware dependent and offer compatibility
challenges.
Conclusion
In this chapter, we covered some essential types of instruction sets used in microcontrollers.
It is important to learn instruction sets for understanding the working of microcontrollers and
optimize their performance.

The instructions of 8051 Microcontroller can be classified into five different groups. These
groups are like below
• Data Transfer Group
• Arithmetic Group
• Logical Group
• Program Branch Group
• Bit Processing Group
•
This Bit-Processing group is also known as Boolean Variable Manipulation.
Like 8085, some instruction has two operands. The first operand is the Destination, and the
second operator is Source.
In the following examples, you will get some notations. The notations are like −
Rn = Any register from R0to R7
Ri = Either R0 or R1
d8 = Any 8-bit immediate data (00H to FFH)
d16 = 16-bit immediate data
a8 = 8-bit address
bit = 8-bit address of bit which is bit addressable
rel = 8-bit signed displacement. The range is -128 to 127. It is relative

Addressing Modes

In this section, we will see different addressing modes of the 8051 microcontrollers. In
8051 there are 1-byte, 2-byte instructions and very few 3-byte instructions are present.
The opcodes are 8-bit long. As the opcodes are 8-bit data, there are 256 possibilities.
Among 256, 255 opcodes are implemented.

The clock frequency is12MHz, so 64 instruction types are executed in just 1 µs, and rest
are just 2 µs. The Multiplication and Division operations take 4 µsto to execute.

In 8051 There are six types of addressing modes.

• Immediate AddressingMode
• Register AddressingMode
• Direct AddressingMode
• Register IndirectAddressing Mode
• Indexed AddressingMode
• Implied AddressingMode
•
Immediate addressing mode

In this Immediate Addressing Mode, the data is provided in the instruction itself. The
data is provided immediately after the opcode. These are some examples of Immediate
Addressing Mode.
MOVA, #0AFH;
MOVR3, #45H;
MOVDPTR, #FE00H;
In these instructions, the # symbol is used for immediate data. In the last instruction,
there is DPTR. The DPTR stands for Data Pointer. Using this, it points the external
data memory location. In the first instruction, the immediate data is AFH, but one 0 is
added at the beginning. So when the data is starting with A to F, the data should be
preceded by 0.

Register addressing mode

In the register addressing mode the source or destination data should be present in a
register (R0 to R7). These are some examples of RegisterAddressing Mode.
MOVA, R5;
MOVR2, #45H;
MOVR0, A;
In 8051, there is no instruction like MOVR5, R7. But we can get the same result by
using this instruction MOV R5, 07H, or by using MOV 05H, R7. But this two
instruction will work when the selected register bank is RB0. To use another register
bank and to get the same effect, we have to add the starting address of that register
bank with the register number. For an example, if the RB2 is selected, and we want to
access R5, then the address will be (10H + 05H = 15H), so the instruction will look like
this MOV 15H, R7. Here 10H is the starting address of Register Bank 2.

Direct Addressing Mode

In the Direct Addressing Mode, the source or destination address is specified by using 8-
bit data in the instruction. Only the internal data memory can be used in this mode.
Here some of the examples of direct Addressing Mode.
MOV80H, R6;
MOVR2, 45H;
MOVR0, 05H;
The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is
80H). The second one is forgetting content from 45H to R2. The third one is used to get
data from Register R5 (When register bank RB0 is selected) to register R5.
Register indirect addressing Mode

In this mode, the source or destination address is given in the register. By using register
indirect addressing mode, the internal or external addresses can be accessed. The R0
and R1 are used for 8-bit addresses, and DPTR is used for 16-bit addresses, no other
registers can be used for addressing purposes. Let us see some examples of this mode.
MOV0E5H, @R0;
MOV@R1, 80H
In the instructions, the @ symbol is used for register indirect addressing. In the first
instruction, it is showing that theR0 register is used. If the content of R0 is 40H, then
that instruction will take the data which is located at location 40H of the internal RAM.
In the second one, if the content of R1 is 30H, then it indicates that the content of port
P0 will be stored at location 30H in the internal RAM.
MOVXA, @R1;
MOV@DPTR, A;
In these two instructions, the X in MOVX indicates the external data memory. The
external data memory can only be accessed in register indirect mode. In the first
instruction if the R0 is holding 40H, then A will get the content of external RAM
location40H. And in the second one, the content of A is overwritten in the location
pointed by DPTR.

Indexed addressing mode

In the indexed addressing mode, the source memory can only be accessed from program
memory only. The destination operand is always the register A. These are some
examples of Indexed addressing mode.
MOVCA, @A+PC;
MOVCA, @A+DPTR;
The C in MOVC instruction refers to code byte. For the first instruction, let us consider
A holds 30H. And the PC value is1125H. The contents of program memory location
1155H (30H + 1125H) are moved to register A.
Implied Addressing Mode
In the implied addressing mode, there will be a single operand. These types of
instruction can work on specific registers only. These types of instructions are also
known as register specific instruction. Here are some examples of Implied Addressing
Mode.
RLA;
SWAPA;
These are 1- byte instruction. The first one is used to rotate the A register content to the
Left. The second one is used to swap the nibbles in A.