BCD to Seven Segment Display Lab 6
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
Lab 7 Implementation of Full Adder and Parallel Adder
OBJECTIVE
(1) To learn Half and Full Adder Operations.
(2) To learn 4- Bit Binary Parallel Adder Operations.
THEORY
a. Half Adder: The possible operations, when we want to add only two bits, would be
the followings:
0+0=0
0+1=1
1+0=1
1 + 1 = 0 & Carry 1
Above mentioned operation could be performed by a Half Adder circuit.
b. Full Adder : We know that in practice, all addition operations must take into account
the Carry bit (or digit) from the previous operation. Adders in digital computers also
take into account the Carry bit from last operation and add it with the Augend and
Addend bits of the present operation to complete the addition operation. The possible
operations are:
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
0 + 0 + 0 (carry) = 0
0 + 0 + 1 (carry) = 1
0 + 1 + 0 (carry) = 1
0 + 1 + 1 (carry) = 0 & carry 1 (to be added to next higher digit)
1 + 1 + 0 (carry) = 0 & carry 1 (to be added to next higher digit)
1 + 1 + 1 (carry) = 1 & carry 1 (to be added to next higher digit)
The adder that performs the addition of three bits (two significant bits and a previous carry) is
called a Full Adder.
TASK 1: HALF ADDER.
Arbitrarily assign symbols A and B to the two inputs and S (for sum) and Cout (for Carry) to the
two outputs. Truth table for Half Adder as shown below:-
Input
Output
Output
Desired Observed
A B S Cout S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
Table 1: Truth Table for Half Adder operation
The simplified Boolean function for the two outputs can be written from this truth table as:-
S = A'.B +A.B' or A B
Cout = A.B
The circuit diagram for the Half Adder to implement above mentioned Boolean function could be
quite a few. We will however verify only one.
Figure 1: Half Adder using AND and XOR gates.
PROCEDURE
Implement the circuit as per figure 1 [Link] setting various combinations of the two switches
verify that the output of the circuit is in accordance with the Truth Table shown above. Record your
observation.
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
TASK 2: FULL ADDER.
As mentioned in the beginning, a full-adder is a combinational circuit that form the arithmetic
sum of three input bits (two significant bits and a previous carry bit ) and two output bits. We
arbitrarily assign symbols A and B to the two significant bit inputs and Cin for the Carry from
the previous lower significant position, and S (for sum) and Cout (for Carry) to the two outputs.
Truth table for the Full Adder is shown below
Input Output Output
Desired Observed
A B Cin S Cout S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Simplified Boolean function for the two outputs can be written from this truth table as:-
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
S = A B Cin
Cout = ( A B) Cin +A.B
The circuit diagram for the Full Adder is as under:
Figure 2: Full Adder comprising of two Half Adders and an OR gate.
PROCEDURE
Implement the Full Adder circuit as per figure 2 [Link] setting various combinations of the two
switches verify that the output of the circuit is in accordance with the Truth Table shown above.
Record your observation.
TASK 3: 4 BIT BINARY PARALLEL ADDER
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
Figure 3 : IC 7483 Internal Functional Structure
Adders that are available in integrated circuit form are parallel binary adders. A 4-Bit parallel
adder actually consists of four full adders connected in parallel. The carry output of each adder is
internally connected to the carry input of the next higher order adder. Fig 5 shows the internal
functional structure of 7483 IC in which 4 full adders are shown as separate entity. Figure 6 is
connection diagram for full adder function.
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
Figure 4: Connection Diagram for 4-Bit Parallel Adder
PROCEDURE:
1. Wire the circuit as per figure 4 above.
2. Use first four Logic Switches of the trainer for the inputs A0 to A3, and next four switches for
inputs B0 to B3.
3. Connect Cin (pin 13) to GND (we are assuming initial carry to be zero).
4. Use first four LEDs of the trainer to indicate Sum outputs S0 to S3, and another LED to indicate
status of the most significant carry bit Cout.
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
5. Connect +5V to pin 5 (Vcc) and Ground to pin 12 (GND) of the ICs.
6. By setting various combinations of the two sets of input switches verify that the output of the
circuit is in accordance with the Table shown below (only few of the possible additions have
been shown here). Record your observation.
Inputs Desired Output Observed Output
Decimal Decimal
Binary Augend Binary Addend Binary Output Binary Output
Value value
A B Sum
A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S0 Co S3 S2 S1 S0
0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 2
0 0 1 1 0 0 0 1 3 1 0 0 1 0 0 4
0 1 0 0 0 0 1 0 4 2 0 0 1 1 0 6
0 1 0 0 0 1 0 0 4 4 0 1 0 0 0 8
0 1 0 1 0 1 0 0 5 4 0 1 0 0 1 9
0 1 0 1 0 1 0 1 5 5 0 1 0 1 0 10
1 0 0 0 0 1 0 0 8 4 0 1 1 0 0 12
1 0 0 1 0 1 1 0 9 6 0 1 1 1 1 15
School of Systems and Technology Digital Logic Design Lab
Implementation of Full Adder and Parallel Adder Lab 7
1 0 0 1 1 0 0 0 9 8 1 0 0 0 1 17
1 0 0 1 1 0 0 1 9 9 1 0 0 1 0 18
School of Systems and Technology Digital Logic Design Lab