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Tutorial Cache Memory

The document presents a series of tutorial questions on cache memory, covering various cache configurations and their implications on data access. It includes specific examples with calculations for direct mapped, fully associative, and set associative caches, detailing the number of bits required for tag, index, and address fields. Solutions are provided for each question, illustrating the principles of cache memory organization and access patterns.

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3 views2 pages

Tutorial Cache Memory

The document presents a series of tutorial questions on cache memory, covering various cache configurations and their implications on data access. It includes specific examples with calculations for direct mapped, fully associative, and set associative caches, detailing the number of bits required for tag, index, and address fields. Solutions are provided for each question, illustrating the principles of cache memory organization and access patterns.

Uploaded by

shivanshmittal023
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Tutorial Questions on Cache memory

Q1. Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes.
The system has a physical address space of 64 KB and a word length of 16 bits. During
the execution of a program, four data words P, Q, R, and S are accessed in that order 10
times (i.e., PQRSPQRS .....). Hence, there are 40 accesses to the data cache altogether.
Assume that the data cache is initially empty and no other data words are accessed by
the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC284,
0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the
following statements is/are TRUE with respect to the data cache?

(a) Every access to S is a hit


(b) Once P is brought to the cache it is never evicted
(c) At the end of the execution only R and S reside in the cache
(d) Every access to R evicts Q from the
cache

Solution: (a), (b) and (d)


Explanation
Direct Mapping
CM size = 2 KB
MM size = 64 KB
Block size = 64 B
Number of lines = 2K/64⇒211/26=25
Q2. A certain processor uses a fully associative cache of size 16 kB. The cache block size
is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit
address. How many bits are required for the Tag and the Index fields respectively in the
addresses generated by the processor?

Solution:
Cache size = 16 KB
Block Size = 16 B = 24 B
Block offset or word = 4 bits
Main memory address = 32 bits
In fully associative cache main memory address format there are no index bits.
Tag bits = Total bits - Offset bits = 32 - 4 = 28
So, Tag bits = 28, Index bits = 0

Q3. A CPU has a 32-bit memory address, i.e byte addressable and a 256 KB cache
memory. The cache is organized as a 4-way set associative cache with cache block size of
16 bytes. How many bits are required for the Tag, Set, and Word fields respectively in
the addresses generated by the processor?

Solution:
Main memory address = 32 bits
Cache Memory Size = 256 KB
Type: 4-way set associative.
Each block = 16 bytes
Total blocks = 256 KB / 16 B = 218/24 = 214
Total sets = 214/ 22= 212
Each block has 16 bytes, and since memory is byte addressable so number of words = 16
= 24
Tag = Total bits - (set + word) = 32 - 16 = 16 bits
Therefore, we have Tag= 16, Set = 12, Word = 4

Q4. A word addressable computer has 64KBs of memory and 16-bit word size. Its
memory is built out of 4Kx4 chips. The computer uses low-order interleave. Answer the
following questions.
a. How many chips make up memory?
b. How many banks make up memory?
c. How many bits make up an address?
d. Of the bits from part c, which make up the bank select and which make up the address
sent to the bank?

Solution:
64KB of 16-bit words means 64KB/16/8 = 32K words.
a. 32Kx16/4Kx4 = 32 chips
b. 32 chips / (16/4) = 8 banks
c. Log 2 32K = 15 bit address
d. 8 banks requires 3 bits, low-order interleave means the rightmost 3 bits are the bank,
so the format is: 12 bits (address to the bank) | 3 bits (bank select)

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