:/VLSI_Projects/Adaptive_Mul/Adaptive_WTM/Adaptive_WTM.
runs/synth_
D
1/adaptive_system_top_utilization_synth.rpt
opyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced
C
Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
-----------------------------------------------------------
| Tool Version : Vivado v.2025.2 (win64) Build 6299465 Fri Nov 14 19:35:11 GMT
2025
| Date
: Tue May 12 08:55:08 2026
| Host
: DESKTOP-P6CH476 running 64-bit major release (build 9200)
| Command
: report_utilization -file
adaptive_system_top_utilization_synth.rpt -pb
adaptive_system_top_utilization_synth.pb
| Design
: adaptive_system_top
| Device
: xc7a100tcsg324-1
| Speed File
: -1
| Design State : Synthesized
----------------------------------------------------------------------------------
-----------------------------------------------------------
Utilization Design Information
able of Contents
T
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
. Slice Logic
1
--------------
-------------------------+------+-------+------------+-----------+-------+
+
|
Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs*
| 357 | 0 | 0 | 63400 | 0.56 |
|
LUT as Logic | 357 | 0 | 0 | 63400 | 0.56 |
|
LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
| Slice Registers
| 173 | 0 | 0 | 126800 | 0.14 |
|
Register as Flip Flop | 173 | 0 | 0 | 126800 | 0.14 |
|
Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
| F7 Muxes
| 0 | 0 | 0 | 31700 | 0.00 |
| F8 Muxes
| 0 | 0 | 0 | 15850 | 0.00 |
| Unique Control Sets
| 1 | | 0 | 15850 | <0.01 |
-------------------------+------+-------+------------+-----------+-------+
+
* Warning! The Final LUT count, after physical optimizations and full
implementation, is typically lower. Run opt_design after synthesis, if not already
completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
Warning! For any ECO changes, please run place_design if there are unplaced
instances
** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets
Report for more information regarding control sets.
.1 Summary of Registers by Type
1
--------------------------------
-------+--------------+-------------+--------------+
+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0
| _ | - | - |
| 0
| _ | - | Set |
| 0
| _ | - | Reset |
| 0
| _ | Set | - |
| 0
| _ | Reset | - |
| 0
| Yes | - | - |
| 0
| Yes | - | Set |
| 173
| Yes | - | Reset |
| 0
| Yes | Set | - |
| 0
| Yes | Reset | - |
+-------+--------------+-------------+--------------+
. Memory
2
---------
----------------+------+-------+------------+-----------+-------+
+
|
Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile |
0 | 0 | 0 | 135 | 0.00 |
|
RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
|
RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can
accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a
Block RAM Tile, that tile can still accommodate a RAMB18E1
. DSP
3
------
-----------+------+-------+------------+-----------+-------+
+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs
| 0 | 0 | 0 | 240 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
. IO and GT Specific
4
---------------------
-----------------------------+------+-------+------------+-----------+-------+
+
|
Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB
| 68 | 0 | 0 | 210 | 32.38 |
| Bonded IPADs
| 0 | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL
| 0 | 0 | 0 | 6 | 0.00 |
| PHASER_REF
| 0 | 0 | 0 | 6 | 0.00 |
| OUT_FIFO
| 0 | 0 | 0 | 24 | 0.00 |
| IN_FIFO
| 0 | 0 | 0 | 24 | 0.00 |
| IDELAYCTRL
| 0 | 0 | 0 | 6 | 0.00 |
| IBUFDS
| 0 | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY
| 0 | 0 | 0 | 24 | 0.00 |
| PHASER_IN/PHASER_IN_PHY
| 0 | 0 | 0 | 24 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY |
0 | 0 | 0 | 300 | 0.00 |
| ILOGIC
| 0 | 0 | 0 | 210 | 0.00 |
| OLOGIC
| 0 | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
. Clocking
5
-----------
------------+------+-------+------------+-----------+-------+
+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL
| 1 | 0 | 0 | 32 | 3.13 |
| BUFIO
| 0 | 0 | 0 | 24 | 0.00 |
| MMCME2_ADV |
0 | 0 | 0 | 6 | 0.00 |
| PLLE2_ADV |
0 | 0 | 0 | 6 | 0.00 |
| BUFMRCE
| 0 | 0 | 0 | 12 | 0.00 |
| BUFHCE
| 0 | 0 | 0 | 96 | 0.00 |
| BUFR
| 0 | 0 | 0 | 24 | 0.00 |
+------------+------+-------+------------+-----------+-------+
. Specific Feature
6
-------------------
-------------+------+-------+------------+-----------+-------+
+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2
| 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2
| 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT
| 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR
| 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 |
0 | 0 | 0 | 1 | 0.00 |
ICAPE2
| | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1
| 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2
| 0 | 0 | 0 | 1 | 0.00 |
| XADC
| 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
. Primitives
7
-------------
----------+------+---------------------+
+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6
| 201 | LUT |
| FDCE
| 173 | Flop & Latch |
| LUT4
| 83 | LUT |
| LUT5
| 76 | LUT |
| LUT2
| 65 | LUT |
| IBUF
| 36 | IO |
| OBUF
| 32 | IO |
| LUT3
| 28 | LUT |
| LUT1
| 1 | LUT |
| BUFG
| 1 | Clock |
+----------+------+---------------------+
. Black Boxes
8
--------------
----------+------+
+
| Ref Name | Used |
+----------+------+
. Instantiated Netlists
9
------------------------
----------+------+
+
| Ref Name | Used |
+----------+------+