Module-5

Introduction to the ARM Instruction set

Contents
• Introduction
• Data processing instructions
• Load – Store instruction
• Software interrupt instructions
• Program status register instructions
• Loading constants
• ARMv5E extensions
• Conditional Execution
Introduction
• ARM instructions process data held in registers and only access
memory with load and store instructions.
• ARM instructions commonly take two or three operands.
• For instance the ADD instruction below adds the two values stored in
registers r1 and r2 (the source registers).
• It writes the result to register r3 (the destination register).
Data processing instructions
• The data processing instructions manipulate data within registers.
• They are move instructions, arithmetic instructions, logical
instructions, comparison instructions, and multiply instructions.
• Most data processing instructions can process one of their operands
using the barrel shifter.
• If you use the S suffix on a data processing instruction, then it updates
the flags in the cpsr.
• Move and logical operations update the carry flag C, negative flag N,
and zero flag Z.
Move Instructions
• It copies N into a destination register Rd, where N is a register or
immediate value.
• This instruction is useful for setting initial values and transferring data
between registers.
Example
Barrel Shifter
• A unique and powerful feature of the ARM processor is the ability to
shift the 32-bit binary pattern in one of the source registers left or
right by a specific number of positions before it enters the ALU.
• This shift increases the power and flexibility of many data processing
operations.
• Pre-processing or shift occurs within the cycle time of the instruction.
• This is particularly useful for loading constants into a register and
achieving fast multiplication or division by a power of 2.
Barrel Shifter and ALU

Pre-processing or shift

The example multiplies register r5 by four and then places

the result into register r7.
Barrel shifter operations
Example : MOVS r0, r1, LSL #1
• This example of a MOVS
instruction shifts register r1
left by one bit.
• This multiplies register r1 by a
value 2 (1 0000 0008).
• As you can see, the C flag is
updated in the cpsr because
the S suffix is present in the
instruction mnemonic.
Logical shift left by one
Arithmetic Instructions
• The arithmetic instructions implement addition and subtraction of
32-bit signed and unsigned values.
Example: SUB r0, r1, r2
Example: SUBS r1, r1, #1
Example: Using the Barrel Shifter with Arithmetic
Instructions
RSB r0, r1, #0
• This reverse subtract instruction (RSB) subtracts r1 from the constant
value #0, writing the result to r0. You can use this instruction to
negate numbers.
Logical Instructions
• Logical instructions perform bitwise logical operations on the two
source registers.
ORR r0, r1, r2

What is the result ?

ORR r0, r1, r2
BIC r0, r1, r2

• In this example, register r2

contains a binary pattern where
every binary 1 in r2 clears a
corresponding bit location in
register r1.

• This instruction is particularly

useful when clearing status bits
and is frequently used to change
interrupt masks in the cpsr.
Comparison Instructions
• The comparison instructions are used to compare or test a register
with a 32-bit value.
• They update the cpsr flag bits according to the result, but do not
affect other registers.
• After the bits have been set, the information can then be used to
change program flow by using conditional execution.
• You do not need to apply the S suffix for comparison instructions to
update the flags.
Comparison Instructions

• The CMP is effectively a subtract instruction with the result discarded; similarly the
TST instruction is a logical AND operation, and TEQ is a logical exclusive OR
operation.
• For each, the results are discarded but the condition bits are updated in the cpsr.
• It is important to understand that comparison instructions only modify the condition
flags of the cpsr and do not affect the registers being compared.
Multiply Instructions
• The multiply instructions multiply the contents of a pair of registers
and, depending upon the instruction, accumulate the results in with
another register.
• The long multiplies accumulate onto a pair of registers representing a
64-bit value.
• The final result is placed in a destination register or a pair of registers.
Multiply Instructions
• The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL)
produce a 64-bit result.
• The result is too large to fit a single 32-bit register so the result is
placed in two registers labelled RdLo and RdHi.
• RdLo holds the lower 32 bits of the 64-bit result, and RdHi holds the
higher 32 bits of the 64-bit result.
Branch Instructions
• A branch instruction changes the flow of execution or is used to call a
routine.
• This type of instruction allows programs to have subroutines,
if-then-else structures, and loops.
• The change of execution flow forces the program counter pc to point
to a new address.
• The address label is stored in the instruction as a signed pc-relative
offset and must be within approximately 32 MB of the branch
instruction.
Branch Instructions
Examples of branch instructions
• The forward branch skips three instructions.
• The backward branch creates an infinite loop.
• Branches are used to change execution flow.
• Most assemblers hide the details of a branch
instruction encoding by using labels.
• In this example, forward and backward are the
labels.
• The branch labels are placed at the beginning of
the line and are used to mark an address that can
be used later by the assembler to calculate the
branch offset.
BL-Branch with Link
• The branch with link, or BL,
instruction is similar to the B
instruction but overwrites the link
register lr with a return address.
• It performs a subroutine call. This
example shows a simple fragment of
code that branches to a subroutine
using the BL instruction.
• To return from a subroutine, you
copy the link register to the pc.
Load-Store Instructions
• Load-store instructions transfer data between memory and processor
registers.
• There are three types of load-store instructions: single-register
transfer, multiple-register transfer, and swap.
Single-Register Transfer
• These instructions are used for moving a single data item in and out
of a register.
• The datatypes supported are signed and unsigned words (32-bit),
half-words (16-bit), and bytes.
Single register transfer
• LDR and STR instructions can load and
store data on a boundary alignment that is
the same as the datatype size being
loaded or stored.
Single-Register Load-Store Addressing Modes
• The ARM instruction set provides different modes for addressing
memory.
• These modes incorporate one of the indexing methods: preindex with
writeback, preindex, and postindex
• Preindex with writeback calculates an
address from a base register plus address
offset and then updates that address base
register with the new address.
• In contrast, the preindex offset is the
same as the preindex with writeback but
does not update the address base
register.
• Postindex only updates the address base
register after the address is used.
• The preindex mode is useful for accessing
an element in a data structure.
• The postindex and preindex with
writeback modes are useful for traversing
an array.
Multiple-Register Transfer
• Load-store multiple instructions can transfer multiple registers between memory and the
processor in a single instruction.
• The transfer occurs from a base address register Rn pointing into memory.
• Multiple-register transfer instructions are more efficient from single-register transfers for
moving blocks of data around memory and saving and restoring context and stacks.
• Load-store multiple instructions can increase interrupt latency.
• ARM implementations do not usually interrupt instructions while they are executing.
• For example, on an ARM7 a load multiple instruction takes 2 + Nt cycles, where N is the
number of registers to load and t is the number of cycles required for each sequential access
to memory.
• If an interrupt has been raised, then it has no effect until the load-store multiple instruction is
complete.
• Any subset of the current bank of registers can be transferred to memory or fetched from
memory.
• The base register Rn determines the source or destination address for a load-store multiple
instruction.
• This register can be optionally updated following the transfer.
• This occurs when register Rn is followed by the ! character, similar to the single-register
load-store using preindex with writeback.
LDMIA r0!, {r1-r3}
LDMIA → Load Multiple Increment After

r0! → Use r0 as base address, and update it after execution (! means write-back)

{r1–r3} → Load values into registers r1, r2, r3

Load multiple values from memory into r1, r2, r3 starting from address in r0, and update r0 after loading.

Pre-condition (Before execution)

Explain what is given:
● r0 = 0x800010 → starting memory address

● Memory contains:

○ 0x800010 → 0x01

○ 0x800014 → 0x02

○ 0x800018 → 0x03

Emphasize:
● Each value is 32-bit (word) → addresses increase by 4 bytes
Step by Step Process
●
● | Step | Action |
● | ---- | --------------------------------------- |
● | 1 | Load from address in r0 → into r1 |
● | 2 | Increment address by 4 |
● | 3 | Load next value → into r2 |
● | 4 | Increment address by 4 |
● | 5 | Load next value → into r3 |
● | 6 | Final updated address stored back in r0 |
Start from:

● r0 = 0x800010
● Then:
● r1 = Memory[0x800010] = 0x01
r2 = Memory[0x800014] = 0x02
r3 = Memory[0x800018] = 0x03

Now update r0:

● New r0 = 0x80001C Because: 3 registers × 4 bytes = 12 bytes = 0xC ; 0x800010 + 0xC = 0x80001C
After execution

r1 = 0x00000001
r2 = 0x00000002
r3 = 0x00000003
r0 = 0x80001C
✔ Loads multiple registers in one instruction
✔ Memory is accessed in ascending order
✔ Address increments by 4 bytes (word size)
✔ ! means update base register (r0)

“LDMIA loads multiple registers sequentially from memory and updates the base address
automatically.”
LDMIB r0!, {r1-r3}

Pre-condition for LDMIB instruction

load-store multiple instruction pairs
• If you use a store with base
update, then the paired load
instruction of the same
number of registers will
reload the data and restore
the base address pointer.

• This is useful when you need

to temporarily save a group of
registers and restore them
later.
Example: STMIB with LDMDA

1. The STMIB instruction stores the values 7,

8, 9 to memory.
2. We then corrupt register r1 to r3.

3. The LDMDA reloads the original values and

restores the base pointer r0.
This example shows how we can save register values to memory and later restore them back
Saving your work
Editing something
Then restoring the original

Step 1: Initial Values (PRE)

Explain:
r0 = base address (0x0009000); r1 = 9; r2 = 8; r3 = 7
STMIB Instruction STMIB r0!, {r1–r3} STM → Store Multiple; IB → Increment Before; r0! → update r0 after storing, “We store r1, r2,
r3 into memory”
Increment BEFORE storing So: First address = r0 + 4; Then store values sequentially
Values stored in memory: 7, 8, 9 (based on register order in execution)
Registers are Modified (Corruption Step)
MOV r1, #1
MOV r2, #2
MOV r3, #3
“Now we change the register values, so original data is lost from registers.”

Now: r1 = 1 r2 = 2 r3 = 3 But original values are safe in memory

“LDMDA works in the reverse direction of STMIB”
● STMIB → Increment Before

● LDMDA → Decrement After

This pairing ensures:

We read back values in the correct original order
After execution:
● r1 = 9; r2 = 8; r3 = 7; r0 restored to original value

So we successfully:
✔ Stored values
✔ Modified registers
✔ Restored original values

“STMIB saves register values to memory, and LDMDA restores them back in reverse addressing order.”
Block memory copy (example: 32 Bytes
transfer)
 Block memory copy
• Registers r9 and r11 determine the data to be copied, and register r10 points to the
destination in memory for the data.
• LDMIA loads the data pointed to by register r9 into registers r0 to r7. It also updates
r9 to point to the next block of data to be copied.
• STMIA copies the contents of registers r0 to r7 to the destination memory address
pointed to by register r10. It also updates r10 to point to the next destination
location.
• CMP and BNE compare pointers r9 and r11 to check whether the end of the block
copy has been reached.
• If the block copy is complete, then the routine finishes; otherwise the loop repeats
with the updated values of register r9 and r10.
• The BNE is the branch instruction B with a condition mnemonic NE (not equal).
• If the previous compare instruction sets the condition flags to not equal, the branch
instruction is executed.
Stack Operations
• The ARM architecture uses the load-store multiple instructions to carry out
stack operations.
• The pop operation (removing data from a stack) uses a load multiple
instruction;
• The push operation (placing data onto the stack) uses a store multiple
instruction.
• Ascending (A) stacks grow towards higher memory addresses; in contrast,
descending (D) stacks grow towards lower memory addresses.
• When you use a full stack (F), the stack pointer sp points to an address that
is the last used or full location (i.e., sp points to the last item on the stack).
• If you use an empty stack (E) the sp points to an address that is the first
unused or empty location
Addressing modes for stack operations
STMFD sp!, {r1,r4}

• The STMFD instruction pushes registers

onto the stack, updating the sp.
• STMFD is a push onto a full descending
stack.
• When the stack grows the stack pointer
points to the last full entry in the stack.
STMED sp!, {r1,r4}

• STMED instruction is used to push registers

on an empty stack.
• The STMED instruction pushes the registers
onto the stack but updates register sp to
point to the next empty location.
Swap Instruction
• The swap instruction is a special case of a load-store instruction.
• It swaps the contents of memory with the contents of a register.
• This instruction is an atomic operation—it reads and writes a location
in the same bus operation, preventing any other instruction from
reading or writing to that location until it completes.
• Swap cannot be interrupted by any other instruction or any other bus
access. We say the system “holds the bus” until the transaction is
complete.
Syntax of the SWAP instruction
SWP r0, r1, [r2]
The swap instruction
loads a word from
memory into register r0
and overwrites the
memory with register
r1.
Software Interrupt Instruction
• A software interrupt instruction (SWI) causes a software interrupt
exception, which provides a mechanism for applications to call
operating system routines.
• When the processor executes an SWI instruction, it sets the program
counter pc to the offset 0x8 in the vector table.
• The instruction also forces the processor mode to SVC, which allows
an operating system routine to be called in a privileged mode.
• Each SWI instruction has an associated SWI number, which is used to
represent a particular function call or feature.
 Software Interrupt Instruction
0x00008000 SWI 0x123456

• Since SWI instructions are used to call operating system

routines, you need some form of parameter passing.

• This is achieved using registers. In this example, register r0 is

used to pass the parameter 0x12. The return values are also
passed back via registers. Here we have a simple example of an SWI call
with SWI number 0x123456, used by ARM
toolkits as a debugging SWI.
lr_svc = address of next instruction
👉 “Processor saves return address so it can come back later”
spsr_svc = cpsr
👉 “It saves the current state before switching modes”
pc = vectors + 0x8
👉 “Jumps to SWI handler (fixed location in memory)”
cpsr mode = SVC
👉 “Switches to Supervisor mode (privileged mode)”
cpsr I = 1
👉 “Disables interrupts temporarily for safety”
● Registers are used to pass data Example: r0 = 0x12 → parameter
“Before calling SWI, we load values into registers.
The OS reads these registers to know what input we gave.”
0x00008000 SWI 0x123456
BEFORE execution (PRE): Processor is in USER mode
r0 = 0x12 (input parameter)
pc = 0x00008000 (current instruction)
AFTER execution (POST): Mode changes to SVC mode
● pc = 0x00000008 → jumps to SWI handler
● lr = 0x00008004 → return address stored
“The processor saves where it came from and jumps to OS code.”
Program Status Register Instructions
•The ARM instruction set provides two instructions to
directly control a program status register (psr).
•The MRS instruction transfers the contents of either
the cpsr or spsr into a register; in the reverse
direction, the MSR instruction transfers the contents
of a register into the cpsr or spsr.
•Together these instructions are used to read and write
the cpsr and spsr.
Program Status Register Instructions
Modifying “I” bit in CPSR
• The MSR first copies the cpsr into
register r1.
• The BIC instruction clears bit 7 of r1.
• Register r1 is then copied back into the
cpsr, which enables IRQ interrupts.
• You can see from this example that this
code preserves all the other settings in
the cpsr and only modifies the I bit in
the control field.
• This example is in SVC mode.
• In user mode you can read all cpsr bits,
but you can only update the condition
flag field f.
Loading Constants
• You might have noticed that there is no ARM instruction to move a
32-bit constant into a register.
• Since ARM instructions are 32 bits in size, they obviously cannot
specify a general 32-bit constant.
• To aid programming there are two pseudoinstructions to move a
32-bit value into a register.