Digital Logic Design

One-Day Revision Notes

Logic Gates | Boolean Algebra | Combinational Circuits | Sequential Circuits

01 Topic 1: Basic Logic Gates

Definition: Basic building blocks of digital circuits that perform logical operations on binary inputs (0 or 1).

Gate Symbol / Name Boolean Expression Output Rule

AND A · B (or AB) Y=A·B Output 1 only when ALL inputs are 1

OR A+B Y=A+B Output 1 when ANY input is 1

NOT A' or ■ Y = A' Output is opposite (complement) of input

Truth Tables
AND Gate OR Gate NOT Gate

A B Y A B Y A Y

0 0 0 0 0 0 0 1

0 1 0 0 1 1 1 0

1 0 0 1 0 1

1 1 1 1 1 1

EXAM TIP: Most common exam questions: draw truth table for given gate, identify gate from truth table, write
Boolean expression. AND = multiplication, OR = addition, NOT = complement.

02 Topic 2: Boolean Algebra Laws

Definition: A set of mathematical rules used to simplify and manipulate Boolean (logical) expressions in digital circuits.

Law AND Form OR Form Memory Tip

1. Commutative A · B = B · A A + B = B + A Order doesn't matter

2. Associative (A·B)·C = A·(B·C) (A+B)+C = A+(B+C) Grouping doesn't matter

3. Distributive A·(B+C) = A·B + A·C A+(B·C) = (A+B)·(A+C) Expand brackets

4. Identity A · 1 = A, A · 0 = 0 A + 0 = A, A + 1 = 1 Neutral element

5. Redundancy
A · A = A A · A' = 0 A + A = A A + A' = 1 Same or complement
(Complement)
6. De Morgan's (A · B)' = A' + B' (A + B)' = A' · B' Flip op, complement all

EXAM TIP: De Morgan's Law is the most tested. Remember: break the bar, change the sign. (AB)' = A' + B' and
(A+B)' = A'B'. Identity law shortcuts: anything AND 0 = 0, anything OR 1 = 1.

03 Topic 3: Combinational Logic Circuits

Definition: Circuits whose output depends only on the current inputs (no memory, no clock). Output = f(inputs).

3a. Half Adder

• Adds two 1-bit numbers (A and B). Produces Sum and Carry.
• Built with: 1 EX-OR gate (for Sum) + 1 AND gate (for Carry).
• Limitation: Cannot accept a carry input from a previous addition.

Sum = A XOR B = A ⊕ B Carry = A AND B = A · B

Truth Table — Half Adder

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

3b. Full Adder

• Adds three 1-bit numbers: A, B, and Carry-in (Cin).
• Produces Sum and Carry-out (Cout).
• Built with: 2 EX-OR gates + 2 AND gates + 1 OR gate.
• Can be cascaded for multi-bit addition (ripple-carry adder).

Sum = (A ⊕ B) ⊕ Cin Carry-out = A·B + Cin·(A ⊕ B)

Truth Table — Full Adder

A B Cin Sum Carry-out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Half Adder vs Full Adder — Quick Comparison

Parameter Half Adder Full Adder

Inputs 2 (A, B) 3 (A, B, Cin)

 Outputs Sum, Carry Sum, Carry-out

Carry input No Yes

Gates 1 XOR + 1 AND 2 XOR + 2 AND + 1 OR

Alternate name — Ripple-carry adder

Used in Calculators, simple circuits ALU, multi-bit processors

3c. Encoders
• Converts 2N input lines into N output lines (binary code). One input active at a time.
• Example: 8x3 Octal-to-Binary encoder — 8 inputs, 3 outputs (X, Y, Z).
• Boolean functions: X = D4+D5+D6+D7, Y = D2+D3+D6+D7, Z = D1+D3+D5+D7
• Implemented using OR gates only.

Priority Encoder:
• Solves the problem when more than one input is active at the same time.
• Higher-priority input overrides lower ones. Includes a Valid bit (V).
• V = 1 when at least one input is active; V = 0 when all inputs are 0.
• For 4-to-2 priority encoder: X = D2 + D3, Y = D1·D2' + D3

3d. Decoders
• Opposite of encoder. Converts N input lines into 2N output lines.
• Example: 3-to-8 line decoder — 3 inputs (X, Y, Z), 8 outputs (D0–D7).
• Each output is a minterm: D0 = X'Y'Z', D1 = X'Y'Z, D2 = X'YZ', ... D7 = XYZ
• Implemented using AND gates (with inverters for complement inputs).

Encoder: 2N inputs → N outputs (uses OR Decoder: N inputs → 2N outputs (uses AND

gates) gates)

3e. Multiplexer (MUX)

• Selects 1 out of N = 2n inputs and routes it to a single output.
• Also called a data selector. Has data inputs, select lines, and one output.
• n select lines control which input passes to output.

MUX Type Data Inputs Select Lines Boolean Expression

2×1 MUX I0, I1 1 (S) Y = S'·I0 + S·I1

4×1 MUX I0–I3 2 (S1, S0) Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3

8×1 MUX I0–I7 3 (S2, S1, S0) Built from two 4×1 MUX + one 2×1 MUX

16×1 MUX I0–I15 4 (S3–S0) Built from two 8×1 MUX + one 2×1 MUX

4×1 MUX Truth Table

S1 S0 Output (Y)

0 0 I0

0 1 I1

1 0 I2

1 1 I3
 EXAM TIP: Know how higher-order MUX is built from lower-order: 8×1 = two 4×1 + one 2×1 (S2 controls 2×1).
MUX Boolean expression for 4×1 is frequently asked. MUX = data selector.

04 Topic 4: Sequential Logic Circuits

Definition: Circuits whose output depends on current inputs AND past state (memory). Require a clock signal.

4a. Latch
• Level-triggered memory device — output changes immediately when input changes.
• Has SET and RESET inputs, and two complementary outputs (Q and Q').
• No clock signal required (asynchronous).
• Example: SR Latch — built from NOR or NAND gates.

4b. SR Flip-Flop (Set-Reset)

• Two inputs: S (Set) and R (Reset). Two outputs: Q and Q'.
• S=1, R=0 → Q=1 (Set). S=0, R=1 → Q=0 (Reset).
• S=0, R=0 → No change (holds previous state).
• Invalid state: S=1, R=1 → Unpredictable output. Must be avoided.
• Edge-triggered (unlike latch which is level-triggered).

Truth Table — SR Flip-Flop

S R Q(n+1) Comment

0 0 Q(n) No change

0 1 0 Reset

1 0 1 Set

1 1 ? Invalid!

4c. JK Flip-Flop (most important)

• Improved version of SR Flip-Flop — eliminates the invalid state.
• Two inputs: J (Set) and K (Reset). Two outputs: Q and Q'.
• Has two modes: synchronous (state changes with clock) and asynchronous.
• Uses two 3-input NAND gates. Outputs Q and Q' are fed back to inputs.
• Circuit contains CLK (clock), CLR (clear/reset), and PR (preset) pins.

Truth Table — JK Flip-Flop

J K Q(n+1) State

0 0 Q(n) No change

0 1 0 Reset

1 0 1 Set

1 1 Q'(n) Toggle

J=0, K=0 → No Change: J=0, K=1 → Reset: J=1, K=0 → Set: J=1, K=1 → Toggle:
Q(n+1) = Q(n) Q(n+1) = 0 Q(n+1) = 1 Q(n+1) = Q'(n)

Applications of JK Flip-Flop:
• Counters — binary synchronous and asynchronous counters.
• Shift Registers — for serial-to-parallel or parallel-to-serial data conversion.
• Memory Units — can act as basic RAM when chained.

Advantages: Versatile, toggle functionality, works in both sync/async modes.

Disadvantages: More complex than D/T flip-flops, propagation delay, race problem.

4d. D Flip-Flop (Data / Delay)

• Simplest flip-flop. One input: D. Two outputs: Q and Q'.
• Whatever is on D gets copied to Q on the active clock edge.
• Created by modifying SR flip-flop: S=D, R=D' (eliminates invalid state).
• When CLK=HIGH → Q follows D. When CLK=LOW → Q holds previous value.

Truth Table — D Flip-Flop

D Q(n+1) Comment

0 0 Reset (output follows input)

1 1 Set (output follows input)

Applications: Memory registers, data storage, counters, synchronous systems.

4e. T Flip-Flop (Toggle)

• One input: T. Two outputs: Q and Q'.
• T=0 → No change. T=1 → Output toggles (flips).
• Useful for counters and frequency dividers.

Truth Table — T Flip-Flop

T Q(n+1) Comment

0 Q(n) No change

1 Q'(n) Toggle

Flip-Flop vs Latch — Comparison

Feature Flip-Flop Latch

Trigger type Edge-triggered Level-triggered

Clock signal Always required Not required

Output change Only at clock edge Immediately with input

Used in Synchronous circuits Asynchronous circuits

Examples SR, JK, D, T SR Latch, D Latch

Built from Gates (NOR, NAND, etc.) Gates

Building relation Can be built from latches Can be built from gates

EXAM TIP: JK Flip-Flop is the most tested sequential circuit. Memorise all 4 states: No Change (0,0), Reset (0,1),
Set (1,0), Toggle (1,1). Key difference from latch: flip-flop is EDGE-triggered, latch is
LEVEL-triggered.

Quick Reference Card

Circuit Gates Used Key Expression Remember

Half Adder XOR + AND Sum = A XOR B, Carry = AB 2 inputs, no carry-in

Full Adder 2 XOR + 2 AND + OR Sum = A XOR B XOR Cin 3 inputs, has carry-in
 Priority encoder for multiple active
Encoder OR gates 2N inputs → N outputs
inputs

Decoder AND gates + inverters N inputs → 2N outputs 3-to-8 decoder has 8 AND gates

MUX AND + OR + NOT Y = f(select lines, inputs) n select lines → 2n inputs

SR Flip-Flop NAND/NOR S=R=1 invalid Avoid S=R=1

JK Flip-Flop 3-input NAND J=K=1 → Toggle No invalid state

D Flip-Flop Modified SR Q(n+1) = D Simplest; output copies input

T Flip-Flop Modified JK T=1 → Q flips Used in counters

Good luck on your exam!