Memory Organisation in Computer Architecture

Memory organization is essential for efficient data processing and storage. The memory hierarchy
ensures quick access to data by the CPU, while larger, slower storage devices hold data for the
long term. Effective memory management ensures the system operates efficiently, providing
programs with the memory they need and preventing unnecessary delays in processing.

Types of Memory in a Computer System

Auxiliary Memory (Non-Volatile)

Devices that provide secondary or backup storage are called auxiliary memory. For
example, Magnetic disks and tapes are commonly used auxiliary devices. It is not directly
accessible to the CPU, is accessed using the Input/Output channels.

 Hard Disk Drive (HDD): A permanent storage device that holds large amounts of data even
when the computer is turned off. It is slower than RAM but offers much more capacity.
 Solid-State Drive (SSD): A faster alternative to HDDs with no moving parts. SSDs provide faster
read/write speeds compared to HDDs.
 Optical Discs and USB Flash Drives: Optical discs and USB flash drives are other forms of
secondary memory used for storage, though they are less common in modern high-speed
systems.

Main Memory (Volatile)

The memory unit that communicates directly within the CPU, Cache memory is called main
memory. It is fast memory used to store data during computer operations. Main memory is made
up of RAM and ROM, majority part consists of RAM.

RAM Random Access Memory

 DRAM: Dynamic RAM, is made of capacitors and transistors. It is slower and cheaper than
SRAM.
 SRAM: Static RAM, retains data, until powered off.

ROM Read Only Memory

Read Only Memory, is non-volatile and is more like a permanent storage for information. It also
stores the bootstrap loader program, to load and start the operating system when computer is
turned on. PROM (Programmable ROM), EPROM (Erasable PROM) and EEPROM (Electrically
Erasable PROM) are some commonly used ROMs.

Cache Memory
The cache memory is used to store program data that is currently being executed in the CPU.
Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not
found in cache memory then the CPU moves onto the main memory.

Registers
These are small, ultra-fast memory locations within the CPU used to hold data that is being
processed. Registers are crucial for executing instructions efficiently.
Tertiary and Offline Memory
 Tertiary memory refers to storage devices used for backups and archives, like magnetic tapes.
 Offline memory is storage that is not directly accessible by the computer (e.g., external hard
drives, optical discs) but data can be retrieved when connected.
Other Types of Memory Based on Storage Time

Volatile Memory: This loses its data, when power is switched off.

Non-Volatile Memory: This is a permanent storage and does not lose any data when power is
switched off.

Memory Organization

 Program Load: When a program is executed, it is loaded from secondary storage (HDD/SSD)
into main memory (RAM). It may also be loaded partially into cache memory to speed up
execution.

 Accessing Data: The CPU accesses data through registers and cache for quick computations. If
the data is not in the cache, it will fetch it from RAM. If it’s not in RAM either, it will fetch it
from secondary storage.

 Swapping and Virtual Memory: If the system runs out of physical RAM, parts of the program
(pages) may be swapped out to secondary storage. This process, known as paging, is managed
by the operating system’s memory manager.

Memory Mapping

Modern computers have a virtual memory that is not physically present. We can achieve it by
setting up a Hard disk, this way extended memory is called virtual memory. So any program that is
inside the computer will have a virtual memory address to store data. This data cannot be used
unless it is converted to a physical address. So, In short, Memory Mapping is the process done by
the Operating System to translate Virtual memory addresses to physical addresses. So, the
program can run anytime when the OS loads it as it is required.

How It Works

 Each process has its own virtual address space.

 The Memory Management Unit (MMU) translates virtual addresses → physical addresses.
 The OS maintains a page table that stores these mappings.
 Files or devices can also be memory-mapped, meaning the file’s contents are loaded into
the virtual address space, and the program can read/write to it as if it were normal memory.

Cache Memory in Computer Organization

Cache memory is a small, high-speed storage area in a computer. It stores copies of the data from
frequently used main memory locations. There are various independent caches in a CPU, which
store instructions and data.

 The most important use of cache memory is that it is used to reduce the average time to
access data from the main memory.
 The concept of cache works because there exists locality of reference (the same items or
nearby items are more likely to be accessed next) in processes.

By storing this information closer to the CPU, cache memory helps speed up the overall processing
time. Cache memory is much faster than the main memory (RAM). When the CPU needs data, it
first checks the cache. If the data is there, the CPU can access it quickly. If not, it must fetch the
data from the slower main memory.

Characteristics of Cache Memory

 Extremely fast memory type that acts as a buffer between RAM and the CPU.
 Holds frequently requested data and instructions, ensuring that they are immediately
available to the CPU when needed.
 Costlier than main memory or disk memory but more economical than CPU registers.
 Used to speed up processing and synchronize with the high-speed CPU.

Levels of Memory
Level 1 or Register: It is a type of memory in which data is stored and accepted that are
immediately stored in the CPU. The most commonly used register is Accumulator, Program
counter, Address Register, etc.

Level 2 or Cache memory: It is the fastest memory that has faster access time where data is
temporarily stored for faster access.

Level 3 or Main Memory: It is the memory on which the computer works currently. It is small in
size and once power is off data no longer stays in this memory.

Level 4 or Secondary Memory: It is external memory that is not as fast as the main memory but
data stays permanently in this memory.

Cache Performance

When the processor needs to read or write a location in the main memory, it first checks for a
corresponding entry in the cache.

 If the processor finds that the memory location is in the cache, a Cache Hit has occurred
and data is read from the cache.
 If the processor does not find the memory location in the cache, a cache miss has
occurred. For a cache miss, the cache allocates a new entry and copies in data from the
main memory, then the request is fulfilled from the contents of the cache.

The performance of cache memory is frequently measured in terms of a quantity called Hit ratio.

Hit Ratio(H) = hit / (hit + miss) = no. of hits/total accesses

Miss Ratio = miss / (hit + miss) = no. of miss/total accesses = 1 - hit ratio(H)

We can improve Cache performance using higher cache block size, and higher associativity, reduce
miss rate, reduce miss penalty, and reduce the time to hit in the cache.

Cache Mapping

Cache mapping refers to the method used to store data from main memory into the cache. It
determines how data from memory is mapped to specific locations in the cache.

There are three different types of mapping used for the purpose of cache memory which is as
follows:

 Direct Mapping
 Fully Associative Mapping
 Set-Associative Mapping
1. Direct Mapping

Direct mapping is a simple and commonly used cache mapping technique where each block of
main memory is mapped to exactly one location in the cache called cache line. If two memory
blocks map to the same cache line, one will overwrite the other, leading to potential cache misses.
Direct mapping's performance is directly proportional to the Hit ratio.

Memory block is assigned to cache line using the formula below:

i = j modulo m = j % m

where,

i = cache line number

j = main memory block number

m = number of lines in the cache

For example, consider a memory with 8 blocks(j) and a cache with 4 lines(m). Using direct
mapping, block 0 of memory might be stored in cache line 0, block 1 in line 1, block 2 in line 2, and
block 3 in line 3. If block 4 of memory is accessed, it would be mapped to cache line 0 (as i = j
modulo m i.e. i = 4 % 4 = 0), replacing memory block 0.

The Main Memory consists of memory blocks and these blocks are made up of fixed number of
words. A typical address in main memory is split into two parts:

 Index Field: It represent the block number. Index Field bits tells us the location of block
where a word can be.
 Block Offset: It represent words in a memory block. These bits determines the location of
word in a memory block.

The Cache Memory consists of cache lines. These cache lines has same size as memory blocks. The
address in cache memory consists of:

 Block Offset: This is the same block offset we use in Main Memory.
 Index: It represent cache line number. This part of the memory address determines which
cache line (or slot) the data will be placed in.
 Tag: The Tag is the remaining part of the address that uniquely identifies which block is
currently occupying the cache line.
The index field in main memory maps directly to the index in cache memory, which determines
the cache line where the block will be stored. The block offset in both main memory and cache
memory indicates the exact word within the block. In the cache, the tag identifies which memory
block is currently stored in the cache line. This mapping ensures that each memory block is
mapped to exactly one cache line, and the data is accessed using the tag and index while the block
offset specifies the exact word in the block.

2. Fully Associative Mapping

Fully associative mapping is a type of cache mapping where any block of main memory can be
stored in any cache line. Unlike direct-mapped cache, where each memory block is restricted to a
specific cache line based on its index, fully associative mapping gives the cache the flexibility to
place a memory block in any available cache line. This improves the hit ratio but requires a more
complex system for searching and managing cache lines

The address structure of Cache Memory is different in fully associative mapping from direct
mapping. In fully associative mapping, the cache does not have an index field. It only have a tag
which is same as Index Field in memory address. Any block of memory can be placed in any cache
line. This flexibility means that there’s no fixed position for memory blocks in the cache.

To determine whether a block is present in the cache, the tag is compared with the tags stored in
all cache lines. If a match is found, it is a cache hit, and the data is retrieved from that cache line. If
no match is found, it's a cache miss, and the required data is fetched from main memory.

3. Set-Associative Mapping

Set-associative mapping is a compromise between direct-mapped and fully-associative mapping in

cache systems. It combines the flexibility of fully associative mapping with the efficiency of direct
mapping. In this scheme, multiple cache lines (typically 2, 4, or more) are grouped into sets.

v=m/k

where,

m = number of cache lines in the cache memory

k = number of cache lines we want in each set

v = number of sets

Like direct mapping, now each memory block can be placed into any cache line within a specific
set.

i = j modulo v = j % v

where,
j = main memory block number

v = number of sets

i = cache line set number

This reduces the conflict misses that occur in direct mapping while still limiting the search space
compared to fully-associative mapping.

For example, consider a 2-way set associative cache, which means 2 cache lines make a set in this
cache structure. There are 8 memory blocks and 4 cache lines, thus the number of sets will be 4/2
= 2 sets. Using direct mapping strategy first, block 0 will be in set 0, block 1 in set 1, block 2 in set 2
and so on. Then, the tag is used to search through all cache lines in that set to find the correct
block (Associative Mapping).

Application of Cache Memory

Here are some of the applications of Cache Memory.

Primary Cache: A primary cache is always located on the processor chip. This cache is small and its
access time is comparable to that of processor registers.

Secondary Cache: Secondary cache is placed between the primary cache and the rest of the
memory. It is referred to as the level 2 (L2) cache. Often, the Level 2 cache is also housed on the
processor chip.

Spatial Locality of Reference: Spatial Locality of Reference says that there is a chance that the
element will be present in close proximity to the reference point and next time if again searched
then more close proximity to the point of reference.

Temporal Locality of Reference: Temporal Locality of Reference uses the Least recently used
algorithm will be used. Whenever there is page fault occurs within a word will not only load the
word in the main memory but the complete page fault will be loaded because the spatial locality
of reference rule says that if you are referring to any word next word will be referred to in its
register that's why we load complete page table so the complete block will be loaded.

Advantages

 Cache Memory is faster in comparison to main memory and secondary memory.

 Programs stored by Cache Memory can be executed in less time.
 The data access time of Cache Memory is less than that of the main memory.
 Cache Memory stored data and instructions that are regularly used by the CPU, therefore
it increases the performance of the CPU.

Disadvantages

 Cache Memory is costlier than primary memory and secondary memory .

 Data is stored on a temporary basis in Cache Memory.
 Whenever the system is turned off, data and instructions stored in cache memory get
destroyed.
 The high cost of cache memory increases the price of the Computer System.

Virtual Memory

Virtual memory is a memory management technique used by operating systems to give the
appearance of a large, continuous block of memory to applications, even if the physical memory
(RAM) is limited and not necessarily allocated in contiguous manner. The main idea is to divide the
process in pages, use disk space to move out the pages if space in main memory is required and
bring back the pages when needed.

Objectives of Virtual Memory

 A program doesn’t need to be fully loaded in memory to run. Only the needed parts are
loaded.

 Programs can be bigger than the physical memory available in the system.

 Virtual memory creates the illusion of a large memory, even if the actual memory (RAM) is
small.
  It uses both RAM and disk storage to manage memory, loading only parts of programs into
RAM as needed.

 This allows the system to run more programs at once and manage memory more
efficiently.

How Virtual Memory Works

Virtual memory uses both hardware and software to manage memory.

When a program runs, it uses virtual addresses (not real memory locations).

The computer system converts these virtual addresses into physical addresses (actual locations in
RAM) while the program runs.

Types of Virtual Memory

In a computer, virtual memory is managed by the Memory Management Unit (MMU), which is
often built into the CPU. The CPU generates virtual addresses that the MMU translates into
physical addresses. There are two main types of virtual memory:

1. Paging

Paging divides memory into small fixed-size blocks called pages. When the computer runs out of
RAM, pages that aren't currently in use are moved to the hard drive, into an area called a swap
file. Here,
  The swap file acts as an extension of RAM.
 When a page is needed again, it is swapped back into RAM, a process known as page
swapping.
 This ensures that the operating system (OS) and applications have enough memory to run.

Page Fault Service Time: The time taken to service the page fault is called page fault service time.
The page fault service time includes the time taken to perform all the above six steps.

 Let Main memory access time is: mm

 Page fault service time is: ss
 Page fault rate is : pp
 Then, Effective memory access time = (p∗s)+(1−p)∗m

Page and Frame: Page is a fixed size block of data in virtual memory and a frame is a fixed size
block of physical memory in RAM where these pages are loaded.

 Think of a page as a piece of a puzzle (virtual memory) While, a frame as the spot where it
fits on the board (physical memory).
 When a program runs its pages are mapped to available frames so the program can run
even if the program size is larger than physical memory.

2. Segmentation

Segmentation divides virtual memory into segments of different sizes. Segments that aren't
currently needed can be moved to the hard drive. Here,

 The system uses a segment table to keep track of each segment's status, including
whether it's in memory, if it's been modified and its physical address.
 Segments are mapped into a process's address space only when needed.

Applications of Virtual memory

Virtual memory has the following important characteristics that increase the capabilities of the
computer system.

Increased Effective Memory: It enables a computer to have more memory than the physical
memory using the disk space. This allows for the running of larger applications.

Memory Isolation: Virtual memory allocates a unique address space to each process, such
separation increases safety and reliability based on the fact that one process cannot interact with
another.

Efficient Memory Management: Virtual memory also helps in better utilization of the physical
memories through methods that include paging and segmentation.

Simplified Program Development: For case of programmers, they can program ‘as if’ there is one
big block of memory and this makes the programming easier and more efficient in delivering more
complex applications.

Associative Memory
Associative memory is also known as content addressable memory (CAM) or associative storage
or associative array. It is a special type of memory that is optimized for performing searches
through data, as opposed to providing a simple direct access to the data based on the address.

It can store the set of patterns as memories when the associative memory is being presented with
a key pattern, it responds by producing one of the stored pattern which closely resembles or
relates to the key pattern.

It can be viewed as data correlation here. input data is correlated with that of stored data in the
CAM.

It forms of two type:

1. auto associative memory network : An auto-associative memory network, also known as a

recurrent neural network, is a type of associative memory that is used to recall a pattern
from partial or degraded inputs. In an auto-associative network, the output of the network
is fed back into the input, allowing the network to learn and remember the patterns it has
been trained on. This type of memory network is commonly used in applications such as
speech and image recognition, where the input data may be incomplete or noisy.

2. hetero associative memory network : A hetero-associative memory network is a type of

associative memory that is used to associate one set of patterns with another. In a hetero-
associative network, the input pattern is associated with a different output pattern,
allowing the network to learn and remember the associations between the two sets of
patterns. This type of memory network is commonly used in applications such as data
compression and data retrieval.

Associative memory of conventional semiconductor memory (usually RAM) with added

comparison circuity that enables a search operation to complete in a single clock cycle. It is a
hardware search engine, a special type of computer memory used in certain very high searching
applications.

Associative memory, or content-addressable memory, allows data to be accessed based on

content rather than location. It's particularly useful in high-speed searching applications.

How Does Associative Memory Work?

In conventional memory, data is stored in specific locations, called addresses, and retrieved by
referencing those addresses. In associative memory, data is stored together with additional tags or
metadata that describe its content. When a search is performed, the associative memory
compares the search query with the tags of all stored data, and retrieves the data that matches
the query.

Associative memory is designed to quickly find matching data, even when the search query is
incomplete or imprecise. This is achieved by using parallel processing techniques, where multiple
search queries can be performed simultaneously. The search is also performed in a single step, as
opposed to conventional memory where multiple steps are required to locate the data.
Argument Register: It contains words to be searched. It contains 'n' number of bits.

Match Register: It has m-bits, One bit corresponding to each word in the memory array. After the
making process, the bits corresponding to matching words in match register are set to '1'.

Key Register: It provides a mask of choosing a particular field/key in argument register. It specifies
which part of the argument word need to be compared with words in memory.

Associative Memory Array: It combines word in that are to be compared with the arguments word
in parallel. It contains 'm' words with 'n' bit per word.

Applications of Associative memory :-

 It can be only used in memory allocation format.

 It is widely used in the database management systems, etc.
 Networking: Associative memory is used in network routing tables to quickly find the path
to a destination network based on its address.
 Image processing: Associative memory is used in image processing applications to search
for specific features or patterns within an image.
 Artificial intelligence: Associative memory is used in artificial intelligence applications such
as expert systems and pattern recognition.
 Database management: Associative memory can be used in database management
systems to quickly retrieve data based on its content.

Advantages of Associative memory :-

  It is used where search time needs to be less or short.
 It is suitable for parallel searches.
 It is often used to speedup databases.
 It is used in page tables used by the virtual memory and used in neural networks.

Disadvantages of Associative memory :-

 It is more expensive than RAM

 Each cell must have storage capability and logical circuits for matching its content with
external argument.

Memory Management Unit(MMU)/Memory Mnagement hardware

A Memory Management Unit (MMU) is a very important type of internal hardware. It is used for
high efficiency and secure utilization of a computer's memory devices. Another name for it is a
paged memory management unit (PMMU). The main purpose of an MMU is to serve as a link or
bridge between the physical memory of the computer and the central processing unit (CPU).
It is important for the smooth operation of programs and effective management of data. Let us
explore about MMUs in more detail in this article. This article will define an MMU, and cover some
key terminologies. Finally, we’ll finish up the article with some information on the Importance of
MMUs, and frequently asked questions along with its diagrams and more.
What is a Memory Management Unit (MMU)?
MMU stands for Memory management unit also known as PMMU (paged memory management
unit), Every computer system has a memory management unit , it is a hardware component whose
main purpose is to convert virtual addresses created by the CPU into physical addresses in the
computer's memory. In simple words, it is responsible for memory management In a device as it acts
as a bridge between the CPU and the RAM, which ensures that programs can run smoothly and
access the required data without clashes or unauthorized access. It is usually integrated in the
processor but in some cases it also constructed as a separate Integrated circuit (IC).

Key Terminologies of MMU

Few key terms are mentioned below:

 Virtual Address: The address generated by the CPU during program execution, representing a
location in the virtual address space.
 Physical Address: The physical memory address of a virtual address on a computer, as
determined by address translation performed by the MMU.
 Memory Paging: It is a technique used to manage memory which allows a computer to share its
memory resources by storing some portion of process on disk or other secondary memory.
 Address Translation: The method by which the MMU converts virtual addresses into physical
addresses so that the CPU can access the appropriate places in the computer's memory.
 Cache Memory: It is a high speed and Quick-access data storage layer, small-sized memory that
speeds up CPU operations by storing frequently used data or instructions for fast processing.
MMUs may interact with the cache to optimize memory access.

Functions of Memory Management Unit(MMU)

With the growth of technology the function of Memory Management Unit (MMU) is in its role in
address translation, memory protection, virtual memory management, and how it becomes the
backbone of multitasking in modern operating systems. So lets get into it to know some of the
functions of a Memory Management Unit we have classified some of them below.
 Address Translation: An MMU's primary job is to converting virtual addresses into physical
addresses. The MMU converts virtual addresses created by running programs to corresponding
physical addresses in the computer's memory. This translation is essential for the CPU to access
the correct locations in RAM and interact with the necessary data.
 Memory Protection: MMUs also play a crucial role in implementing memory protection
mechanisms. By implementing access control rules and regulations, they stop illegal usage of
particular memory locations. By doing this, the operating system's security and data integrity are
ensured.
 Virtual Memory Management: MMUs serves a part in the implementation of this method,
which allows heavier programs to be executed than what can fit in the physical RAM. The system
can use virtual memory to extend RAM by using a portion of the storage space on the disc and
dynamically switch data between RAM and the disc as needed.
 Memory Segmentation: Memory segmentation is a feature found in certain MMUs. It splits the
computer's memory into sections that have multiple authorizations and features. This
segmentation provides a more granular control over memory access and aids in optimizing
memory utilization.

Importance of Memory Management Unit(MMU)

 Efficient Memory Utilization: By dynamically controlling the mapping between virtual and
physical addresses, MMUs allow for the efficient use of memory resources. This eliminates the
need for conflicts when running multiple programs simultaneously, each with its own virtual
address space.
 Enhanced Security: The MMUs key role in Memory protection is very beneficial as its
mechanisms is enforced by contribute to system security by preventing unauthorized access to
critical regions of memory or we can also detect any software bugs by any fault in it. This helps
safeguard the integrity of the operating system and data of the user.
 Virtual Memory Support: As MMUs provide virtual memory management, which is supported
by this memory hardware, larger programs can be executed than what the physical RAM can
hold. Due to increased stability, this facilitates multitasking and improves system performance
overall.
 Facilitating Operating System Functions: MMUs play a vital role in supporting the functions of
modern operating systems, enabling features such as process isolation, multitasking,
and dynamic memory allocation.
I/O organization
Input-Output Interface

Input-Output Interface is used as a method which helps in transferring of information between the
internal storage devices i.e. memory and the external peripheral device . A peripheral device is
that which provide input and output for the computer, it is also called Input-Output devices. For
Example: A keyboard and mouse provide Input to the computer are called input devices while a
monitor and printer that provide output to the computer are called output devices. Just like the
external hard-drives, there is also availability of some peripheral devices which are able to provide
both input and output.

In micro-computer base system, the only purpose of peripheral devices is just to provide special
communication links for the interfacing them with the CPU. To resolve the differences between
peripheral devices and CPU, there is a special need for communication links.

The major differences are as follows:

1. The nature of peripheral devices is electromagnetic and electro-mechanical. The nature of

the CPU is electronic. There is a lot of difference in the mode of operation of both peripheral
devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of peripheral
devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the CPU and
memory.
4. The operating mode of peripheral devices are different and each may be controlled so as not
to disturb the operation of other peripheral devices connected to CPU.
5. There is a special need of the additional hardware to resolve the differences between CPU
and peripheral devices to supervise and synchronize all input and output devices.

Functions of Input-Output Interface:

 It is used to synchronize the operating speed of CPU with respect to input-output devices.
 It selects the input-output device which is appropriate for the interpretation of the input-
output signal.
  It is capable of providing signals like control and timing signals.
 In this data buffering can be possible through data bus.
 There are various error detectors.
 It converts serial data into parallel data and vice-versa.
 It also convert digital data into analog signal and vice-versa.

I/O Interface (Interrupt and DMA Mode)

The method that is used to transfer information between internal storage and external I/O devices is
known as I/O interface. The CPU is interfaced using special communication links by the peripherals
connected to any computer system. These communication links are used to resolve the differences
between CPU and peripheral.
Synchronous Data Transfer
 All data transfers occur simultaneously during the
occurrence of a clock pulse.
 Registers in the interface share a common clock with
CPU registers
Asynchronous Data Transfer
 Internal timing in each unit (CPU and Interface) is
independent
 Each unit uses its own private clock for internal registers
Mode of Transfer

The binary information that is received from an external device is usually stored in the memory
unit. CPU merely processes the information but the source and target is always the memory unit.
Data transfer between CPU and the I/O devices may be done in different modes:

1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).

Programmed I/O

 In this each data item transfer is initiated by an instruction in the program

 Usually the transfer is from a CPU register and memory. In this case it requires constant
monitoring by the CPU of the peripheral devices.
 In this case, the I/O device does not have direct access to the memory unit. A transfer from I/O
device to memory requires the execution of several instructions by the CPU
 Including an input instruction to transfer the data from device to the CPU and store instruction
to transfer the data from CPU to memory.
Note: The CPU stays in the program loop until the I/O unit indicates that it is ready for data
transfer. This keeps the CPU busy & can be avoided by using an interrupt facility.

Interrupt-Initiated I/O
Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well be
avoided by using an interrupt driven method for data transfer. By using interrupt facility and
special commands to inform the interface to issue an interrupt request signal whenever data is
available from any device.
Steps:
 In the meantime the CPU can proceed for any other program execution.
 The interface meanwhile keeps monitoring the device.
 Whenever it is determined that the device is ready for data transfer it initiates an interrupt
request signal to the computer.
 Upon detection of an external interrupt signal the CPU stops momentarily the task that it was
already performing, branches to the service program to process the I/O transfer and then
return to the task it was originally performing.
 The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be
executed for each I/O transfer.

Interrupt-driven I/O

Types of Interrupts:
 Hardware vs Software: Hardware interrupts come from external devices, while software
interrupts are generated by program instructions.
 Vectored vs Non-Vectored: Vectored have fixed addresses; non-vectored use dynamic
addresses at runtime.
 Maskable vs Non-Maskable: Maskable can be enabled/disabled; non-maskable are always
active for critical events.
 External vs Internal: External are triggered by hardware (e.g., I/O devices); internal by the
processor (e.g., illegal instructions).
 Synchronous vs Asynchronous: Synchronous occur at predictable times; asynchronous are
triggered unpredictably by external events.

Direct Memory Access

The data transfer between a fast storage media such as magnetic disk and memory unit is limited
by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other
using the memory buses, removing the intervention of the CPU. This type of data transfer
technique is known as DMA or direct memory access.
 During DMA the CPU is idle and it has no control over the memory buses.
 The DMA controller takes over the buses to manage the transfer directly between the I/O
devices and the memory unit. Bus grant request time.
 Transfer the entire block of data at transfer rate of device because the device is usually slow
than the speed at which the data can be transferred to CPU.
 Release the control of the bus back to CPU So,
Total time taken to transfer the N bytes = Bus grant request time + (N) * (memory transfer rate) +
Bus release control time.
 Buffer the byte into the buffer & Inform the CPU that the device has 1 byte to transfer (i.e. bus
grant request)
 Transfer the byte (at system bus speed) & Release the control of the bus back to CPU

Difference between Programmed and Interrupt Initiated I/O

Programmed I/O Interrupt Initiated I/O

Data transfer is initiated by the means of

instructions stored in the computer program. The I/O transfer is initiated by the
Whenever there is a request for I/O transfer the interrupt command issued to the CPU.
instructions are executed from the program.

There is no need for the CPU to stay in

The CPU stays in the loop to know if the device is
the loop as the interrupt command
ready for transfer and has to continuously monitor
interrupts the CPU when the device is
the peripheral device.
ready for data transfer.

The CPU cycles are not wasted as CPU

This leads to the wastage of CPU cycles as CPU
continues with other work during this
remains busy needlessly and thus the efficiency of
time and hence this method is more
system gets reduced.
efficient.

CPU cannot do any work until the transfer is CPU can do any other work until it is
complete as it has to stay in the loop to interrupted by the command indicating
 Programmed I/O Interrupt Initiated I/O

continuously monitor the peripheral device. the readiness of device for data transfer

Its module is faster than programmed

Its module is treated as a slow module.
I/O module.

It can be tricky and complicated to

It is quite easy to program and understand. understand if one uses low level
language.

The performance of the system is severely The performance of the system is

degraded. enhanced to some extent.

Modes of DMA Transfer

Direct Memory Access (DMA):

DMA basically stands for Direct Memory Access. It is a process which enables data transfer
between the Memory and the IO (Input/ Output) device without the need of or you can say
without the involvement of CPU during data transfer.
Working of DMA:

Following list of points will describe briefly about DMA and its working as follows.
 For DMA, you basically need a hardware called DMAC (Direct Memory Access Controller)
which will help in the throughout process of data transfer between the Memory and IO device
directly.
 First what happens is IO device sends the DMA request to DMA Controller, then further DMAC
device sends HOLD signal to CPU by which it asks CPU for several information which are
needed while transferring data.
 CPU then shares two basic information with DMAC before the Data transfer which are:
Starting address (memory address starting from where data transfer should be performed)
and Data Count (no of bytes or words to be transferred).
 CPU then sends HLDACK (Hold Acknowledgement) back to DMAC illustrating that now DMAC
can successfully pass on the information.
 Then further DMAC shares the DMA ACK (DMA Acknowledgement) to the IO device which
would eventually let IO device to access or transfer the data from memory in a direct and
efficient manner.

Modes of DMA Transfer:

Now after getting some brief idea about DMA and its working it's the time to analyze Modes of
DMA Transfer.
 During the DMA Transfer CPU can perform only those operation in which it doesn't require the
access of System Bus which means mostly CPU will be in blocked state.
 For how much time CPU remains in the blocked state or we can say for how much time CPU
will give the control of DMAC of system buses will actually depend upon the following modes
of DMA Transfer and after that CPU will take back control of system buses from DMAC.
Mode-1:
Burst Mode -
 In this mode Burst of data (entire data or burst of block containing data) is transferred before
CPU takes control of the buses back from DMAC.
 This is the quickest mode of DMA Transfer since at once a huge amount of data is being
transferred.
 Since at once only the huge amount of data is being transferred so time will be saved in huge
amount.
Pros:
 Fastest mode of DMA Transfer
Cons:
 Less user friendly because during the DMA transfer CPU will be blocked.

Percentage of Time CPU remains blocked:

Let time taken to prepare the data be Tx and time taken to transfer the data be Ty. Then
percentage of time CPU remains blocked due to DMA is as follows.
Percentage of time CPU remains in blocked state = Ty * 100% / Tx + Ty

Mode-2:
Cycle Stealing Mode -
 Slow IO device will take some time to prepare data (or word) and within that time CPU keeps
the control of the buses.
 Once the data or the word is ready CPU give back control of system buses to DMAC for 1-cycle
in which the prepared word is transferred to memory.
 As compared to Burst mode this mode is little bit slowest since it requires little bit of time
which is actually consumed by IO device while preparing the data.
Pros:
 Most Efficient way for DMA Transfer.
 CPU won't be blocked entire time.
Cons:
 Rate of DMA Transfer will be less.
Percentage of Time CPU remains blocked:
Let time taken to prepare data be Tx and time taken to transfer the data be Ty. Then percentage
of time CPU remains blocked due to DMA is as follows.
Percentage of time CPU remains in blocked state = Ty * 100% /
Tx

Mode-3:
Interleaving Mode -
 Whenever CPU does not require the system buses then only control of buses will be given to
DMAC.
 In this mode, CPU will not be blocked due to DMA at all.
 This is the slowest mode of DMA Transfer since DMAC has to wait might be for so long time to
just even get the access of system buses from the CPU itself.
 Hence due to which less amount of data will be transferred.
Pros:
 CPU will not be blocked at all.
Cons:
 Slowest DMA transfer rate.
Since, DMA will use System Bus only when CPU is not using it So,

Percentage of time CPU remains in blocked state = 0%

Priority Interrupts | (S/W Polling and Daisy Chaining)

When I/O devices are ready for I/O transfer, they generate an interrupt request signal to the
computer. The CPU receives this signal, suspends the current instructions it is executing, and then
moves forward to service that transfer request. But what if multiple devices generate interrupts
simultaneously. In that case, we have a way to decide which interrupt is to be serviced first. In
other words, we have to set a priority among all the devices for systemic interrupt servicing. The
concept of defining the priority among devices so as to know which one is to be serviced first in
case of simultaneous requests is called a priority interrupt system. This could be done with either
software or hardware methods.

SOFTWARE METHOD – POLLING

In this method, all interrupts are serviced by branching to the same service program. This program
then checks with each device if it is the one generating the interrupt. The order of checking is
determined by the priority that has to be set. The device having the highest priority is checked first
and then devices are checked in descending order of priority. If the device is checked to be
generating the interrupt, another service program is called which works specifically for that
particular device.

The major disadvantage of this method is that it is quite slow. To overcome this, we can use
hardware solution, one of which involves connecting the devices in series. This is called Daisy-
chaining method.

HARDWARE METHOD – DAISY CHAINING

The daisy-chaining method involves connecting all the devices that can request an interrupt in a
serial manner. This configuration is governed by the priority of the devices. The device with the
highest priority is placed first followed by the second highest priority device and so on. The given
figure depicts this arrangement.

WORKING: There is an interrupt request line which is common to all the devices and goes into the
CPU.
 When no interrupts are pending, the line is in HIGH state. But if any of the devices raises an
interrupt, it places the interrupt request line in the LOW state.
 The CPU acknowledges this interrupt request from the line and then enables the interrupt
acknowledge line in response to the request.
 This signal is received at the PI(Priority in) input of device 1.
 If the device has not requested the interrupt, it passes this signal to the next device through its
PO(priority out) output. (PI = 1 & PO = 1)
 However, if the device had requested the interrupt, (PI =1 & PO = 0)
o The device consumes the acknowledge signal and block its further use by placing 0
at its PO(priority out) output.
o The device then proceeds to place its interrupt vector address(VAD) into the data
bus of CPU.
o The device puts its interrupt request signal in HIGH state to indicate its interrupt
has been taken care of.
 If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that
acknowledge signal has been blocked. (PI = 0 & PO = 0)
Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an
interrupt. Therefore, by daisy chain arrangement we have ensured that the highest priority
interrupt gets serviced first and have established a hierarchy. The farther a device is from the first
device, the lower its priority.
Priority interrupts:
Advantages:
1. Priority interrupts allow for the efficient handling of high-priority tasks that require immediate
attention. This is especially important in real-time systems where certain tasks must be
completed within strict time constraints.

2. They are more efficient than software polling as the processor does not waste time constantly
checking for events that have not occurred.

3. Priority interrupts are also more deterministic, as the response time to an event can be
accurately predicted based on its priority level.

Disadvantages:
1. One potential disadvantage of priority interrupts is the possibility of lower priority tasks being
starved of resources if high-priority tasks are continuously interrupting the processor.

2. If not implemented properly, priority interrupts can lead to priority inversion, where a low-
priority task holds a resource required by a higher-priority task, causing a delay in the high-
priority task's execution.

Software polling:
Advantages:
1. Software polling is relatively simple to implement and does not require specialized hardware.

2. It can be used to detect events that occur at irregular intervals, as the processor can check for
events whenever it is not performing other tasks.

Disadvantages:
1. Software polling is less efficient than priority interrupts as the processor must constantly
check for events even if none have occurred.

2. In real-time systems, software polling may not be suitable as it is difficult to guarantee the
response time to an event, especially if the processor is busy with other tasks.
Daisy chaining:
Advantages:
1. Daisy chaining allows multiple devices to share a single interrupt line, reducing the number of
interrupt lines required.

2. It is relatively simple to implement and does not require specialized hardware.

Disadvantages:
1. Daisy chaining can result in increased response time as each device must wait for the previous
device to complete its interrupt handling before it can start its own.

2. It can also be difficult to implement and troubleshoot, especially if there are multiple devices
on the same interrupt line.

Introduction of Input-Output Processor

The DMA mode of data transfer reduces the CPU's overhead when handling I/O operations. It also
allows parallel processing between CPU and I/O operations. This parallelism is necessary to avoid the
wastage of valuable CPU time when handling I/O devices whose speeds are much slower as
compared to CPU. The concept of DMA operation can be extended to further relieve the CPU from
getting involved with the execution of I/O operations. This led to the development of special
purpose processors called Input-Output Processors(IOPs) or IO channels.

The Input-Output Processor (IOP) is just like a CPU that handles the details of I/O operations. It is
more capable than typical DMA controller. The IOP can fetch and execute its own instructions that
are specifically designed to characterize I/O transfers. In addition to the I/O tasks, it can also perform
other processing tasks like arithmetic, logic, branching, and code translation. The main memory unit
plays a pivotal role. It communicates with the processor via DMA.

Working of Input-Output Processor

The Input-Output Processor is a specialized processor which loads and stores data in memory along
with the execution of I/O instructions. It serves as an interface between the system and devices. It
follows the given below sequence of steps to perform I/O operations and then store the results in
memory:

1. The I/O processor is triggered by a request from the system or peripheral device to initiate
an I/O operation.

2. It fetches instructions specifically designed for I/O transfers from its own instruction set.

3. Memory space is allocated in the main memory to hold the data being transferred.

4. Direct Memory Access (DMA) is used to transfer data directly between the I/O device and
memory bypassing the CPU.

5. Data is buffered temporarily between the I/O device and memory to ensure efficient
processing.

6. I/O commands, such as read, write, or synchronize, are executed to control the data transfer
process.

7. If errors occur, interrupts are handled and error corrections are managed independently.

8. Once the data transfer is complete, the results are stored in memory and the operation is
marked as complete.

9. The system or peripheral device is informed that the I/O operation has been completed and
the results are available.

10. After the I/O operation, control of the resources is released and the CPU resumes processing
other tasks.

Features of an Input-Output Processor

 An IOP is equipped with specialized hardware that is optimized for handling input/output
operations. This hardware includes input/output ports, DMA controllers, and interrupt
controllers.

 It has the capability to perform Direct Memory Access (DMA) operations. DMA allows data
to be transferred directly between peripheral devices and memory without going through
the CPU, thereby freeing up the CPU for other tasks.

 It can handle interrupts from peripheral devices and manage them independently of the
CPU. This allows the CPU to focus on executing application programs while the IOP handles
interrupts from peripheral devices.

 It can handle communication protocols (Ethernet, USB, SCSI) to interface with devices,
reducing the need for CPU intervention.

 It can buffer data between CPU and peripherals to prevent overload and improve data
handling.

 It can process commands from peripheral devices independently of the CPU. This allows the
CPU to focus on executing application programs tasks.

 It can perform input/output operations in parallel with the CPU. This allows the system to
handle multiple tasks simultaneously and improve overall system performance.
Applications of I/O Processors

 I/O processors can be used in data acquisition systems to handle real-time data transfer and
processing.

 They can be used in industrial control systems for precise timing, control signals, and local
data processing.

 They can handle multimedia I/O, including real-time data processing for audio, video, and
compression.

 They can process network data, including routing, filtering, and encryption.

 They can handle high-speed data transfers, caching, and prefetching for storage systems.

Advantages of Input-Output Processor

 The I/O devices can directly access the main memory without the intervention of the
processor in I/O processor-based systems.

 With an I/O processor, the main processor doesn't have to deal with I/O operations,
allowing it to focus on other tasks. This results in more efficient use of the processor's
resources and can lead to faster overall system performance.

 Since the I/O processor can access memory directly, data transfers between I/O devices and
memory can be faster and more efficient than with other methods.

 By offloading I/O tasks to a dedicated processor, the system can be made more fault-
tolerant. For example, if an I/O operation fails, it won't affect other system processes.

Disadvantages of Input-Output Processor

 I/O processors can add significant costs to a system due to the additional hardware and
complexity required. This can be a barrier to adoption, especially for smaller systems.

 The addition of an I/O processor can increase the overall complexity of a system, making it
more difficult to design, build, and maintain. This can also make it harder to diagnose and
troubleshoot issues.

 While I/O processors can improve system performance by offloading I/O tasks from the main
processor, the gains may not be significant in all cases. In some cases, the additional
overhead of the I/O processor may actually slow down the system.

 With multiple processors accessing the same memory, synchronization issues can arise,
leading to potential data corruption or other errors.

I/O controller

An I/O controller is a device (or part of a chipset) that controls data exchange between the
processor/memory and one or more I/O devices, ensuring smooth, efficient, and error-free
communication.

Without controllers, the CPU would have to handle every detail of communication (timing,
signaling, synchronization) directly — which would:
  Slow down processing
 Increase CPU load
 Cause errors due to speed mismatch

Hence, I/O controllers handle these low-level operations automatically.

Main Functions of I/O Controller

Function Description
Device Communication Manages command and data exchange between CPU and I/O
Control device.
Temporarily stores data to match speed differences between fast
Data Buffering
CPU and slow I/O devices.
Error Detection Detects and sometimes corrects transmission errors.
Address Decoding Determines which device the CPU wants to communicate with.
Interrupt Handling Sends interrupt signals to CPU when a device needs attention.
Control and Status
Holds device status, control commands, and data.
Registers

Types of I/O Controllers

Type Description / Example

Serial I/O Controller Manages serial devices (e.g., COM port, UART).
For parallel data transfer (e.g., printer port, old disk
Parallel I/O Controller
drives).
Manages HDDs or SSDs (e.g., SATA, NVMe
Disk Controller
controller).
Network Interface Controller Handles communication over network (Ethernet, Wi-
(NIC) Fi).
USB Controller Interfaces USB devices with system bus.
Graphics Controller Manages data between CPU and GPU/display.

Example of I/O Control Methods

Method Explanation
Programmed I/O CPU directly controls all I/O operations.
Interrupt-driven I/O Device signals CPU when it’s ready for data.
DMA (Direct Memory Controller transfers data between device and memory without
Access) CPU intervention.