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ET0023 Operating Systems Chapter 2: Computer

Hardware and OS Interface

In this chapter, you will be learning about how computer hardware components work
together and how the operating system manages and utilises these resources to provide
services to applications and users.

1. Learning Objectives
In this lesson, you will learn the following:

• Computer System Architecture

• How CPU works
• How CPU handle I/O events
• Computer Memory
• User Interfaces
• Functions of an Operating System

2. Computer System Architecture

2.1 Von Neumann Architecture
The modern computers are based on a stored-program concept introduced by John Von
Neumann. The term Von Neumann architecture describes a design architecture for an
electronic digital computer with subdivisions of a processing unit, a memory to store
both data and instructions, external mass storage, and input and output mechanisms.

Why this matters for OS: In this stored-program concept, programs and data are stored in
a separate storage unit called memories and are treated the same. This novel idea meant
that a computer built with this architecture would be much easier to reprogram.
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The Von Neumann architecture consists of:

• A central arithmetic unit to perform
arithmetic operations;
• A central control unit to sequence
operations performed by the machine;
• Memory that stores data and
instructions;
• An "outside recording medium" to
store input to and output from the
machine;

• Input and output mechanisms to transfer data between the memory and the outside
recording medium.

The processor is the heart of the computer, which accepts inputs from users and interfaces
with storage and memory controllers. It will execute certain outputs based on the user's
instructions.

3. The CPU
At the heart of the computer there is a unit called the Central Processing Unit (CPU), built
using VLSI.

You’ve probably heard of CPUs before. They’re made by companies like Intel, AMD and
Qualcomm, and have technical data associated with them such as Quad Core, 3.2GHz with
6MB of cache.

The CPU is driven by a clock/pulse generator to execute machine instructions, maintains the
"heartbeat" of the system, and controls operations.
The CPU can be further divided into three main parts: the Arithmetic Logic Unit (ALU), the
Control Unit (CU), and Registers.
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3.1 Registers
Registers are parts of the CPU that can store data. Accessing memory to get an instruction
or data word takes much longer than executing an instruction, CPUs contain some registers
inside to hold key variables and temporary results. Registers can’t hold as much data as RAM
can, but they operate considerably faster.

How OS Uses Registers: During a context switch, the OS saves all register contents of the
current process and loads the register contents of the next process. This allows multiple
processes to share the CPU while maintaining their individual execution states.

• Accumulator: Stores the results of calculations made by ALU.

• Program Counter (PC): Keeps track of the memory location of the next instructions
to be dealt with. The PC then passes this next address to Memory Address Register
(MAR).
• Memory Address Register (MAR): It stores the memory locations of instructions that
need to be fetched from memory or stored into memory.
• Memory Data Register (MDR): It stores instructions fetched from memory or any
data that is to be transferred to, and stored in, memory.
• Current Instruction Register (CIR): It stores the most recently fetched instructions
while it is waiting to be coded and executed.
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• Instruction Buffer Register (IBR): The instruction that is not to be executed

immediately is placed in the instruction buffer register IBR.

3.2 The Arithmetic Logic Unit (ALU)

The ALU is the core of the CPU. It is made up of all those logic circuits that we have been
learning about for the past three weeks.

The ALU uses these logic circuits to perform a variety of operations. It can perform addition

of binary numbers. It can also perform a variety of other arithmetic operations, such as
subtraction and incrementation. The ALU can also perform logical operations, such as

comparing two binary numbers to see if they are the same or not.

3.3 The Control Unit

The control unit decodes what each instruction means, and can then control how the other
components operate. So when the control unit receives an instruction, which is just a binary
number, it will then signal what the ALU and memory is supposed to do. It might be that the
instruction is to add two numbers together, or it might be that the instruction is to store a
number in RAM.

The control unit also contains a clock. This is a tiny oscillating crystal, which controls the rate
at which calculations are performed by the CPU.

4. Instruction Cycle
The fundamental operation of most CPUs, regardless of the physical form they take, is to
execute a sequence of stored instructions that is called a program. The instructions to be
executed are kept in some kind of computer memory.

The basic cycle of CPU is to fetch the first instruction from memory, decode it to determine
its type and operands, execute the instruction and then fetch, decode and execute
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subsequent instructions. The cycle is repeated until the program finishes.

① Fetch: The next instruction is fetched from the memory address that is currently

stored in the Program Counter (PC), and stored in the Instruction register (IR). At the
end of the fetch operation, the PC points to the next instruction that will be read at
the next cycle.

② Decode: The decoder interprets the instruction. During this cycle the instruction

inside the IR (instruction register) gets decoded.

③ Execute: The Control Unit of CPU passes the decoded information as a sequence of

control signals to the relevant function units of the CPU to perform the actions
required by the instruction such as reading values from registers, passing them to the
ALU to perform mathematical or logic functions on them, and writing the result back
to a register. If the ALU is involved, it sends a condition signal back to the CPU.

The result generated by the operation is stored in the main memory, or sent to an output
device. Based on the condition of any feedback from the ALU, Program Counter may be
updated to a different address from which the next instruction will be fetched.

5. Three-bus Architecture

5.1 System Bus Components

The system bus is the communication pathway that connects the CPU, memory, and I/O
devices. It consists of three distinct buses that work together to enable all system
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operations:

• Address bus: carry the addresses of memory to be accessed. OS uses this to specify
where data should be read from or written to.

• Data bus: carry the actual data to be transferred between components. OS manages
data flow through system calls and I/O operations.

• Control bus: carry the control signal to indicate the actual action to be performed,
either READ, WRITE, INTERRUPT, RESET, CLOCK. OS uses control signals to
coordinate hardware operations

Three-bus Architecture
Memory Input /
Processor
Output
devices

Memory bus

Data Bus

Control Bus

5.2 Bus Operations During Instruction Cycle

In each stage of instruction cycle, the involved buses could be various:

① Instruction Fetch

1. CPU places instruction address on Address Bus

2. CPU sends READ signal on Control Bus

3. Memory responds by placing instruction on Data Bus

4. CPU reads instruction from Data Bus

② Instruction Decode
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1. CPU interprets the fetched instruction which is stored in the Instruction Register (IR)

2. Control Unit decodes the opcode and generates internal control signals

3. No external buses are used. This phase is performed internally within the CPU.

③ Instruction Excute (if memory access needed)

1. CPU places data address on Address Bus

2. CPU sends READ/WRITE signal on Control Bus

3. Data transfers via Data Bus (to/from memory)

6. Program Execution
6.1 Basic Instruction Cycle
The basic instruction cycle is fetch and execute, shown in the following picture:

An opcode (operation code) is the portion of a machine language instruction that specifies
the operation to be performed. Apart from the opcode itself, an instruction normally also has

one or more specifiers for operands (i.e. data) on which the operation should act.

6.2 Program Execution

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Step 1: Program counter = 300, fetch the

content 1940 from memory location

300 into Instruction register IR

Step 2: Program counter = 301, decode the

instruction, a read operation, read

content 0003 from memory location

940 into accumulator register: AC= 3

Step 3: Program counter = 301, fetch the

content 5941 from memory location

301 into Instruction register IR

Step 4: Program counter = 302, decode the

instruction, an add operation, add

content 0002 from memory location

941 to AC: AC = 3 + 2 = 5

Step 5: Program counter = 302, fetch the content 2941 from memory location 302 into

Instruction register IR

Step 6: Program counter = 303, decode the instruction, a store operation, store content

0005 from AC into memory location 941.

7. How CPU Handle I/O Events

7.1 I/O Events Handling
We have many external devices attached to the CPU like a mouse, keyboard, scanner,
printer, etc. These devices also need CPU attention. Suppose a CPU is busy in displaying a
PDF and you click the window media player icon on the desktop. Though the CPU does not
have any idea when an event like this would occur, but it has to respond to such inputs from
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the I/O devices.

Interrupt and Polling are the two ways to handle the events generated by the devices that
can happen at any moment while CPU is busy in executing another process. Polling and
Interrupt lets the CPU stop what it is currently doing and respond to the more important
task.

7.2 Polling
Polling is a protocol that notifies CPU that a device needs its attention. Unlike in interrupt,
where device tells CPU that it needs CPU processing, in polling the CPU keeps asking the
I/O device whether it needs CPU processing.

In polling method, OS continuously checks device status. The CPU continuously polls the
devices to see if I/O devices is requesting services. Polling or busy waiting is simple but
inefficient. Polling has the disadvantage of tying up the CPU full time until all the I/O is
done. Polling is reasonable if jobs are few and short.

7.3 Interrupt
In systems programming, an interrupt is a signal to the processor emitted by hardware or
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software indicating an event that needs immediate attention.

An interrupt alerts OS to a high-priority condition requiring the interruption of the current

code the processor is executing, the current thread.

OS responds by suspending its current activities, saving its state, and executing a small
program called an interrupt handler (or interrupt
Interrupts
service routine, ISR) to deal with the event. This
Instruction 1
interruption is temporary, and after the interrupt
Instruction 2
Interrupt
handler finishes, OS resumes execution of the Interrupt Service Routine
Request Instruction 3
Service
previous thread. Such an interrupt request allows OS Save status
Service
to respond quickly and immediately, enabling it to Restore status
Finish
Instruction 4

continue its routine tasks without being tied down,

Instruction 5

until an interrupt request arrives.

7.4 Instruction Cycle with Interrupts

8. Memory Hierarchy
Ideally, memory should be extremely fast, abundantly large and very cheap. The memory
system is constructed as a hierarchy of layers. The top layers have higher speed and
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greater cost per bit while the lower layers have larger capacity at lower cost.
This Memory Hierarchy Design is divided into 2 main types:
• Internal Memory or Primary Memory
Comprising of Main Memory, Cache Memory & CPU registers. This is directly
accessible by the processor.
• External Memory or Secondary Memory
Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e. peripheral storage
devices which are accessible by the processor via I/O Module.

9. Types of Memory
9.1 Registers (Fastest, Smallest)
• Made of same material as the CPU thus just as fast
• CISC vs RISC systems (Complex Instruction Set Computer vs Reduced Instruction Set
Computer)
• How OS Manage it:
o OS cannot directly manage these but benefits from their speed during system
operations
o Context switching involves saving/restoring register contents

9.2 Cache Memory

• High-speed memory located close to the CPU
• Stores copies of frequently accessed blocks (cache lines) from main memory
• Exploits spatial and temporal locality (nearby and recently used data are likely
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reused)
• Cache includes tags to identify which block(s) of main memory are in the cache
• Cache Read Operations - Cache Miss /
Cache Hit
1) CPU requests contents of memory
location

2) Cache is checked for this data

3) If present, get from cache (fast)

4) If not present, read required block from

main memory to cache

5) Then deliver from cache to CPU

• How OS Manage it:

o Hardware-managed but OS-aware
o OS can optimise memory access patterns to improve cache performance
o Cache misses affect OS scheduling decisions

Please read the article below for additional information on how caching works.
How Caching Works | HowStuffWorks

9.3 Main Memory

The main memory in a computer system typically consists of two types:

• Volatile Memory:

• RAM (Random Access Memory): This is the primary working memory used by the
system to store data and instructions that the CPU needs for running applications and
processes. It is temporary and loses all stored data when the power is turned off.

There are two main types of RAM:

o DRAM (Dynamic RAM): Commonly used as the main memory in personal

computers. It needs to be refreshed periodically to retain data.
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o SRAM (Static RAM): Faster and more expensive than DRAM, often used for
cache memory inside the CPU.

The primary focus of OS memory management is to allocate, protect, and track memory
usage efficiently, while supporting virtual memory through hardware assistance.

• Non-Volatile Memory:

• ROM (Read-Only Memory): Stores permanent data, such as the system's BIOS or
firmware. Data in ROM is usually written during manufacturing and cannot be easily
modified.

Types of ROM include:

o PROM (Programmable ROM): Can be programmed once after manufacturing.

o EPROM (Erasable Programmable ROM): Can be erased with UV light and

reprogrammed.

o EEPROM (Electrically Erasable Programmable ROM): Can be erased and

reprogrammed electrically, and allows flexibility in updating systems,
commonly used for firmware updates.

• Flash Memory: A type of EEPROM that is faster and used in modern applications such
as SSDs (Solid-State Drives) and USB flash drives. It stores data even when the power
is off, making it a widely used form of non-volatile memory. It is used for OS storage,
file systems, and persistent data.

• How OS Manage it:

o Primary focus of OS memory management
o OS allocates, protects, and tracks memory usage
o Supports virtual memory through hardware assistance
•

9.4 Magnetic Storage (Slowest, Largest)

A disk consists of one or more metal platters which may be accessed on 1 or 2 surfaces.
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Each platter is divided into a number of concentric tracks. Each track is divided into sectors
which usually hold 512 bytes of data.

A cylinder is made up of a track on each of the platters at the same horizontal position.
Outside tracks may hold more information than inside tracks on a platter.

The platters spin at a high speed measured in RPM.

Access speed is the time taken for the Read/Write head to move from sector to another for
information. The amount of data that the drive can read/write is known as the data
access rate.

• How OS Manage it:

o OS manages it as virtual memory extension
o File system implementation
o Swap space for virtual memory

10. Direct Memory Access

10.1 Direct Memory Access
There are several memory access methods. Direct memory access (DMA) is a feature of
computer systems that allows certain hardware subsystems to access main system memory
(random-access memory) independent of the central processing unit (CPU).
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Without DMA, when the CPU is using programmed input/output, it is typically fully occupied
for the entire duration of the read or write operation, and is thus unavailable to perform
other work. With DMA, the CPU first initiates the transfer, then it does other operations
while the transfer is in progress, and it finally receives an interrupt from the DMA controller
(DMAC) when the operation is done. This feature is useful at any time that the CPU cannot
keep up with the rate of data transfer, or when the CPU needs to perform work while waiting
for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive
controllers, graphics cards, network cards and sound cards.

Simply put...
• DMA allows access to the system memory without CPU intervention
• Specific hardware is used to transfer data from I/O device to Memory (DMA
controller)
• Advantages:
o Overcomes slow I/O operations from the CPU
o Reduces CPU involvement in data transfers
o Allows OS to schedule other processes during I/O operations
o Improves overall system throughput
• Uses: Storage data transfers, Network transfers

Main techniques used in DMA are:

• Block DMA Requests (Burst Mode)
o Once the DMA controller gains the charge of the system bus, then it releases
the system bus only after completion of data transfer. Till then the CPU has
to wait for the system buses.
• Cycle Stealing Mode
o The DMA controller forces the CPU to stop its operation and relinquish the
control over the bus for a short term to DMA controller. After the transfer of
every byte, the DMA controller releases the bus and then again requests for
the system bus. In this way, the DMA controller steals the clock cycle for
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transferring every byte.

• Transparent mode
o The DMA controller takes the charge of system bus only if the processor does
not require the system bus.
• How OS Manage it:
o OS sets up DMA transfers by programming the DMA controller
o OS handles DMA completion interrupts
o OS ensures memory coherency after DMA operations

10.2 Normal I/O Operation V.S. Direct Memory Access

Normal I/O operation allows the CPU to control hardware by reading and writing specific
memory addresses. Usually, this would be used for low-bandwidth operations such as
changing control bits.

DMA allows hardware to directly read and write memory without involving the CPU.
Usually, this would be used for high-bandwidth operations such as disk I/O or camera video
input.

Normal I/O Operations

I/O Request
Control Signal Slow!!
DO
CPU Data Bus
I/O Device request
Device => CPU
Address Bus
CPU => Memory
WHILE more data

Memory Peripheral
(RAM) (Storage)
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Direct Memory Access

DMA Acknowledge
DMA Request
Control Signal

Data Bus DMA

CPU
Controller
Address Bus

Memory Peripheral
(RAM) (Storage)

11. User Interface

11.1 Command Line Interface (CLI)
• Direct text-based interaction with OS
• Efficient for system administration and scripting
• Lower resource overhead

11.2 Graphical User Interface (GUI)

• Windows, Gnome, KDI

• Heavy use of memory and I/O

• Keyboard, mouse, touch

11.3 Application Progg Interfaces (API)

An application programming interface (API) is a protocol intended to be used as an
interface by software components to communicate with each other. An API is a library that
may include specification for routines, data structures, object classes, and variables.
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APIs provide libraries for:

• System calls, routines, transfers

• Graphics

Makes development of software:

• Consistent with the OS
• Better controlled
• Easier for the programmer

12. OS Pyramid
The Operating System (OS) pyramid is a conceptual model that illustrates the various
functions within an operating system:
• User Interface
• Job Management
• Task Management
• Memory Management
• File Management
• Device Management
• Security