Measurement of Delay in Floorplanning

• Throughout the ASIC design process we need to predict the performance of the
final layout.
• In floorplanning we wish to predict the interconnect delay before we complete any
routing.
• To predict delay we need to know the parasitics associated with interconnect:
 the interconnect capacitance ( wiring capacitance or routing
capacitance )
 as well as the interconnect resistance.
• We cannot predict the resistance of the various pieces of the interconnect path
since we do not yet know the shape of the interconnect for a net.
• At the floorplanning stage we know only the fanout ( FO ) of a net (the number of
gates driven by a net) and the size of the block that the net belongs to.
• However, we can estimate the total length of the interconnect and thus estimate
the total capacitance.

• We estimate interconnect length by collecting statistics from previously routed

chips and analyzing the results.

• From these statistics we create tables that predict the interconnect capacitance
as a function of net fanout and block size.

• A floorplanning tool can then use these predicted-capacitance tables (also known
as interconnect-load tables or wire-load tables ).
Interconnect and gate delays. As feature sizes decrease, both average
interconnect delay and average gate delay decrease—but at different
rates. This is because interconnect capacitance tends to a limit that is
independent of scaling. Interconnect delay now dominates gate delay.
Predicted capacitance. (a) Interconnect lengths as a function of fanout (FO) and circuit-block size. (b) Wire-load
table. There is only one capacitance value for each fanout (typically the average value). (c) The wire-load table
predicts the capacitance and delay of a net (with a considerable error). Net A and net B both have a fanout of 1,
both have the same predicted net delay, but net B in fact has a much greater delay than net A in the actual
layout (of course we shall not know what the actual layout is until much later in the design process).
• shows that, because we do not decrease chip size as we scale down feature
size, the worst-case interconnect delay increases. One way to measure the
worst-case delay uses an interconnect that completely crosses the chip,
a coast-to-coast interconnect . In certain cases the worst-case delay of a
0.25 m m process may be worse than a 0.35 m m process, for example.
•
FIGURE 16.5 Worst-case
interconnect delay. As we scale
circuits, but avoid scaling the chip
size, the worst-case interconnect
delay increases.
 1. A and C in this example, are standard-cell
areas. These are flexible blocks .
Floorplanning Tools
2. Fixed blocks can only be modified when
they are created.

3. Seeding-force logic cells to be flexible

blocks.

4. ram_control* would select all logic cells

whose names started with ram_control to
be placed in one flexible block.

5. Seeding may be hard or soft. hard seed is

fixed and not allowed to move during the
remaining floorplanning and placement
steps.

6. A soft seed is an initial suggestion only

and can be altered if necessary by the
floorplanner.

7. We may also use seed connectors within

flexible blocks
1. We need to control the aspect ratio of our floorplan
because we have to fit our chip into the die cavity

2. (a) The initial floorplan with a 2:1.5 die aspect ratio

3. (b) Altering the floorplan to give a 1:1 chip aspect

ratio.

4. (c) A trial floorplan with a congestion map. Blocks A

and C have been placed so that we know the terminal
positions in the channels.

5. congestion map : the difference between the number of

interconnects that we actually need, called the channel
density , and the channel capacity.

6. Another measure the ratio of channel density to the

channel capacity.
7. Shading indicates the ratio of channel density to the
channel capacity. Dark areas show regions that cannot
be routed because the channel congestion exceeds the
estimated capacity.
8. (d) Resizing flexible blocks A and C alleviates
congestion.
Channel Definition

1. During the floorplanning step we assign the areas

between blocks that are to be used for interconnect.
This process is known as channel definition or channel
allocation.

2. Routing a T-junction between two channels in two-

level metal. The dots represent logic cell pins.

3. a) Routing channel A (the stem of the T) first allows us

to adjust the width of channel B.

4. (b) If we route channel B first (the top of the T), this

fixes the width of channel A. We have to route the stem
of a T-junction before we route the top.
Slicing Floorplan

1. (a) Make a cut all the way across the chip between
circuit blocks.

2. Each cut divides a piece into two without cutting

through a circuit block.

3. Continue slicing until each piece contains just one

circuit block.

4. (b) A sequence of cuts: 1, 2, 3, and 4 that successively

slices the chip until only circuit blocks are left.

5. (c) The slicing tree corresponding to the sequence of

cuts gives the order in which to route the channels: 4,
3, 2, and finally 1.
Cyclic constraints
1. Figure shows a floorplan that is not a slicing structure.

2. This means we cannot route any of the channels in this

floorplan without routing all of the other channels first.

3. We say there is a cyclic constraint in this floorplan.

4. There are two solutions to this problem. One solution

is to move the blocks until we obtain a slicing
floorplan. The other solution is to allow the use of L -
shaped, rather than rectangular, channels.

5. (a) A nonslicing floorplan with a cyclic constraint that

prevents channel routing.

6. (b) In this case it is difficult to find a slicing floorplan

without increasing the chip area.

7. (c) This floorplan may be sliced (with initial cuts 1 or

2) and has no cyclic constraints, but it is inefficient in
area use and will be very difficult to route.
Merging the blocks

1. We can remove the cyclic constraint by moving the

blocks again, but this increases the chip size.

2. Figure (c) shows an alternative solution. We merge the

flexible standard cell areas A and C.

3. We can do this by selective flattening of the netlist.

4. Sometimes flattening can reduce the routing area

because routing between blocks is usually less efficient
than routing inside the row-based blocks. Figure (b)
shows the channel definition and routing order for our
chip.
I/O and Power Planning 1. Every chip communicates with the outside world. We
need to consider the I/O and power constraints early in
the floorplanning process.

2. A die consists of a logic core inside a pad ring

3. Two types of die: Pad-limited and core-limited die.

4. (a) A pad-limited die. The number of pads

determines the die size.
5. (b) A core-limited die: The core logic determines the
die size.
6. (c) Using both pad-limited pads and core-limited pads
for a square die.

7. Usually one set of VDD/VSS pads supplies one power

ring that runs around the pad ring and supplies power
to the I/O pads only (dirty power since it has to supply
large transient currents to the output transistors).

8. Another set of VDD/VSS pads connects to a second

power ring that supplies the logic core (the clean
power ).
I/O and Power Planning

1. a) This chip uses both pad-limited and core-limited

pads. (b) A hybrid corner pad. (c) A chip with stagger-
bonded pads. (d) An area-bump bonded chip (or flip-
chip).

2. (c) shows a stagger-bond arrangement using two rows

of I/O pads. In this case the design rules for bond wires
(the spacing and the angle at which the bond wires
leave the pads) become very important.

3. (d) shows an area-bump bonding arrangement. Even

though the bonding pads are located in the center of
the chip, the I/O circuits are still often located at the
edges of the chip because of difficulties in power
supply distribution and integrating I/O circuit
 1. Power distribution. (a) Power distributed using m1 for
Two power distribution schemes VSS and m2 for VDD. This helps minimize the
number of vias and layer crossings needed but causes
problems in the routing channels.

2. (b) In this floorplan m1 is run parallel to the longest

side of all channels, the channel spine (c) An
expanded view of part of a channel (interconnect is
shown as lines). If power runs on different layers along
the spine of a channel, this forces signals to change
layers.

3. (d) A closeup of VDD and VSS buses as they cross.

Changing layers requires a large number of via
contacts to reduce resistance.

4. Channel spine use a preferred layer or preferred

direction

5. Since we can have both horizontal and vertical

channels, we have to decide whether to use a preferred
layer or the preferred direction for some channels
 Important Key Point Till Now
1. Die or Core
2. Wafer
3. Delay: Interconnect Delay, Gate Delay, Parasitic Delay, Delay due to Fan Out
4. Wire-Load
5. As Feature size decreased after some point the delay will get increased
6. Primitive Cell, Logic Cell, Standard Cell, Standard Cell Library (GPDK,TSMC,PDK,UMC), Standard
Block
7. FloorPlann
• Fixed Block
• Flexible Block
• Interconnect
• Standard Block
• Seeding
• Channel Density, Channel Capacity, Congestion Map
• T-Junction: Stem of T must route first
• Slicing,Slicing Tree
• Cyclic Constraints :Solution merge two flexible blocks together (Flattering the netlist)
8. I/O Pads and Power Planning
Pad Limitted ([Link] Pads determine the die size) and Core Limitted (Core logic determine the die size)
I/O Pads, I/O Circuitry
Power Pads (Vdd,Vss)
Two Distribution Scheme (Two Vdd, Vss)
 Different power distribution schemes

1. Power Pads
2. Power Rings
3. Power Mesh
4. Hierarchical power distribution
5. Dynamic Power distribution
6. Power Island
Clock Planning 1. A clock spine not to be confused with a channel spine

2. A clock spine is usually driven from one or more

clock-driver cells.

3. All clock pins driven directly from the clock driver

4. The clock-driver cell, often part of a special clock-pad

cell

5. Delay in the driver cell is a function of the number of

stages and the ratio of output to input capacitance for
each stage (taper).

6. Since all clocked elements are driven from one net

with a clock spine, skew is caused by differing
interconnect lengths and loads. If the clock-driver
delay is much larger than the interconnect delays, a
clock spine achieves minimum skew but with long
latency.
1. Clock skew represents a fraction of the clock period
that we cannot use for computation. A clock skew of
500 ps with a 200 MHz clock means that we waste
500 ps of every 5 ns clock cycle, or 10 percent of
performance.

2. Latency can cause a similar loss of performance at

the system level when we need to resynchronize our
output signals with a master system clock.

3. illustrates the construction of a clock-driver cell. The

delay through a chain of CMOS gates is minimized
when the ratio between the input capacitance C1 and
the output (load) capacitance C 2 is about 3 (exactly
2.7, an exponential ratio, if we neglect the effect of
parasitics).
Suppose we have an ASIC with the following specifications:
o 40,000 flip-flops
o Input capacitance of the clock input to each flip-flop is 0.025 pF
o Clock frequency is 200 MHz
o V DD = 3.3 V
o Chip size is 20 mm on a side
o Clock spine consists of 200 lines across the chip
o Interconnect capacitance is 2 pFcm –1

o clock-spine capacitance CL = 200 X 2 cm X 2 pFcm –1 = 800 pF.

o Number of buffer stages required
first-stage input capacitance of 0.025 pF

• The power dissipated charging the input capacitance of the

flip-flop clock is fCV 2 P 1 =(4 X10 4 ) (200 MHz) (0.025 pF) (3.3 V) 2= 2.178 W .
1

• power is dissipated in the clock-driver cell due to interconnect

P 2 1=(200 ) (200 MHz) (20 mm) (2 pFcm –1 )(3.3 V) 2= 1.7424 W = 2W
• The peak current would have reach
rise time is 0.1 ns
• Minimum delay is achieved when the taper of successive stages is about 3.
• We have to balance the clock arrival times at all of the leaf nodes to minimize clock skew.
• we need to balance the delays through the tree carefully to minimize clock skew (Clock Routing)
 Placement

After completing a floorplan we can begin placement of the logic

cells within the flexible blocks. After we complete floorplanning
and placement, we can predict both intrablock and interblock
capacitances.
 Placement Goals and Objectives

The goal of a placement tool is to arrange all the logic cells within the flexible blocks on a
chip.
Placement Goals:
• Guarantee the router can complete the routing step
• Minimize all the critical net delays
• Make the chip as dense as possible
• Minimize power dissipation
• Minimize cross talk between signals

Placement objectives:
• Minimize the total estimated interconnect length
• Meet the timing requirements for critical nets
• Minimize the interconnect congestion
 Placement Algorithms

There are two classes of placement algorithms commonly used in commercial CAD tools:

• constructive placement and

• iterative placement improvement.
• A constructive placement method uses a set of rules to arrive at a constructed placement
(min-cut algorithm).

The min-cut placement method

The min-cut placement method uses successive application of partitioning.
The following steps are
 Cut the placement area into two pieces.
 Swap the logic cells to minimize the cut cost.
 Repeat the process from step 1, cutting smaller pieces until all the logic cells
are placed.
The min-cut placement method (a) Divide the chip into bins using a grid.
(b) Merge all connections to the center of each
bin.
(c) Make a cut and swap logic cells between
bins to minimize the cost of the cut.
(d) Take the cut pieces and throw out all the
edges that are not inside the piece.
(e) Repeat the process with a new cut and
continue until we reach the individual bins.
 Iterative Placement Improvement

An iterative placement algorithm takes an existing placement and tries to improve it by moving the
logic cells.

There are two parts to the algorithm:

 The selection criteria that decides which logic cells to try moving.
 The measurement criteria that decides whether to move the selected cells.

There are several interchange or iterative exchange methods that differ in their selection and
measurement criteria:

 pairwise interchange,
 force-directed interchange,
 force-directed relaxation, and
 force-directed pairwise relaxation.
Iterative Placement

All of these methods usually consider only pairs of

logic cells to be exchanged. A source logic cell is
picked for trial exchange with a destination logic
cell.

[Link] the source logic cell at random.

[Link] all the other logic cells in turn as the
destination logic cell.
[Link] any of the measurement methods we have
discussed to decide on whether to accept the
interchange.
[Link] process repeats from step 1, selecting each
logic cell in turn as a source logic cell.
 Timing-Driven Placement Methods

• Minimizing delay(Between input and Output) is becoming more and more

important as a placement objective.
• There are two main approaches:
• net based and path based. T
• One method finds the n most critical paths (using a timing-analysis engine,
possibly in the synthesis tool). The net weights might then be the number of times
each net appears in this list. The problem with this approach is that as soon as we
fix (for example) the first 100 critical nets, suddenly another 200 become
[Link] consider only pairs of
 • The
difference
between the
required and
arrival times
at each input
pin is
the slack
time

The zero-slack algorithm. (a) The circuit with no net delays.

 • The practical
problem, however,
is getting the
weight information
for each net
(usually in the form
of timing
constraints) from a
synthesis tool or
timing verifier.
These files can
easily be hundreds
of megabytes in
size

The zero-slack algorithm adds net delays (at the outputs of each gate,
equivalent to increasing the gate delay) to reduce the slack times to
zero.
• With the zero-slack algorithm we simplify the problem. For example,
we might be able to do a better job by making some nets a little
longer than the slack indicates if we can tighten up other nets. What
we would really like to do is deal with paths such as the critical path
shown in Figure (a) and not just nets . Path-based algorithms have
been proposed to do this, but they are complex and not all
commercial tools have this capability.
• There is still the question of how to predict path delays between
gates with only placement information. Usually we still do not
compute a routing tree but use simple approximations to the total
net length and then use this to estimate a net delay. It is not until the
routing step that we can make accurate estimates of the actual
interconnect delays.
 Physical Design Flow

Historically placement was included with routing as a single tool (the term P&R is
often used for place and route).
Because interconnect delay now dominates gate delay,
The trend is to include placement within a floorplanning tool and use a separate
router.
Figure 16.31 shows a design flow using synthesis and a floorplanning tool that
includes placement. This flow consists of the following steps:
1. Design entry.
2. Synthesis.
3. Initial floorplan
4. Synthesis with load constraints
5. Timing-driven placement.
6. Synthesis with in-place
optimization ( IPO ).
7. Detailed placement.
1. Design entry. The input is a logical description with no physical information.
2. Synthesis. The output of the synthesis tool (typically an EDIF netlist) is the
input to the floorplanner.
3. Initial floorplan. From the initial floorplan interblock capacitances are input to
the synthesis tool as load constraints and intrablock capacitances are input as
wire-load tables.
4. Synthesis with load constraints. At this point the synthesis tool is able to
resynthesize the logic based on estimates of the interconnect capacitance each
gate is driving.
5. Timing-driven placement. After placement using constraints from the synthesis
tool, the location of every logic cell on the chip is fixed and accurate estimates
of interconnect delay can be passed back to the synthesis tool.
6. Synthesis with in-place optimization ( IPO ). The synthesis tool changes the
drive strength of gates based on the accurate interconnect delay estimates from
the floorplanner without altering the netlist structure.
7. Detailed placement. The placement information is ready to be input to the
routing step.
 Summary

• Floorplanning follows the system partitioning step and is the first step
in arranging circuit blocks on an ASIC.
• There are many factors to be considered during floorplanning:
arranging fixed blocks and reshaping flexible blocks to occupy the
minimum die area; organizing the interconnect areas between blocks;
minimizing connection length and signal delay between blocks;
planning the power, clock, and I/O distribution. The handling of some
of these factors may be automated using CAD tools, but many still
need to be dealt with by hand.
• Placement follows the floorplanning step and is more automated.
• It consists of organizing an array of logic cells within a flexible block.
• Optimization of minimum interconnect area, minimum total
interconnect length, or performance.
• There are two main types of placement algorithms: based on min-cut
or eigenvector methods. (iterative placement )
• Because interconnect delay in a submicron CMOS process dominates
logic-cell delay, planning of interconnect will become more and more
important.
• Instead of completing synthesis before starting floorplanning and
placement, we will have to use synthesis and
floorplanning/placement tools together to achieve an accurate
estimate of timing.
• standard delay format ( SDF)
• physical design exchange format ( PDEF )
• library exchange format ( LEF)
• design exchange format ( DEF )