MODULE-4
Draw and Explain the Physical Layout of CMOS 2-Input NAND and NOR Gates
1. CMOS 2-Input NAND Gate Layout
(Refer Fig. 5.19, Page 179)
Circuit Structure
● pMOS transistors (A and B) are connected in parallel between V_{DD} and output.
● nMOS transistors (A and B) are connected in series between output and V_{SS}.
Layout Diagram
1
Explanation
. The NAND gate consists of two pMOS transistors in parallel and two nMOS transistors in
series.
. Polysilicon lines A and B form the gates of both pMOS and nMOS transistors.
. The output is taken from the common connection between pull-up and pull-down networks.
. Shared diffusion regions reduce chip area.
. Metal lines are used for VDD, VSS, and output routing.
. The output becomes LOW only when both A and B are HIGH.
. The layout is compact and minimizes parasitic capacitances.
2. CMOS 2-Input NOR Gate Layout
(Refer Fig. 5.20, Page 180)
Circuit Structure
● pMOS transistors connected in series.
● nMOS transistors connected in parallel.
Layout Diagram
Explanation
. The NOR gate uses pMOS transistors in series and nMOS transistors in parallel.
. Inputs A and B are applied through polysilicon gate lines.
. The output node is connected between pull-up and pull-down networks.
. Shared diffusion reduces silicon area.
. Metal interconnections provide routing for power and output.
. Output becomes HIGH only when both inputs are LOW.
. The layout follows CMOS design rules for minimum area and delay.
Explain the Working of CMOS Complementary Logic
Definition
CMOS complementary logic is a logic design technique that uses both pMOS and nMOS transistors
in a complementary manner. The pMOS transistors form the Pull-Up Network (PUN) and the nMOS
transistors form the Pull-Down Network (PDN).
Diagram
Working
Case 1: Input = 0 (LOW)
● pMOS transistor turns ON.
● nMOS transistor turns OFF.
● Output is connected to VDD.
● Therefore, output becomes HIGH (1).
Case 2: Input = 1 (HIGH)
● pMOS transistor turns OFF.
● nMOS transistor turns ON.
● Output is connected to VSS (Ground).
● Therefore, output becomes LOW (0).
Advantages of CMOS Complementary Logic
. Uses complementary pMOS and nMOS transistor networks.
. Provides full output voltage swing from 0 to V_{DD}.
. Consumes very low static power.
. Offers high noise immunity.
. Produces less heat dissipation.
. Produces less heat dissipation.
. Gives reliable logic operation.
. Widely used in VLSI digital circuit design.
Realize / Design CVSL based XOR gate
Realise/ Design 2-input XOR/XNOR gate using Cascode Voltage Switch Logic
(CVSL)
Pass Transistor Logic (PTL)
Definition
Pass Transistor Logic (PTL) is a logic design technique in which MOS transistors are used as
switches to pass logic levels between nodes, instead of directly connecting transistors to V_{DD}
and V_{SS} as in conventional CMOS logic.
In PTL, the transistor acts as a controlled switch:
● ON → passes the input signal to the [Link] → disconnects the input from the output.
Operation
● Control = 1 → transistor ON → OUT = IN
● Control = 0 → transistor OFF → OUT disconnected
Example 1: XOR Gate using PTL
The textbook shows a pass transistor network implementing: F = A|B using controlled transistor
paths.
Draw the schematic diagram of:
4:1 multiplexer using NMOS and CMOS pass transistor logic
2:1 multiplexer using pass transistor logic
Pseudo nMOS Logic – Structure, Operation, Advantages and Disadvantages
Definition
Pseudo nMOS logic is an extension of conventional nMOS logic in which the depletion-load
transistor is replaced by a pMOS transistor. The pMOS transistor acts as an always-ON load
device with its gate connected to ground (VSS).
Structure
Circuit Diagram (Pseudo nMOS Gate)
● One pMOS transistor is connected between VDD and output.
● Gate of pMOS is permanently tied to VSS, so it remains ON.
● nMOS transistors form the pull-down logic network.
● Output is taken at the junction of pMOS and nMOS networks.
Operation
Case 1: Pull-down Network OFF
● Input combination does not create a path to ground.
● nMOS network remains OFF.
● Always-ON pMOS pulls the output to VDD.
● Output Z = 1 (HIGH)
Case 2:Pull-down Network ON
● Input combination turns ON the nMOS logic network.
● Output node is connected to ground.
● nMOS network overcomes the pMOS load.
● Output Z = 0 (LOW)
Thus the output is determined by the nMOS pull-down network while the pMOS transistor provides
the pull-up action.
Advantages of Pseudo nMOS Logic
. Requires fewer transistors than CMOS logic.
. Smaller chip area due to reduced transistor count.
. Simpler circuit design.
. Lower input capacitance.
. Higher packing density.
. Faster switching for some logic functions.
. Suitable for large fan-in gates.
Disadvantages of Pseudo nMOS Logic
. Static power dissipation occurs whenever the pull-down network is ON.
. pMOS transistor is always conducting, causing DC current flow.
. Higher power consumption than CMOS.
. Reduced noise margins.
. Proper transistor sizing is required for correct operation.
. Output voltage levels may not be ideal if sizing is improper.
. Not as power efficient as complementary CMOS logic.
What are the advantages of Dynamic CMOS logic? Explain the working of Dynamic
CMOS inverter with timing diagrams
Advantages of Dynamic CMOS Logic
. Low power dissipation because there is no direct DC path between V_{DD} and ground in
steady state.
. Fewer transistors than static CMOS logic.
. Smaller chip area due to reduced transistor count.
. Higher packing density.
. Higher operating speed because of lower input capacitance.
. Large fan-in gates can be implemented efficiently.
. Reduced load capacitance compared to complementary CMOS.
. Good performance for VLSI circuits requiring high speed and compact area.
Dynamic CMOS Inverter
Circuit Diagram
Where:
● φ = Clock signal
● PMOS = Precharge transistor
● NMOS = Evaluate transistor
Working of Dynamic CMOS Inverter
Dynamic CMOS operates in two phases:
1. Precharge Phase (φ = 0)
● PMOS precharge transistor turns ON.
● NMOS evaluate transistor turns OFF.
Output node Z is charged to V_{DD}.
φ=0
PMOS : ON
NMOS : OFF
Z = 1 (HIGH)
Thus the output capacitor is precharged.
2. Evaluation Phase (φ = 1)
● PMOS turns OFF.
● NMOS turns ON.
● Logic network determines the output.
Case A: Input = 1
A conducting path exists to ground.
Output discharges Z= 0
Case B: Input = 0
No path to ground exists.
Stored charge remains Z = 1
Timing diagram
Precharge and Evaluate Phases in Dynamic CMOS Logic
Dynamic CMOS logic operates in two phases controlled by a clock signal ( ):
1. Precharge Phase ( = 0)
Operation
● The pMOS precharge transistor is ON.
● The nMOS evaluate transistor is OFF.
● The output node is charged to VDD (logic 1).
● No discharge path exists to ground.
Result
● Output node Z is precharged to logic HIGH.
● The output capacitor stores charge.
● The gate is prepared for the next evaluation phase.
2. Evaluate Phase ( = 1)
Operation
● The pMOS precharge transistor turns OFF.
● The nMOS evaluate transistor turns ON.
● The logic network determines whether the output should remain HIGH or discharge.
Case 1: Logic Network Conducts
● A path exists to ground.
● Stored charge is discharged.
● Output becomes 0.
Case 2: Logic Network Does Not Conduct
● No discharge path exists.
● Stored charge remains.
● Output stays at 1.
Describe the operation of: C^2MOS logic
Definition
C²MOS (Clocked CMOS) is a dynamic CMOS logic technique in which clock-controlled transistors
are inserted into a conventional CMOS gate. These clock transistors enable or disable the logic
operation depending on the clock signal.
The circuit consists of:
● A CMOS logic block.
● A pMOS clock transistor connected to V_{DD}.
● An nMOS clock transistor connected to V_{SS}.
● A clock signal \phi and its complement \bar{\phi}.
Operation
1. Precharge / Hold Phase ( = 0)
● The pMOS clock transistor turns ON.
● The nMOS clock transistor turns OFF.
● The output node is isolated from ground.
● The previously stored logic value is retained.
● No evaluation occurs.
Result: Output remains unchanged (stored).
2. Evaluation Phase ( = 1)
● The pMOS clock transistor turns OFF.
● The nMOS clock transistor turns ON.
● The CMOS logic network becomes active.
● Depending on the inputs, the output is evaluated and updated.
Result: Correct logic output appears at the output node.
Advantages
. Lower dynamic power dissipation.
. Reduced clock loading.
. Better noise immunity than simple dynamic logic.
. Prevents direct short-circuit current paths.
Disadvantages
. Requires clock and complementary clock signals.
. Additional clock transistors increase delay.
. Rise and fall times are larger than static CMOS.
. Clock distribution becomes more complex.
Describe the operation of: CVS / CVSL (Cascode Voltage Switch Logic)
Definition
CVSL (Cascode Voltage Switch Logic) is a differential CMOS logic style that produces both a
logic function F and its complement simultaneously.
It consists of:
● Two complementary nMOS logic networks.
● Two cross-coupled pMOS transistors acting as active loads.
● Differential outputs Q and .
Basic Structure
The pMOS transistors are cross-coupled:
● Gate of left pMOS connected to Q̅ .
● Gate of right pMOS connected to Q.
Operation
Case 1: F = 1
● Left nMOS network conducts.
● Node Q is pulled to GND (0).
● Since Q = 0, the right pMOS turns ON.
● Right pMOS pulls to VDD (1).
Therefore: Q = 0, Q̅ = 1
Case 2: F = 0
● Right nMOS network conducts.
● Node is pulled to GND (0).
● Left pMOS turns ON.
● Left pMOS pulls Q to VDD (1).
Therefore: Q = 1, Q̅ = 0
Why Cross-Coupled pMOS?
The cross-coupled pMOS pair provides:
● Positive feedback.
● Faster switching.
● Full voltage swing.
● Better noise margin.
Only one output can be HIGH while the other is LOW.