Registration No.

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02 4
2/ 2
Total Number of Pages: 02
1 7 /1 Course:[Link]
Sub_Code:REC5D006

09 -
1
5th / 7th Semester Regular/Back Examination: 2024-25
SUBJECT: Digital VLSI Design
BRANCH(S): AEIE, CSE, EEE, ELECTRICAL, ECE, ETC, IT, MMEAM, MECH

- - 1
Time: 3 Hours

24
Max Marks: 100

/ 2 0 [Link]: R399

12
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two

1 7 / from Part-III.

9-
The figures in the right hand margin indicate marks.

10 -- 1
Q1 Answer the following questions:
Part-I
0 2 4 (2 x 10)
a) Why modularity is important in designing VLSI Circuits?
b) Differntiate between Lambda and Micron design1rules. 2 /2
1 7 /
c) Why constant voltage scaling is preferred?
d) Why Noise Margin of CMOS is better 9
0 - Resistive Load Inverter?
than
e) Draw a two input NOR gate using1dynamic logic.
f) What is the most important advantage of CMOS transmission gate compared to pass
transistor logic.
-- 1
g) What are the different types of fault
2 4
models?
0
h) Why LFSR is used in output response
2 / 2 analyzer?

j) Draw a three input AND7 / 1using pass transistor logic.

i) Why SRAM is used in cache memory?

9 - 1 gate

10 Part-II -- 1
4 of Twelve)
1 Answer Type Questions- (Answer Any Eight2out
Q2
4
a) Differentiate
-
Only Focused-Short
-between Regularity, Modularity, and Locality. /2 0 (6 x 8)

2
b) Derive0 2 /1 2
the MOSFET current equation for Linear region of operation.
/ the 4:1 multiplexer using Transmission gates.-17
c) 2Sketch
1
7 /
d) What do you mean by MOSFET scaling? Show how
0 9 the MOSFET parameters (power,

109-1 e)
area, current density, doping densities) are
Draw a JK Flipflop using static CMOS Logic.
1 constant voltage scaling.
scaled in

f) Why cascading is not preferred in dynamic CMOS logic?

g) Create a circuit which will explain the Ad Hoc Testable Design Techniques.
h) Draw and explain the Scan-Based Techniques for testing of sequential circuits.
 i) Draw and explain the operation of 1T DRAM Cell. Why DRAM is not preferred in high-
speed logic design?
j)
-- 1
Draw the stick diagram of the Boolean function Y = AB + CD (E + F).
k)
l)
02 4
Draw the half adder circuit using Pass Transistor Logic.
Describe the operations of Flash memory with proper diagram.

2/ 2
1 7 /1
9 - Part-III

10
Only Long Answer Type Questions (Answer Any Two out of Four)

Q3 In CMOS inverter Vdd = 5V. The output load capacitance is 1 nF. The nMOS transistor (16)
parameters are given as µncox = 20 µA/ V2, (W/L)n = 10, VT, n = 1.0 V. Calculate the delay
- - 1
time when output is falling from 4.7 V to 1 V.

2 0 24
Q4
12 /
Write and draw all the steps needed to fabricate CMOS n-well Process. (16)

Q5 1 7 /
Draw a edge triggered D Flipflop using CMOS transmission gates. (16)

10 9- 1
Q6
4 --
Explain the signature analysis technique used in output response analyzer of Built in (16)

2 02
self-Test (BIST) technique with taking an example of 5-bit Linear Feedback Shift
Register (LFSR).
2/
1 7 /1
-
109
-- 1
02 4
1 2 /2
17 /
0 9 -
1 -- 1
2 4
2 4 --1 / 2 0
20 /1 2
1 2 / - 1 7
- 17/ 109
10 9
 Registration No.:

-- 1
Total Number of Pages: 02
02 4 Course: [Link]
Sub_Code: REC5D006
1/ 2
th
6 0
5 Semester/Regular/Back Examination: 2023-24

9 - 1 BRANCH(S): ECE,
SUBJECT: Digital VLSI Design

1 0 Time: 3 Hour
ETC

Max Marks: 100

[Link]: N382
- 1
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
-
2 0 24
from Part-III.
The figures in the right hand margin indicate marks.
01 /
1 6 / Part-I
Q1
a)
10 9-
Answer the following questions:
Give the various color coding used in stick diagram.
1
(2 x 10)

b) What is CLB?
4 --
c)
0
Build a circuit for NAND gate using pass transistor.
2 2
d)
1/
What is the role of parasitic capacitance for the computation of dynamic power?
e) What is Body effect?
1 6 /0
f)
-
What are the approaches in design for testability?
g)
h)
Explain about clock skew.
109
What is one-time programmable memory?
i) What is the interconnect design?
j) List out the applications of FPGAs.
-- 1
02 4
0 1 /2 Part-II
Q2
Twelve)
16 /
Only Focused-Short Answer Type Questions- (Answer Any Eight out of (6 × 8)

a) 9 -
Discuss the design rules of contact cuts for NMOS and CMOS.
0
b) 1 -- 1
What is meant by sheet resistance Rs? Explain the concept of Rs applied to MOS
2 4
--1
transistors.
c)
4 / 2 0
Derive the relationship between drain to source current Ids versus drain to source

20 2
voltage Vds in a non-saturated and a saturated region.
/0 1
0 1
d) / 1 6
Derive the expression for the CMOS inverter delay.
-
- 16/ e)
f) 109
Briefly discuss about scaling limitation for low voltage, low power design.
Define threshold voltage of a MOS device and explain its significance.

10 9 g) What are the different faults found in combinational circuits? How can they be
categorized?
h) Implement the expression Y = (A + B + C)Ꞌ with TG.
i) Explain the operation modes of NORA logic style.
 j)
-- 1
With the help of neat diagrams explain about power grid and clock design.
k)
l)
Explain about the MUX based latches.
02 4
Draw the circuit diagram of the Built-In Self-Test (BIST) circuit and explain its
operation.
1/ 2
1 6 /0
09 - Part-III
1
Only Long Answer Type Questions (Answer Any Two out of Four)

Q3 a) Analyze the steps involved in a CMOS p-well process. (08)

b)
- - 1
What is Moore’s law? Explain its relevance with respect to the evolution of (08)
technology.
0 2 4
1 2
Q4 a) Design a multiplier/for 5 bits and 3 bits. Explain its operation and summarize the (08)
/ 0
6step-by-step procedure to implement half adder circuit using FPGA.
number of adders.
- 1
b) Explain the
9
(08)

Q5 a) 1 An0nMOS transistor is operating in saturation region with the following

-1 parameters.
V = 5V; V = 1.2V; W/L = 110; μ C = 110 μA/V . Find 4
GS tn n ox
2

2 -
transconductance of the
(08)

device?
2
b) Derive the expressions for rise time and fall time in/the
0case of CMOS inverter.
/ 0 1 (08)

-
Q6 a) Design a queue and write the dataflow style 1 6VHDL program for the same. (08)

1 0 9
b) Draw a structure of 4x4 static RAM and explain its operation. (08)

-- 1
0 2 4
1 / 2
6 / 0
9 - 1
10 4 - - 1
- - 1 2 02
0 2 4 1 /
/ 2 6 /0
/ 0 1 9 - 1
- 1 6 1 0
109
 Registration No :

-- 1
Total Number of Pages : 02
02 3 Course: [Link]
Sub_Code: PET5H002 / REC5D006
4/ 2
th
/ 0 / Back Examination: 2022-23
5 Semester Regular
8
9 - 0SUBJECT: Digital VLSI Design

1 0 BRANCH(S): ECE,ETC
Time : 3 Hour
Max Marks : 100
[Link] : L450/ L451
- 1
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two
-
2 0 23 from Part-III.
The figures in the right hand margin indicate marks.
04 /
0 8 / Part-I
Q1 Answer
0 9 - the following questions: (2 x 10)
a) What
1 are the various modeling in Verilog?
-- 1 operation
mode of the PMOS transistor?
0 2 3
b) What is the oxide capacitance value for linear and saturation

c) What is the full custom ASIC design?

4 / 2
d) Define average propagation delay for an CMOS
8 /0 inverter.
e) CAM is mostly used in which memory
f) Draw the stick diagram for a CMOS 9 - 0 circuits?
3- input NAND gate
g) What are feed-through cells?1State 0 their uses.
h) The NMOS transistor shown has V = 0.5V. Find the range of V for which
T G
the transistor conducts.
- - 1 of NAND gate
i) Design EX-NOR gate using minimum
j) Explain about the principle of Built02 3 number
in Self-Test.
4 / 2
8 / 0 Part-II
Q2 Only Focused-Short
of Twelve) 09
-0 Answer Type Questions- (Answer Any Eight out (6 × 8)

1
a) Define Channel-length -- 1
modulation? Show it’s impact on output impedance
- 1
of MOS transistor.
0 2 3
b) Explain3the
2 - concept involved in structural gate level modeling
/ 2 and give the
0 a for
description
2 Full adder.
/0 4
c) /Consider resistive load inverter circuit with V 8
/ 0 4 0.8 V, R =250KΩ and W/L=[Link] noise9-margins
DD
0 of the circuit.
n
2
=6V, K ′ = 20 µA/V , V =
TO

- 0 8 d) Explain λ-based design rules in VLSI circuit

L
1 0 Design.
109 e) Draw input and output waveforms during high to low transition of output for
a CMOS inverter. Derive expression for τPHL.
f) Prove that (W/L)P ≅ 2.5(W/L)n, in an ideal symmetrical CMOS inverter.
g) Calculate the average propagation delay of a CMOS Ring Oscillator circuit
if its Oscillation frequency is 1KHz and number of inverters used for the
design is 7.
 h) Draw the Euler path and layout diagram of 3-input NAND gate.
i)
-- 1
Compare NORA and NP(ZIPPER) CMOS logic structures.
j)
clock.
02 3
Design a shift register with the dynamic latch operated by a two-phase

k) / 2
Draw the schematic of negative edge-triggered master-slave D flip-flop
4
l)
topology. 0 8/0
Explained a balance topology offers less glitch compared to unbalanced

09 -
1 Part-III
Only Long Answer Type Questions (Answer Any Two out of Four)

- 1
Q3 (a) Calculate the threshold voltage VT0 at VSB=0 for an Aluminum gate n-
- (10)

0 23
channel MOS transistor, with the following parameters: substrate doping
density NA=4x1018 cm-3, gate oxide thickness tox=20 Ao, metal
2
04 /
workfunction=4.2 eV, ni= 1.45x1010 cm-3 and oxide interface fixed charge

0 8 /
density Nox=2x1010 cm-2.

10 9-
(b) Explain VLSI Design flow using Y-chart.
1
(06)

--
Q4 (a) What is a multiplexer? Realize a 4X1 MUX using transmission gate logic.
3 (08)
02
(b) With neat sketches explain oxidation process in IC fabrication.
2 NOR2 gate, if k
(08)

4
Calculate the switching threshold voltage0of
/CMOS
Q5 (a)
and V = |V |= 0.6 V. Given that the 8
0 / voltage is 3.3 V.
supply
n = kp (08)

(b)
T,n T,P

9
Explain the charge sharing problem
0 -of DOMINO logic. (08)
1
Q6 (a) Draw the schematic of NAND Flash Memory cell (06)

-- 1
(b) Analyze the problem of cascading that occurs in dynamic CMOS logic with (10)

Domino Logic = C + (D+ ) 0 3

the help of a suitable example. Implement the following logic function using
2
0 4 /2
08 /
0 9 -
1 -- 1
2 3
2 3 --1 / 2 0
20 /0 4
0 4 / - 0 8
- 08/ 109
10 9
 Registration No :
109 109 109 109 109 109 109 109

Total Number of Pages : 02 B. Tech

REC5D006

5th Semester Regular / Back Examination: 2021-22

DIGITAL VLSI DESIGN
BRANCH(S): ECE, ETC
Time : 3 Hour
109 109 109 109
Max Marks 109
: 100 109 109 109

[Link] : OF415
Answer Question No.1 (Part-1) which is compulsory, any eight from Part-II and any two from Part-
III.
The figures in the right hand margin indicate marks.

Part-I
Q1 Answer the following questions : (2 x 10)
109 109 109 109 109 109 109 109
a) For the CMOS circuit of the Boolean function Y =(( A+B+C)(D+E))’, what is the
equivalent W/L ratio of the pMOS network? Assume (W/L)p = 15 for all pMOS
transistor.
b) What is the flat band voltage? How is it related to surface potential of MOSFET?
c) Explain the concept of locality in design.
d) What is the effect of substrate bias voltage on threshold voltage?
e) In linear operating mode of MOS transistor, what are the values of the capacitance
109 109
Cgb(total) and C (total)?
109 gs 109 109 109 109 109
f) Implement two input XOR gate using transmission gate.
g) Draw the circuit and plot thevoltage transfer characteristic (VTC) of a resistive load
inverter.
h) What are the capacitances present between three parallel lines running on two
different levels?
i) What is the effect of channel length modulation on the drain current in saturation
region?
109
j)
109
What is power109
delay product?
109 109 109 109 109

Part-II
Q2 Only Focused-Short Answer Type Questions- (Answer Any Eight out of (6 × 8)
Twelve)
a) Explain the three regions of operation of an n-channel enhancement MOSFET with
suitable diagram.
b) For a polysilicon interconnect line
109 109 given below109calculate the total
109 lumped 109 109 109 109
resistance and total parasitic
capacitance of this line. Given sheet
resistance = 30 /square, Cpf(Area) =
0.066 fF/µm2 and Cpf(Perimeter) =
0.046 fF/µm.
c) Prove that the total equivalent resistance of the transmission gate (TG) remains
relatively constant, independent of the output voltage. Explain the operation in all
109 109 the three regions.
109 109 109 109 109 109
d) Explain the operation of a CMOS SR latch circuit based on 2-input NAND gates.
Also discuss about the total lumped capacitance at both the output nodes.

109 109 109 109 109 109 109 109

 e) Explain the basic principle of pass transistor for logic “0” transfer. Calculate the fall
109 109 time for the 109
soft-node voltage.109 109 109 109 109

f) Explain the pipelined NORA CMOS system.

g) For a CMOS inverter with the following parameters: VT0,n = 0.6v, VT0,p = -0.7v, VDD
= 3.3v, kn = 200µA/V2, kp = 80µA/V2. Calculate noise margins of the circuit.
h) Draw the MOSFET schematic circuit diagram and stick diagram for Y = (A + BC +
DEF)’.
i) Give a comparison of the different VLSI design styles.
109
j)
109
Discuss both 109
constant field109scaling and constant
109
voltage 109
scaling and its 109 109
effect on drain current and power density.
k) Explain the operation of a fully CMOS SRAM cell including read and write
operation.
l) Explain the electrical fault and logical faults in VLSI chip with the help of examples.

Part-III
Only Long Answer Type Questions (Answer Any Two out of Four)
109 Q3 109 Consider a 109
MOS system with 109the following parameters:
109 109 Armstrong, 109 =
tox= 200 GC (16) 109
15 -3 11 2
-0.85v, NA = 2×10 cm , QOX = q.2.10 C/cm . Determine the threshold voltage
VT0 under zero bias at room temperature. εOX = 3.97ε0 and εsi= 11.7 ε0. Also
determine the type (p-type or n-type) and the amount of channel implant (in
NI/cm2) required to change the threshold voltage to 0.8V.

Q4 What is rise time and fall time? Determine the fall time of a CMOS inverter using (16)
both average current method and differential equation method . The output load
109 109
capacitance109
is 1 pf. The nMOS109 109
transistor parameters are: kn’ 109 109
= 20µA/V2, (W/L)n =
109

10, VDD = 5v and VT,n = 1v.

Q5 i) What are the junction capacitances in a MOSFET. Derive the equivalent (16)
capacitance of a junction when the reverse bias voltage across the pn-junction
changes from V1 to V2.
ii) Consider an abrupt reverse biased PN junction. The doping density of the n-
type region is ND = 1019 cm-3 and doping density of the p-type region is given as
109 109 109 109 109 109 109 109
NA = 1016 cm-3. The junction area is A = 30 µm × 30 µm. Calculate the zero bias
junction capacitance per unit area. Also, find the average junction capacitance
assuming that the reverse bias voltage changes form V1 = 0 to V2 = -3 V

Q6 Explain the operation of 2 input CMOS NOR gate with help of circuit diagram. (16)
Calculate the critical voltage levels VIL, VIH and its corresponding output voltage
considering the following parameters: (W/L)p = 4, (W/L)n = 1, VTn = 0.7V, VTp = -
109 109
0.7V, kn’ = 40 µA/V2, kp’ = 20109
109
µA/V2, and VDD 109
=5V. 109 109 109

109 109 109 109 109 109 109 109

109 109 109 109 109 109 109 109