MODULE III SYNCHRONOUS SEQUENTIAL LOGIC

Sequential Circuits - Latches and Flip Flops - Analysis of clocked sequential circuits– State

Table, State Reduction Diagram and State Assignment – Design Procedure.

Sequential Circuits
Sequential circuits are digital circuits that store and use previous state information to
determine their next state. They are commonly used in digital systems to implement state
machines, timers, counters, and memory elements and are essential components in digital
systems design.
 Sequential circuits are commonly used in digital systems to implement state
machines, timers, counters, and memory elements.
 The memory elements in sequential circuits can be implemented using flip-flops,
which are circuits that store binary values and maintain their state even when the
inputs change.
 Unlike combinational circuits, which only depend on the current input values to
produce outputs, sequential circuits depend on both the current inputs and the
previous state stored in memory elements.
Sequential circuit is a combinational logic circuit that consists of inputs variable (X), logic
gates (Computational circuit), and output variable (Z).

A combinational circuit produces an output based on input variables only, but a sequential
circuit produces an output based on current input and previous output variables. That
means sequential circuits include memory elements that are capable of storing binary
information. That binary information defines the state of the sequential circuit at that time.
A latch capable of storing one bit of information.
As shown in the figure, there are two types of input to the combinational logic :
1. External inputs which are not controlled by the circuit.
2. Internal inputs, which are a function of a previous output state.
Secondary inputs are state variables produced by the storage elements, whereas secondary
outputs are excitations for the storage elements.
Types of Sequential Circuits
There are two types of sequential circuits
Asynchronous Sequential Circuit
These circuits do not use a clock signal but uses the pulses of the inputs. These circuits
are faster than synchronous sequential circuits because there is clock pulse and change their
state immediately when there is a change in the input signal. We use asynchronous sequential
circuits when speed of operation is important and independent of internal clock pulse.

But these circuits are more difficult to design and their output is uncertain.
Synchronous Sequential Circuit
These circuits uses clock signal and level inputs (or pulsed) (with restrictions on pulse width
and circuit propagation). The output pulse is the same duration as the clock pulse for the
clocked sequential circuits. Since they wait for the next clock pulse to arrive to perform the
next operation, so these circuits are bit slower compared to asynchronous. Level output
changes state at the start of an input pulse and remains in that until the next input or clock
pulse.

We use synchronous sequential circuit in synchronous counters, flip flops, and in the design
of MOORE-MEALY state management machines. We use sequential circuits to design
Counters, Registers, RAM, MOORE/MEALY Machine and other state retaining machines.
Clock Signal and Triggering
Clock signal is a kind of control signal that allows the elements of synchronous circuits to be
in phase or phenomena that occur in circuits. It is derived from the square wave that has a
high and a low level, it helps in measuring the sequential changes in the circuit states. The
clock signal also makes a pulse simultaneously on all the circuit parts that are needed for the
proper work of synchronous sequential circuits.
Types of Triggering
In Sequential circuits, triggering denotes the way, in terms of which the state changes take
place. There are two main types of triggering
Level Triggering
Level triggering happens when the change of state is from the level of the clock signal is high
or low. The circuit depends on the level of the clock signal rather than the rising or the falling
edge of it. There are two types of level triggering:
1. Positive Level Triggering: The circuit changes state when it is high time in the clock
cycle i.e. when the clock signal is high.
2. Negative Level Triggering: The circuit changes state when the clock signal is in the
low state.
Edge Triggering
Edge triggering occurs when the state change is initiated by the transition (rising or falling
edge) of the clock signal. The circuit responds to the clock signal's edges rather than its
levels. There are two types of edge triggering:
1. Positive Edge Triggering: The circuit changes state on the rising edge (transition
from low to high) of the clock signal.
2. Negative Edge Triggering: The circuit changes state on the falling edge (transition
from high to low) of the clock signal.
Edge Triggering
Applications
Sequential circuits find application in virtually almost every digital system today because of
their capacity to handle state information. Some common applications include:
 Counters: Appearing in commonly in digital clocks, frequency counters, and event
counters.
 Registers: Found in microprocessors and digital systems as a storage medium, a
transfer medium and a medium for manipulating data.
 Memory Elements: Used in RAM and other storage devices to keep data in a
temporary hold.
 State Machines: Made use in control systems , communication processes, and
different digital devices for state control.
 Timers: It is applied in time measurement, delay production, and scheduling functions
in digital circuits.
What are Latches?
Latches are digital circuits that store a single bit of information and hold its value until it is
updated by new input signals. They are used in digital systems as temporary storage elements
to store binary information. Latches can be implemented using various digital logic gates,
such as AND, OR, NOT, NAND, and NOR gates.
Latches are widely used in digital systems for various applications, including data storage,
control circuits, and flip-flop circuits. They are often used in combination with other digital
circuits to implement sequential circuits, such as state machines and memory elements.
Latches Definition
Latches are basic storage elements that operate with signal levels (rather than signal
transitions). Latches controlled by a clock transition are flip-flops. Latches are level-sensitive
devices. Latches are useful for the design of the asynchronous sequential circuit. Latches are
sequential circuit with two stable states. These are sensitive to the input voltage applied and
does not depend on the clock pulse. Flip flops that do not use clock pulse are referred to as
latch.
Types of Latches in Digital Electronics
In digital electronics different types of latches are:
 SR Latches
 Gated SR Latches
 D Latches
 Gated D Latches
 JK Latches
 T Laches
SR Latch
S-R latches i.e., Set-Reset latches are the simplest form of latches and are implemented using
two inputs: S (Set) and R (Reset). The S input sets the output to 1, while the R input resets the
output to 0. When both S and R inputs are at 1, the latch is said to be in an "undefined" state.
They are also known as preset and clear states. The SR latch forms the basic building blocks
of all other types of flip-flops.
Truth Table of SR Latch
The below table represents the truth table of SR latch.

S R Q Q'

0 0 Latch Latch

0 1 0 1

1 0 1 0
S R Q Q'

1 1 0 0

Logic Diagram of SR Latch

SR Latch is a logic circuit with:
 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
 2 input S for SET and R for RESET
 2 output Q, Q'.
The below logic diagram represents the SR latch using NAND gate.

The below logic diagram represents SR latch using NOR Gate.

Different Cases of SR Latch
The different cases of SR latch are discussed below.
Case 1: S' = R' = 1 (S = R = 0)
If Q = 1, Q and R' inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R' inputs for 2nd NAND gate are 0 and 1 respectively.

Case 2: S' = 0, R' = 1 (S = 1, R = 0)

 As S' = 0, the output of 1st NAND gate, Q = 1 (SET state).
 In second NAND gate, as Q and R' inputs are 1, Q'=0.
Case 3: S' = 1, R' = 0 (S = 0, R = 1)
 As R'=0, the output of 2nd NAND gate, Q' = 1.
 In first NAND gate, as Q and S' inputs are 1, Q = 0 (RESET state).

Case 4: S' = R' = 0 (S = R = 1)

When S = R = 1, both Q and Q' becomes 1 which is not allowed. So, the input condition is
prohibited.
Gated SR Latch
A Gated SR latch is a SR latch with enable input which works when enable is 1 and retain the
previous state when enable is 0.
Truth Table of Gated SR Latch
The below table represents the truth table of Gated SR latch.

Enabl
e S R Qn+1

0 X X Qn

1 0 0 Qn

1 0 1 0

1 1 0 1

1 1 1 X

Logic Diagram of Gated SR Latch

The below logic diagram represents the gated SR latch.

Logic
Diagram of Gated SR Latch

D Latch
D latches are also known as transparent latches and are implemented using two inputs: D
(Data) and a clock signal. The output of the latch follows the input at the D terminal as long
as the clock signal is high. When the clock signal goes low, the output of the latch is stored
and held until the next rising edge of the clock.
Truth Table of D Latch
The below table represents the truth table of D latch.
E D Q Q'

0 0 Latch Latch

0 1 Latch Latch

1 0 0 1

1 1 1 0

Logic Diagram of D Latch

The below logic diagram represents the D latch.

L
ogic Diagram of D Latch

Gated D Latch
D latch is similar to SR latch with some modifications made. Here, the inputs are
complements of each other. The D latch stands for "data latch" as this latch stores single bit
temporarily.
Truth Table of Gated D Latch
The below table represents the truth table of Gated D latch.

Enable D Qn Qn+1 STATE

1 0 x 0 RESET
Enable D Qn Qn+1 STATE

1 1 x 1 SET

0 x x Q(n) No Change

Characteristics Equation: Qn+1 = EN.D + EN'.Qn

Logic Diagram of Gated D Latch

The below logic diagram represents the gated D latch.

JK Latch
JK latch has two inputs J and K. The output gets toggled when the J and K inputs are
high. JK latch is just like SR latch, but it eliminates the undefined state of SR latch.
Truth Table of JK Latch
The below table represents the truth table of JK latch.

J K Qn+1 Comment

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 Q' Toggle

Logic Diagram of JK Latch

The below logic diagram represents the JK latch.

Logic Diagram of JK Latch

T Latch
When the JK inputs of JK latch are shorted we get the T latch. In T latch the outputs are
toggled when the inputs are high.
Logic Diagram of T Latch
The below logic diagram represents the T latch.
Logic Diagram of T Latch

Advantages of Latches
Some of the advantages of latches are listed below.
1. Easy to Implement: Latches are simple digital circuits that can be easily
implemented using basic digital logic gates.
2. Low Power Consumption: Latches consume less power compared to other
sequential circuits such as flip-flops.
3. High Speed: Latches can operate at high speeds, making them suitable for use in
high-speed digital systems.
4. Low Cost: Latches are inexpensive to manufacture and can be used in low-cost
digital systems.
5. Versatility: Latches can be used for various applications, such as data storage, control
circuits, and flip-flop circuits.
Disadvantages of Latches
Some of the disadvantages of latches are listed below.
1. No Clock: Latches do not have a clock signal to synchronize their operations, making
their behavior unpredictable.
2. Unstable State: Latches can sometimes enter into an unstable state when both inputs
are at 1. This can result in unexpected behavior in the digital system.
 3. Complex Timing: The timing of latches can be complex and difficult to specify,
making them less suitable for real-time control applications.
Flip-Flop Types
Last Updated : 8 Oct, 2025


The flip-flop is a circuit that maintains a state until directed by input to change the state. A
basic flip-flop can be constructed using four-NAND or four-NOR gates. A flip-flop is
popularly known as the basic digital memory circuit. It has its two states as logic 1(High) and
logic 0 (Low) states.
 A flip-flop is a sequential circuit which consists of a single binary state of information
or data.
 The digital circuit is a flip-flop which has two outputs and are of opposite states. It is
also known as a Bistable Multivibrator.
Types of Flip-Flops
Given Below are the Types of Flip-Flop
 SR Flip Flop
 JK Flip Flop
 D Flip Flop
 T Flip Flop
Logic diagrams and truth tables of the different types of flip-flops are as follows:
S-R Flip Flop
In the flip flop, with the help of preset and clear when the power is switched ON, the states of
the circuit keeps on changing, that is it is uncertain. It may come to set(Q=1) or reset(Q’=0)
state. In many applications, it is desired to initially set or reset the flip flop that is the initial
state of the flip flop that needs to be assigned. This thing is accomplished by the preset(PR)
and the clear(CLR).
Block Diagram of S-R Flip Flop
Given Below is the Block Diagram of S-R Flip Flop
 S-R Flip Flop

Circuit Diagram and Truth Table of S-R Flip Flop

Given Below is the Diagram of S-R Flip Flop with its Truth Table
Operations of S-R Flip Flop
Given Below is the Operations of S-R Flip Flop
 Case 1(PR=CLR=1): The asynchronous inputs are inactive and the flip flop responds
freely to the S,R and the CLK inputs in the normal way.
 Case 2(PR=0 and CLR=1):This is used when the Q is set to 1.
 Case 3(PR=1 and CLR=0):This is used when the Q’ is set to 1.
 Case 4(PR=CLR=0): This is an invalid state.
Characteristics Equation for SR Flip Flop
QN+1 = QNR' + SR'
J-K Flip Flop
In JK flip flops, The basic structure of the flip flop which consists of Clock (CLK), Clear
(CLR), Preset (PR).
Block Diagram of J-K Flip Flop
Given Below is Block Diagram of J-K Flip Flop

J-K Flip Flop

Circuit Diagram and Truth Table of J-K Flip Flop
Given Below is the Diagram of J-K Flip Flop with its Truth Table
Operations of J-K Flip Flop
Given Below is the Operations of J-K Flip Flop
 Case 1 (PR=CLR=0 ):This condition is in its invalid state.
 Case 2 (PR=0 and CLR=1):The PR is activated which means the output in the Q is
set to 1. Therefore, the flip flop is in the set state.
 Case 3 (PR=1 and CLR=0):The CLR is activated which means the output in the Q’
is set to 1. Therefore, the flip flop is in the reset state.
 Case 4 (PR=CLR=1):In this condition the flip flop works in its normal way whereas
the PR and CLR gets deactivated.
Race Around Condition in J-K Flip Flop
When the J and K both are set to 1, the input remains high for a longer duration of time, then
the output keeps on toggling. Toggle means that switching in the output instantly i.e. Q=0,
Q’=1 will immediately change to Q=1 and Q’=0 and this continuation keeps on changing.
This change in output leads to race around condition.
Characteristics Equation for JK Flip Flop
QN+1 = JQ'N + K'QN

D Flip Flop
The D Flip Flop Consists a single data input(D), a clock input(CLK),and two outputs: Q and
Q' (the complement of Q).
Block Diagram of D Flip Flop
Given Below is the Block Diagram of D Flip Flop

D
FLIP FLOP

Circuit Diagram and Truth Table of D Flip Flop

Given Below is the Diagram of D Flip Flop with its Truth Table
Operation of the D Flip-Flop
Given Below is the operation of D Flip-Flip
 Case 1 (PR=CLR=0):This conditions is represents as invalid state where both
PR(present) and CLR(clear) inputs are inactive.
 Case 2 (PR=0 and CLR=1):This state is set state in which PR is inactive (0) and
CLR is active(1) and the output Q is set to 1.
 Case 3 (PR=1 and CLR=0):This state is reset state in which PR is active (1) and
CLR is inactive (0) and the complementary output Q' is set to 1.
 Case 4 (PR=CLR=1):In This state the flip flop behaves as normal, both PR and CLR
inputs are active(1).
Characteristics Equation for D Flip Flop
QN+1 = D
T Flip Flop
The T Flip Flop consists of data input (T), a clock input (CLK), and two outputs: Q and Q'
(the complement of Q).
Block Diagram of T Flip Flop
Given Below is the Block Diagram of T Flip Flop
 T
FLIP FLOP

Circuit Diagram and Truth Table of T Flip Flop

Given Below is the Circuit Diagram and Truth Table of T Flip Flop

Operation of the T Flip-Flop

Given Below is the Operation of T Flip-Flop
 Case 1 (T=0):In this condition the flip-flop remains in its current state regardless of
clock input,Also the Output Q will remain unchanged unit the value of T will not
change.
 Case 2 (T=1):In this condition the flip flop will change when T input is 1,At each
rising or falling edge of the clock signal the output Q will be in complementary state.
Characteristics Equation for T Flip Flop
QN+1 = Q'NT + QNT' = QN XOR T

Conversion for Flip Flops

The Excitation Table of the Flip Flop can be given as
EXCITATION TABLE:

Steps To Convert from One Flip Flop to Other

Let there be required flipflop to be constructed using sub-flipflop:
1. Draw the truth table of the required flip-flop.
2. Write the corresponding outputs of sub-flipflop to be used from the excitation table.
3. Draw K-Maps using required flipflop inputs and obtain excitation functions for sub-
flipflop inputs.
4. Construct a logic diagram according to the functions obtained.
Convert SR To JK Flip Flop
The Table for the SR To JK is given as
Excitation Functions and Logic Diagram
Function and Logic Diagram for the conversion is given below
Convert SR To D Flip Flop
The Table for the SR To JK is given as
Excitation Functions and Logic Diagram
Function and Logic Diagram for the conversion is given below

Ap
plications of Flip-Flops
These are the various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.
 Counters: The Flip Flop are used in the Counter Circuits for Counting pulse or
events.
 Frequency Dividers: The Flip Flop are used in Frequency Dividers to divide the
frequency of a input signal by a specific factor.
 Shift Registers: The Shift registers consist of interconnected flip-flops that shift data
serially.
 Storage Registers: The Storage Resistor uses Flip Flop to store data in binary
information.
 Bounce elimination switch: The Flip Flop are used in Bounce elimination switch to
eliminate the contact bounce.
 Data storage: The Flip Flop are used in the Data Storage to store binary data
temporarily or permanently.
 Data transfer: The Flip Flops are used for data transfer in different electronic parts.
 Latch: The Latches are the Sequential circuit which uses Flip Flop for temporary
storage of data
 Registers: The Registers are mode from the array of flip flop which are used to store
data temporarily.
 Memory: The Flip Flops are the main components in the memory unit for data
storage