MODULE II COMBINATIONAL LOGIC Combinational circuits - Analysis and Design

procedures –Adder - Subtractor Decimal adder – Binary Multiplier - Magnitude

Comparators -Encoder -Decoder - Multiplexer - Demultiplexer - HDL models of
combinational circuits.

Combinational circuits
A combinational circuit, also called a combinational logic circuit, is a digital electronic circuit
whose output is determined by present inputs only.

The output of a combinational logic circuit does not depend on the history of the circuit
operation.

In other words, a combinational circuit is a digital logic circuit whose output depends only on the
present input values and does not depend on any feedback or previous input or output values.

What is Combinational Circuit?

Combinational circuits are very well-known components in digital electronics, which can provide
an output instantly based on the current input. Unlike sequential circuits, a combinational circuit
listens for input signals and generates output regardless of the past input or state, as it has no
feedback or memory component.

 It only cares about the present input and state.

 They are specially designed using multiple interconnected logic gates such that the
output will be generated by computing the logical combinations of the present input only.

 No clock pulse is present here; moreover, no previously stored value or state is taken
into consideration here.

 The output is independent of previous states.

Classification of Combinational Circuits

Combinational circuits are generally grouped into three main types based on their functions:
Applications of Combinational Circuit
In modern technologies, combinational circuits are widely used for its simple functionality and
ability to give instant output. Some of the applications are discussed below:

 Data Encryption and Decryption: In information protection fields, combinational circuit

are used for Data Encryption and decryption of data for secure communication.
Encryption/decryption algorithms are also a complex mathematical formula which can be
performed by combinational circuits.

 Data Multiplexing and Demultiplexing: It is just a practical implementation of

multiplexer and demultiplexer. By using it we can optimize network bandwidth by
effectively reducing network traffic as combinational circuit allows to transmit multiple
data signals over a single communication channel.

 Traffic Light Control: In traffic lights control mechanism, combinational circuits are
used to instantly determine the timing and sequence of traffic light changes based on the
inputs of timers and sensors.
Analysis and Design procedures

Design Procedure (Synthesis)

The design procedure starts with a problem statement and creates the circuit:

1. Define the Problem: Clearly state the problem, identifying the number of inputs and
outputs.

2. Assign Variables: Assign letter symbols to all input and output variables.

3. Create Truth Table: Derive a truth table that defines the functional relationship between
inputs and outputs.

4. Simplify Boolean Expressions: Obtain the simplified Boolean functions for each output
using Karnaugh maps (K-maps) or Boolean algebra.

5. Logic Diagram: Draw the logic diagram using appropriate logic gates (AND, OR, NOT,
etc.).

6. Verify: Verify the design through simulation or manual analysis.

Analysis Procedure

The analysis procedure starts with a circuit diagram and determines its function:

1. Label Gates: Label all gate outputs that are functions of input variables with arbitrary
symbols.

2. Determine Boolean Functions: Find the Boolean functions for these gate outputs.

3. Iterate: If there are multiple levels, continue labeling outputs that depend on previous
outputs until all output expressions are defined.

4. Obtain Output Expressions: Derive the final output functions in terms of input variables
by substituting previously defined functions.

5. Create Truth Table: Create the final truth table based on the derived Boolean
expressions.

6. Summary Table
Step Design Procedure Analysis Procedure

1 Define specs & inputs/outputs Label intermediate gate outputs

2 Create truth table Determine Boolean functions for gates

3 Simplify expressions (K-maps) Obtain final output expression

4 Draw logic diagram Create truth table

5 Verify circuit Understand functionality

Adder
A binary adder is a combinational circuit that performs the addition of binary digits or bits.
Depending on the design and configuration, there are two types of binary adders namely, Half
Adder and Full Adder.

Half Adder

half adder is a basic combinational circuit that adds two single-bit binary inputs (A and B) to
produce a SUM using an XOR gate and a CARRY using an AND gate, without considering any
carry-in from a previous stage.

 Performs binary addition of two 1-bit inputs, generating a SUM (A ⊕ B) and CARRY (A ·
B).

 Cannot handle carry-in from a previous stage, making it suitable only for the first stage of
multi-bit addition.

Truth Table of Half Adder

Below is the truth table, illustrating the operation of a half adder.

logical Expression of Half Adder

Here we perform two operations Sum and Carry, thus we need two K-maps one for each to
derive the expression.

For Sum
Sum = A XOR B

For Carry

Carry = A AND B

Implementation of Half Adder

Half adder has only two inputs and there is no provision to add a carry coming from the lower
order bits when multi addition is performed.

Advantages of Half Adder in Digital Logic

 Simplicity: A half adder is a straightforward circuit that requires a couple of fundamental

parts like XOR AND entryways. It is not difficult to carry out and can be utilized in
numerous advanced frameworks.
  Speed: The half adder works at an extremely rapid, making it reasonable for use in fast
computerized circuits.

Disadvantages of Half Adder in Digital Logic

 Limited Usefulness: The half adder can add two single-piece numbers and produce a
total and a convey bit. It can't perform expansion of multi-bit numbers, which requires the
utilization of additional intricate circuits like full adders.

 Lack of Convey Info: The half adder doesn't have a convey input, which restricts its
value in more mind boggling expansion tasks. A convey input is important to perform
expansion of multi-bit numbers and to chain numerous adders together.

 Propagation Deferral: The half adder circuit has a proliferation delay, which is the time
it takes for the result to change in light of an adjustment of the info. This can cause
timing issues in computerized circuits, particularly in fast frameworks.

Application of Half Adder in Digital Logic

 Arithmetic circuits: Half adders are utilized in number-crunching circuits to add double
numbers. At the point when different half adders are associated in a chain, they can add
multi-bit double numbers.

 Data handling: Half adders are utilized in information handling applications like
computerized signal handling, information encryption, and blunder adjustment.

 Address unraveling: In memory tending to, half adders are utilized in address
deciphering circuits to produce the location of a particular memory area.

 Encoder and decoder circuits: Half adders are utilized in encoder and decoder circuits
for computerized correspondence frameworks.

 Multiplexers and demultiplexers: Half adders are utilized

in multiplexers and demultiplexers to choose and course information.

 Counters: Half adders are utilized in counters to augment the count by one.

Full Adder
Full Adder is a combinational circuit that adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM.

 The C-OUT is also known as the majority 1's detector, whose output goes high when
more than one input is high.

 A full adder logic is designed in such a manner that can take eight inputs together to
create a byte-wide adder and cascade the carry bit from one adder to another.

 We use a full adder because when a carry-in bit is available, another 1-bit adder must be
used since a 1-bit half-adder does not take a carry-in bit.

 A 1-bit full adder adds three operands and generates 2-bit results.
Full Adder Truth Table

A Full Adder takes three binary inputs:

 A (first bit)

 B (second bit)

 C-IN (carry input)

And it produces two outputs:

 Sum (S)

 Carry Out (C-OUT)

Here’s the truth table for the full adder:

INPUT OUTPUT
A B C-IN SUM C-OUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logical Expressions for SUM

From the truth table, the logical expression for the sum (S) in a full adder is:

S = A'B'C-IN + A'BC-IN' + AB'C-IN' + ABC-IN

Since A'B + AB' =A ⊕ B. This simplifies to:

S = C-IN(A ⊕ B)' + C-IN'(A ⊕ B)

The final simplified expression is:

S = A ⊕ B ⊕ C-IN

Thus, the sum output is the XOR of A, B, and C-IN.

Logical Expression for C-OUT

From the truth table, the logical expression for C-OUT (carry-out) in a full adder is:

C-OUT = A' B C-IN + A B' C-IN + A B C-IN' + A B C-IN

This simplifies to:

C-OUT = A B(C-IN'+C-IN) + C-IN(A'B+AB')

Since C-IN' + C-IN =1 and A'B + AB' =A ⊕ B. Thus, the final simplified expression is:

C-OUT = A B + C-IN (A ⊕ B)

Logic Circuit of Full Adder

To implement a Full Adder using basic logic gates:

Sum (S) is implemented using XOR gates:

Use two XOR gates:

 First XOR gate: A ⊕ B

 Second XOR gate: (A ⊕ B) ⊕ C-IN to get the final sum S.

Carry (C-Out) is implemented using XOR,AND and OR gates:Finally, the two outputs from the
AND gates are combined using an OR gate to generate the final C-OUT output.

First AND gate: This gate calculates A AND B.

Second AND gate: This gate calculates C-IN AND (A ⊕ B). To do this, you need the result of
the first XOR gate (A ⊕ B) as an input to the second AND gate.
Subtractor
A binary subtractor is a combinational logic circuit used to subtract one binary number from
another. Similar to binary adder, there are two types of binary subtractors namely, half
subtractor and full-subtractor.

Half Subtractor in Digital Logic

A half subtractor is a digital logic circuit that performs the binary subtraction of two single-bit
binary numbers. It has two inputs, A and B, and two outputs, Difference and Borrow.
The Difference output represents the result of subtracting B from A, while the Borrow output
indicates whether a borrow is needed when A is smaller than B.

The half subtractor can be implemented using basic logic gates such as XOR, AND, and
NOT gates. It is a fundamental building block for more complex arithmetic circuits like full
subtractors and multi-bit subtractors.

Truth Table of Half Subtractor

Logical Expression of Half Subtractor

For difference,
The SOP form of the Difference is as follows:

Difference = A'B+AB'

For borrow,

The SOP form of the Borrow is as follows:

Borrow = A'B

Implementation of Half Subtractor

Advantages of Half Subtractor

 Simplicity: The half subtractor circuits are simple and easy to design, implement, and
debug compared to other binary arithmetic circuits.

 Building blocks: The half subtractor is basic building block that can be used to
construct more complex arithmetic circuits, such as full subtractors, multiple-bit
subtractors.
  Low cost: The half subtractor circuits use only a few gates, which reduces the cost and
power consumption compared to more complex circuits.

 Easy integration: The half subtractor can be easily integrated with other digital circuits
and systems.

Disadvantages of Half Subtractor

 Limited functionality: The half subtractor can only perform binary subtraction of two
single-bit numbers, respectively, and not suitable for more complex arithmetic
operations.

 Inefficient for multi-bit numbers: For multi-bit numbers, multiple half subtractors need
to be cascaded, which increases the complexity and decreases the efficiency of the
circuit.

 High propagation delay: When cascaded for multi-bit operations, the cumulative
propagation delay of half subtractors becomes higher compared to dedicated multi-bit
subtractors (e.g., using look-ahead borrow).

Application of Half Subtractor in Digital Logic

 Calculators: Most mini-computers utilize advanced rationale circuits to perform

numerical tasks. A Half Subtractor can be utilized in a number cruncher to deduct two
parallel digits from one another.

 Alarm Systems: Many caution frameworks utilize computerized rationale circuits to

identify and answer interlopers. A Half Subtractor can be utilized in these frameworks to
look at the upsides of two parallel pieces and trigger a caution in the event that they are
unique.

 Automotive Systems: Numerous advanced vehicles utilize computerized rationale

circuits to control different capabilities, like the motor administration framework, stopping
mechanism, and theater setup. A Half Subtractor can be utilized in these frameworks to
perform computations and examinations.

 Security Frameworks: Advanced rationale circuits are usually utilized in security

frameworks to identify and answer dangers. A Half Subtractor can be utilized in these
frameworks to look at two double qualities and trigger a caution in the event that they are
unique.

 Computer Frameworks: Advanced rationale circuits are utilized broadly in PC

frameworks to perform estimations and examinations. A Half Subtractor can be utilized in
a PC framework to deduct two paired values from one another.

Full Subtractor in Digital Logic

A Full Subtractor is a combinational circuit used to perform binary subtraction. It has three
inputs:

 A (Minuend)
  B (Subtrahend)

 B-IN (Borrow-in from the previous stage)

It produces two outputs:

 Difference (D): The result of the subtraction.

 Borrow-out (B-OUT): Indicates if a borrow is needed for the next stage.

The full subtractor is essential because a half-subtractor can only subtract the least significant
bit (LSB) of binary numbers. However, if a borrow is generated during the subtraction of the
LSBs, it will affect the subtraction in the next stages. A full subtractor handles this situation by
considering the borrow from the previous stage, ensuring accurate subtraction even when a
borrow is present.

The full subtractor is used to subtract binary numbers with borrow handling, making it suitable
for multi-bit subtraction in digital circuits like Arithmetic Logic Units (ALUs).

Truth Table of Full Subtractor

INPU
T OUTPUT

A B B-IN D B-OUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Full Subtractor

From above table we can draw the K-Map as shown for "difference" and "borrow"

Logical expression for difference

The basic expression is:

D = A'B'Bin + A'BBin' + AB'Bin' + ABBin

Factoring common terms:

D = Bin(A'B' + AB) + Bin'(AB' + A'B)

Recognizing XOR and XNOR properties:

A'B' + AB = A XNOR B
AB' + A'B = A XOR B

Substituting these values:

D = Bin(A XNOR B) + Bin' (A XOR B)

Using XNOR identity:

D = Bin ⊕ (A ⊕ B)

D = (A ⊕ B) ⊕ Bin
Thus, the final simplified expression for the difference in a full subtractor is:

Logical expression for borrow

The borrow (Bout) output is derived as follows:

The basic expression:

Bout = A'B'Bin + A'BBin' + A'BBin + ABBin

Factoring common terms:

Bout = A'Bin(B + B') + A'B(Bin + Bin') + BBin(A + A')

Simplifying:

Bout = A'Bin + A'B + BBin

Alternatively, using another approach:

Bout = A'B'Bin + A'BBin' + A'BBin + ABBin

Factoring common terms:

Bout = Bin(AB + A'B') + A'B(Bin + Bin')

Using XOR and XNOR properties:

AB + A'B' = A XNOR B

Substituting these values:

Bout = Bin(A XNOR B) + A'B

Using XNOR identity:

Bout = Bin (A XOR B)' + A'B

Thus, the final simplified expression for borrow in a full subtractor is:
Logic Circuit for Full Subtractor

Magnitude Comparator
What is Magnitude Comparator?

Magnitude comparator is a type of Combinational circuit, It Basically compares two binary

numbers and determines their relative magnitude. It gives output whether one number is greater
than the other, or less than or equal. These comparators are used in digital systems, such as for
sorting networks, and decision-making circuits to handle numerical comparisons perfectly
without any error.

The circuit works by comparing the bits of the two numbers starting from the most significant bit
(MSB) and moving toward the least significant bit (LSB). At each bit position, the two
corresponding bits of the numbers are compared. If the bit in the first number is greater than the
corresponding bit in the second number, the A>B output is set to 1,and the circuit immediately
determines that the first number is greater than the second. Similarly, if the bit in the second
number is greater than the corresponding bit in the first number, the A<B output is set to 1,
and the circuit immediately determines that the first number is less than the second.

If the two corresponding bits are equal, the circuit moves to the next bit position and compares
the next pair of bits. This process continues until all the bits have been compared. If at any point
in the comparison, the circuit determines that the first number is greater or less than the second
number, the comparison is terminated, and the appropriate output is generated.

If all the bits are equal, the circuit generates an A=B output, indicating that the two numbers
are equal.

There are different ways to implement a magnitude comparator, such as using a combination of
XOR, AND, and OR gates, or by using a cascaded arrangement of full adders. The choice of
implementation depends on factors such as speed, complexity, and power consumption.

1-Bit Magnitude Comparator

A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs
each for two single-bit numbers and three outputs to generate less than, equal to, and greater
than between two binary numbers.

The truth table for a 1-bit comparator is given below.

1-Bit Magnitude Comparator

A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs
each for two single-bit numbers and three outputs to generate less than, equal to, and greater
than between two binary numbers.

The truth table for a 1-bit comparator is given below.

From the above truth table logical expressions for each output can be expressed as follows.

A>B: AB'

A<B: A'B

A=B: A'B' + AB =AXNORB

From the above expressions, we can derive the following formula.

By using these Boolean expressions, we can implement a logic circuit for this comparator as
given below.

2-Bit Magnitude Comparator

A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and
greater than between two binary numbers.

The truth table for a 2-bit comparator is given below.

 INPUT OUTPUT

A1 A0 B1 B0 A<B A=B A>B

0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
From the above truth table, K-map for each output can be drawn as follows.

Truth Table of Output A>B

Truth Table of Output A=B

Truth Table of Output A<B

From the above K-maps logical expressions for each output can be expressed as
follows.

A>B: A1B1’ + A0B1’B0’ + A1A0B0’

A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’

A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)

(A0B0 + A0’B0’) (A1B1 + A1’B1’)

(A0 Ex-Nor B0) (A1 Ex-Nor B1)

A<B: A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below.
Applications of Comparators

 Comparators are used in central processing units (CPU s) and microcontrollers (MCUs).

 These are used in control applications in which the binary numbers representing
physical variables such as temperature, position, etc. are compared with a reference
value.

 Comparators are also used as process controllers and for Servo motor control.

 Used in password verification and biometric applications.

Advantage of Comparator

 Comparators are simple and efficient for comparison of binary values.

 Fast decision-making in Digital Circuits.

 This comparator can be easily integrated in to complex systems like processors and
arithmetic units.

 Design of comparator are modular, which allow them to scale solutions for comparing
multi-bit numbers
Disadvantages of Comparator

 Comparators have limit of bits for comparison.

 It requires more complex circuit for large bits.

 Power consumption increases with increase in the complexity of the circuit.

Encoders and Decoders

Binary code of N digits can be used to store 2N distinct elements of coded information. This is
what encoders and decoders are used for.

Encoders convert 2N lines of input into a code of N bits and Decoders decode the N bits into
2N lines.

1. Encoders - An encoder is a combinational circuit that converts binary information in the form
of a 2N input lines into N output lines, which represent N bit code for the input. For simple
encoders, it is assumed that only one input line is active at a time. As an example, let’s
consider Octal to Binary encoder. As shown in the following figure, an octal-to-binary encoder
takes 8 input lines and generates 3 output lines.

Truth Table –

D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

As seen from the truth table, the output is 000 when D0 is active; 001 when D1 is active; 010
when D2 is active and so on.

Implementation -

From the truth table, the output line Z is active when the input octal digit is 1, 3, 5 or 7. Similarly,
Y is 1 when input octal digit is 2, 3, 6 or 7 and X is 1 for input octal digits 4, 5, 6 or 7. Hence, the
Boolean functions would be:

X = D4 + D5 + D6 + D7
Y = D2 +D3 + D6 + D7
Z = D1 + D3 + D5 + D7

Hence, the encoder can be realized with OR gates as follows:

One limitation of this encoder is that only one input can be active at any given time. If more than
one inputs are active, then the output is undefined. For example, if D6 and D3 are both active,
then, our output would be 111 which is the output for D7. To overcome this, we use Priority
Encoders. Another ambiguity arises when all inputs are 0. In this case, encoder outputs 000
which actually is the output for D0 active. In order to avoid this, an extra bit can be added to the
output, called the valid bit which is 0 when all inputs are 0 and 1 otherwise.

Priority Encoder -

A priority encoder is an encoder circuit in which inputs are given priorities. When more than one
inputs are active at the same time, the input with higher priority takes precedence and the
output corresponding to that is generated. Let us consider the 4 to 2 priority encoder as an
example. From the truth table, we see that when all inputs are 0, our V bit or the valid bit is zero
and outputs are not used. The x’s in the table show the don’t care condition, i.e, it may either be
0 or 1. Here, D3 has highest priority, therefore, whatever be the other inputs, when D3 is high,
output has to be 11. And D0 has the lowest priority, therefore the output would be 00 only when
D0 is high and the other input lines are low. Similarly, D2 has higher priority over D1 and D0 but
lower than D3 therefore the output would be 010 only when D2 is high and D3 are low (D0 & D1
are don’t care).

2. Decoders
A decoder is a combinational circuit that performs the reverse operation of an encoder,
converting n input lines into 2ⁿ output lines, with only one output active for each input
combination.

Let’s take an example of 3-to-8 line decoder.

Truth Table -

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Implementation -

D0 is high when X = 0, Y = 0 and Z = 0. Hence,

D0 = X’ Y’ Z’

Similarly,

D1 = X’ Y’ Z
D2 = X’ Y Z’
D3 = X’ Y Z
D4 = X Y’ Z’
D5 = X Y’ Z
D6 = X Y Z’
D7 = X Y Z

Hence,
Multiplexer
What is a Multiplexer?

As already mentioned, a multiplexer, also referred to as MUX, is a combination logic circuit that
is designed to accept multiple input signals and transfer only one of them through the output
line. In simple words, a multiplexer is a digital logic device that selects one-out-of-N (N = 2 n)
input data sources and transmits the selected data to a single output line.

The multiplexer is also called data selector as it selects one from several. The block diagram of
a typical 2n:1 multiplexer is shown in Figure 1.

In the case of multiplexer, the selection of desired data input to flow through the output line is
controlled with the help of SELECT lines. In the block diagram of mux in Figure 1, I0, I1,... In-1,
i.e., (2n) are the input lines, and "n" be the select lines. These select lines will determine which
input is to be routed to the output.

Hence, the multiplexer works as a multi-position switch whose operation is controlled by digital
signals. These digital control signals are applied to the select lines to determine which data
input will be switched to the output line

Function of Multiplexer

Multiplexer is a digital logic device which is used to perform multiplexing of data. Where,
multiplexing simply means sharing of data. Technically, when a particular data is selected from
multiple input data sources and transmitted the selected data to a single output channel, it is
called multiplexing.

There are two types of multiplexing namely, frequency multiplexing and time multiplexing.

When multiple devices are connected to a single transmission line in a system. At any point of
time, only one device is using the line to transmit data, then this is called time multiplexing. On
the other hand, when multiple devices share a common line to transmit data but at different
frequencies, it is called frequency multiplexing.

Types of Multiplexers

Based on input data lines and select lines, the multiplexer can be of several types. But, in this
article, we will discuss only the following three types of multiplexers −

 2×1 Multiplexer

 4×1 Multiplexer

Let us discuss each of these three multiplexers individually.

2×1 Multiplexer
The block diagram of a 2×1 multiplexer is shown in Figure 2. The 2×1 multiplexer is basic two
input multiplexer which has two data input lines designated as I0 and I1, one data select line
denoted by S and one output line denoted by Y. The 2×1 mux is used to connect two 1-bit data
sources to a common designation.

In the 2×1 multiplexer, the logic level of the digital signal applied to the select line S determines
which data input will pass through the output line. The operation of the 2×1 multiplexer can be
understood from the following truth table.

Select Line (S) Output (Y)

0 I0

1 I1

4×1 Multiplexer
4×1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4×1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines. Truth table of 4×1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4×1 multiplexer is shown in the following figure.
We can easily understand the operation of the above circuit. Similarly, you can implement 8×1
Multiplexer and 16×1 multiplexer by following the same procedure.

Applications of Multiplexers

In digital electronics, multiplexers have numerous applications in almost all types of digital
systems. Some important applications of multiplexers are as follows −

 Data routing and data selection

 Parallel to series conversion

 Logic function implementation

 Generation of waveform, etc.

Demultiplexer

What is a Demultiplexer?

A Demultiplexer is a combinational logic circuit that accepts a single input and distributes it
over several output lines. Demultiplexer is also termed as DEMUX in short. As Demultiplexer is
used to transmit the same data to different destinations, hence it is also known as data
distributor.

There is another combinational logic circuit named multiplexer which performs opposite
operation of the Demultiplexer, i.e. accepts several inputs and transmits one of them at time to
the output line.

From the definition, we can state that a Demultiplexer is a 1-to-2n device. The functional block
diagram of a typical 1×2n Demultiplexer is shown in Figure-1.

It can be seen that the Demultiplexer has only one data input line, 2n output lines, and n select
lines. The logic level applied to select lines of the Demultiplexer determines the output channel
to which the input data will be transmitted.

Demultiplexer circuit are the combinational logic circuit widely used in digital decoders and
Boolean function generator circuits.

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Types of Demultiplexer

Based on the number of output lines (2n), Demultiplexers can be classified into several types.
Some commonly used types of Demultiplexers are −

 1×2 Demultiplexer

 1×4 Demultiplexer

Now, let us briefly discuss each type of Demultiplexer.

1×2 Demultiplexer
The functional block diagram of a 1×2 Demultiplexer is shown in Figure-2.

The 1×2 Demultiplexer consists of 1 input line (I), 1 select line (S), and 2 output lines (Y 0 and
Y1). The logic level applied at the select line determines the output line to which the input data
will be transmitted.

The operation of the 1×2 Demultiplexer can be analyzed with the help of its function table given
below.

Select Line Outputs

S Y1 Y0

0 0 I

1 I 0

From this function table of 1×2 Demultiplexer, we can directly derive the Boolean expression for
each output as follow.

1×4 Demultiplexer
The functional block diagram of 1×4 Demultiplexer is shown in Figure-3.

The 1×4 Demultiplexer has 1 input line (I), 2 select line (S0 and S1), and 4 output lines (Y0, Y1,
Y2, and Y3). The logic level applied to the select lines determines the output line to which the
input data (I) will be transmitted.

The operation of the 1×4 Demultiplexer can be understood with the help of its function table
given below.

Select Line Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From this truth table of 1×4 Demultiplexer, we can directly write the Boolean expression for each
output as follow.

We can easily understand the operation of the above circuit. Similarly, you can implement 1×8
Demultiplexer and 1×16 Demultiplexer by following the same procedure.
Applications of Demultiplexer

Demultiplexer is a crucial combinational logic circuit which is used in a number of applications.

Some important uses of Demultiplexers are listed below −

 Demultiplexer are used in several input and output devices for data routing.

 Demultiplexer are used in digital control systems to select one signal from a mutual
stream of signals.

 Demultiplexer are also employed for data transmission in synchronous systems.

 Demultiplexer are also utilized in data acquisition systems.

 Demultiplexer can be used for generating Boolean functions.

 Demultiplexer can be used in serial to parallel converters.

 Demultiplexer are used for broadcasting of ATM packets.

 Demultiplexer can also be used to design automatic test equipment, etc.

Difference Multiplexer Demultiplexer

A multiplexer is a combinational digital A demultiplexer is a combinational

Definition circuit that takes multiple data inputs digital circuit that takes single input
and provides only single output. and provides multiple outputs.

Abbreviated The abbreviation used to represent the The abbreviation used to represent
name multiplexer is MUX. the demultiplexer is DEMUX.

Multiplexer has 2n input lines and 1 Demultiplexer has 1 input line

Input and output
output line. Where, n is the number of and 2n output lines. Where, n is the
lines
select lines. number of select lines.

Multiplexer is also known as a "data Demultiplexer is also known as

Also known as
selector". "data distributor".

Operating The operating principle of the The operating principle of a

principle multiplexer is "many to one". demultiplexer is "ne to many".

Acts as Multiplexer acts as a digital multi- Demultiplexer acts as a digital

 position switch. circuit.

Conversion A multiplexer performs parallel to serial A demultiplexer performs serial to

technique conversion. parallel conversion.

In case of multiplexer, the function of In demultiplexer, the function of

Function of control signal is to select a specific control signal is to deliver the
control signal input that has to be transmitted at the single input signal over the multiple
output. output lines.

Examples of some common Some common demultiplexers are

multiplexers are  1:2 Demultiplexer

Examples  8:1 Multiplexer  1:4 Demultiplexer

 16:1 Multiplexer  1:8 Demultiplexer
 32:1 Multiplexer  1:16 Demultiplexer

In practice, the multiplexer increases In practice, the demultiplexer takes

Practical the efficiency of the communication the output of a multiplexer and
importance system by enabling the data convert in its original form at the
transmission using a single line. receiver end.

Usage in time- A multiplexer is used at the transmitter The demultiplexer is used at the
division end in the time-division multiplexing receiver end in the time-division
multiplexing (TDM). multiplexing.

The demultiplexers are used in

The multiplexers are commonly used in
communication systems,
Applications communication systems, telephone
reconstruction of parallel data,
networks, computer memories, etc.
ALU, etc.
Key HDL Modeling Styles for Combinational Circuits

 Gate-Level Modeling: Directly maps the physical schematic using logic gates
(and, or, xor, not) and predefined primitives to define circuit structure. Example: xor g1(s,
a, b);.

 Dataflow Modeling: Uses the assign keyword to describe circuit function with Boolean
equations rather than specific gates. It is efficient for describing logical operations.
Example: assign Y = (A & S) | (B & ~S);.

 Behavioral Modeling: Uses always blocks and procedural assignments to describe the
high-level functionality. For combinational logic, this requires a sensitivity list containing
all inputs or a sensitivity list (*) for automatic detection.

 User-Defined Primitives (UDP): Defines custom logic gates or small modules when
standard primitives are insufficient.

Common Combinational Circuit Examples in HDL

 Half/Full Adder: Modeled using xor and and gates or + operator.

 Multiplexer (MUX): Often modeled using a conditional operator (? :) in dataflow or if-

else/case in behavioral style.

 Decoder/Encoder: Represented using boolean expressions for each output line.

 Magnitude Comparator: Modeled using relational operators (>, <, ==).

Key Considerations

 Sensitivity Lists: In always blocks, omitting inputs can lead to mismatched simulation
and synthesis results (creating unintended latches).

 Propagation Delay: HDL can model gate delays (#delay) to simulate real-world timing
behavior.

 Synthesis: Dataflow and behavioral styles are generally preferred for RTL (Register
Transfer Level) design as they are easier to synthesize into gate-level netlists.