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Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full
Adder

Conference Paper · March 2018

DOI: 10.1109/IBCAST.2018.8312254

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 Low Power 4×4 Bit Multiplier Design using Dadda
Algorithm and Optimized Full Adder
Muhammad Hussnain Riaz 1ŏō, Syed Adrees Ahmed 1ō, Qasim Javaid 1ō, Tariq Kamal2

Abstract- This paper presents the model of 4-bit multiplier Sect. IV and V; results in Sect VI; while the conclusion is in
having low power and high speed using Algorithm named Sect. VII.
Dadda and the basic building block used is optimized Full II. PREVIOUS RESEARCH
adder having low power dissipation and minimum propagation Different techniques such as; merged delay transformation [1-
delay. Full and half adder blocks have been designed using 2], genetic algorithm [3-5], evolutionary algorithm [6], delay
pass-transistor logic and CMOS process technology to reduce path Un-equalization [7], carry-look-ahead logic [8], etc. have
the power dissipation and propagation delay. We have also been used and implemented to design digital circuits having low
applied Dadda algorithm to reduce the propagation delay. The power dissipation, minimum delay and to achieve maximum
model has been designed using Cadence Virtuoso in 90-nm throughput in minimum response time. Techniques include
technology. The proposed multiplier starts its operation at the pass-transistor logic CMOS process technology, adiabatic static
frequency of 3.83 GHz and its average dynamic power is 184.3 CMOS logic, reversible logic, etc. Multiplier using Pass
μW at the supply of 1V. transistor logic technique is one which uses a reduced number of
transistors and offers small node capacitances which produces
Keywords— Dadda Algorithm, Hybrid Design, Optimized minimum delay and increase the speed of the circuit. Multipliers
Full Adder, 4×4 Bit Multiplier having reversible logic have reduced power dissipation.
Multipliers’ having adiabatic static CMOS logic produce
I. INTRODUCTION minimum heat while transferring the charges.
Multiplication is the basic process which is used in different
III. PROPOSED RESEARCH
electronic and in various digital communication applications.
Multipliers with low latency and minimum power dissipation In the proposed research, a modified circuit of the 4*4
are preferred to design an optimized circuit so that maximum multiplier is proposed. This multiplier circuit is based on the
throughput can be achieved in minimum response time. optimized full adder which uses 12 transistors i.e., 12T. The
Building blocks used in multipliers are a full adder and a half design of full adder is hybrid i.e., the design consists of two
adder. Different design implementations of a full adder and half techniques, pass-transistor logic, and CMOS process
adder circuits have been used to reduce power and delay in technology. Full adder and a half adder as the building block of
order to design an optimized multiplier circuit which includes the circuit have low propagation delay and low power delay
pass transistor logic, CMOS process technology, split product. The power and delay of this full adder are low as
percentage data-driven logic and CMOS process technology. compared to other previous designed full adders. This ultimately
Besides this, different multiplication algorithms also have been results in the formulation of multipliers having low propagation
used to achieve optimized power and delay product which delay and minimum power dissipation.
includes Dadda, Wallace tree, and Vedic and Booth algorithms.
The Recent multiplier used Reduced-sp-D3Lsum Adder and A. DADDA TREE ALGORITHM
Dadda Algorithm technique. This design operates at high Different algorithms have been proposed to decrease the
frequency and consumes less power as compared to previous propagation delay during the addition of the partial products
designs, but still, power needs to be significantly reduced, so, it generated by AND Gate. One of the most efficient algorithms is
will help in the larger circuits where multiplier itself becomes Dadda algorithm. The proposed 4*4 multiplier has a total of 16
the building block [8]. In proposed work, a multiplier has been partial products, so, the height of the tree is four as shown Fig.
designed in which Full adder and half adder has been used as its 1. Dadda Algorithm has been applied for the purpose to reduce
building block to reduce the power dissipation by using pass- the height of the tree from four to two. If we do not apply Dadda
transistor logic and CMOS technology process. Dadda algorithm, then we must have to wait for the previous stage to
Algorithm has been used to reduce the propagation delay of the simulate it, because, the next stage uses the carry of the previous
multiplier. The paper has been ordered according to this flow. stage which will increase the propagation delay. For this simple
Previous research regarding multiplier and full adder has been technique, we have to use the ripple carry adder, it also
presented in Sect. II; proposed research is described in Sect. III; consumes less power, but the delay is significantly high. To
block diagrams and algorithm implementation are covered in reduce the overall propagation delay of the multiplier Dadda
1,* algorithm has been applied.
Department of Electrical Engineering, Syed Babar Ali School of Science
and Engineering, Lahore University of Management Sciences (LUMS), Lahore, This is the best technique for reduction in the delay of the
Pakistan; Email; hussnainriaz8@[Link] overall multiplier design because, at the start, it does not depend
1* on the previous stage. Therefore, the first stage will be
Department of Electrical Engineering, COMSATS Institute of Information
Technology Wah Cantt, Pakistan; implemented without depending on any other stage. First, we
2 have arranged our partial products to make a tree as shown in
Department of Electrical & Electronics Engineering, Faculty of Engineering,
Sakarya University, Turkey; Fig. 1. These partial products are generated by the AND gate.

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The height of this tree is 4 as the proposed design is the 4-bit C. ALGORITHM IMPLEMENTATION
multiplier. We apply the Dadda algorithm on this tree to reduce the height
B. STAGES OF DADDA ALGORITHM of the tree. At the first stage: tree has a height of 4 which we
The objective is to reduce the height of the tree from four to need to reduce by using full adders and half adders. Hence, we
two. Therefore, building blocks have been used in such a way to have applied a full adder on the 4th column to reduce its height
reduce the tree height from four to three after the completion of also we have applied half adder on the 2nd column and two
first Dadda stage and then from three to two after the more full adders on the 3rd and 5th column to adjust the tree
completion of the second Dadda Stage. Furthermore, the two height to 3. Now these HA and FA are working in parallel and
Dadda stages are used to reduce this tree. The first and second no one is dependent on the previous stage. Figure 3 and 4
Dadda stages are shown in Fig. 2 and Fig. 3, respectively. shows the more tree reduction and in the final stage, we have
used a ripple carry adder. The count of the half adder and full
adder used in the Dadda stages are given by these formulas
Half adder= H-1 Full adder=H2-4H+5

IV. BLOCK DIAGRAM

THE BLOCK DIAGRAM OF OUR PROPOSED MULTIPLIER IS SHOWN

IN FIG. 5.

Figure 1: 4 × 4 Multiplications.

Figure 2: First Dadda Stage

Figure 5: Block Diagram of the proposed Multiplier

The working stages of the proposed model are as follows:
1. In the first step, 16 partial products are generated using
AND gate.
2. In the second step, the height of the tree is reduced
Figure 3: Second Dadda Stage using Dadda stage using one-half adder (HA) and
three full adders (FA).
3. In the third step, the reduction is done by two half
adders and two full adders.
4. At last stage of Dadda, we have used a ripple carry
adder.
5. Finally, results are passed through the buffer to make
the output voltages better (smooth).
Figure 4: Last Dadda Stage V. BUILDING BLOCKS OF PROPOSED
For a 4*4 tree reduction, stages are as given below MULTIPLIER
i. First stage with a height of four.
ii. Second stage with a height of three. THE BLOCKS THAT ARE USED IN THE PROPOSED DESIGN OF
MULTIPLIER ARE AS UNDER:
iii. Finally, the third stage with a height of two.

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A. AND GATE
The proposed model has AND gate for the multiplication of
4*4 multiplier. Consequently, for the 4*4 multiplication, a total
of 16 products are generated. Therefore, it has used 16 AND
gates for multiplication. The schematic of the AND gate is
shown in Fig. 6 while its behavior at different frequencies is
shown in table 1. The average dynamic power of AND gate at
5GHz is 7.65μW with a delay of 0.05 nS. The graphical Figure 8: Proposed XOR Module
representation of Power delay product (PDP) of AND gate at
different frequencies is shown in Fig.7.

Figure 9: XNOR Module

The XNOR module is shown in Fig.9 by just inverting the
output of the XOR module. The equation of the XNOR module
is:
Figure 6: Two input AND gate. XNOR=AB + A'B'
Frequency(GHz) Power(μW) Delay(nS) PDP (fj) We have inverted this, because, it will be used in the formation
1 1.51 0.034 0.05 of the second XOR module that will generate the Sum of the
Full adder. As described above, in that case, we have connected
2 3.05 0.029 0.08 the PMOS source to the XOR module output, while that of
5 7.65 0.05 0.38 NMOS source to the XNOR output. For the generation of
Table 1: AND Gate behavior at different frequencies. carrying we have used two pass transistors. On one pass
transistor, we have applied an input C while on the second pass
transistor we have applied an input B. The schematic of the full
adder is shown in Fig. 10 while its behavior at different
frequencies is shown in table 2. The average dynamic power of
Full adder at 3GHz is 17.5­W with a delay of 0.02 nS.
The equation for the full adder is:
Sum = A Ͱ B Ͱ C Carry = AB + BC + AC
The carry equation if further reduced to If A=B then Carry=A
else Carry=C
Figure 7: Graphical representation of Power delay product of
two input AND gate.
B. FULL ADDER
A full adder is a major block in the multiplier. In proposed
model Full adder has been modified in order to produce
minimum propagation delay and less power dissipation of the
circuit, so, that it can further be used to design multiplier having
optimized parameters including Power, delay, and less layout
area. Proposed modified XOR module in the Full adder is Figure 10: Proposed Full Adder
composed of four transistors. The schematic of the proposed
XOR module is shown in Fig. 8. We have inverted one input Frequency(GHz) Power(μW) Delay(nS) PDP (fj)
i.e., B input because the B and B’ will be used in the next two 1 12.96 0.03 0.38
transistors. We have cascaded a PMOS with NMOS while 2 15.21 0.02 0.304
applying the second input A to the gate terminal of both PMOS 3 17.5 0.02 0.35
and NMOS and instead of connecting the source of the PMOS
Table 2: Full Adder behavior at different frequencies
to Vdd we connected it to the first input B, similarly we have
connected the source of the NMOS to the inverted first input It can be easily shown from the above table that proposed full
i.e., B’, which constitutes XOR module. The equation of the adder is consuming less power as well as the delay of the
XOR module is: proposed full adder is less. The graphical representation of PDP
of the full adder at different frequencies is shown in Fig. 11
XOR=A'B + AB'

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 Figure 14: Buffer
Figure 11: Graphical representation of Power delay product of
Full Adder VI. RESULTS
C. HALF ADDER For the proposed 4*4 multiplier the inputs A3, A2, A1, A0, B3,
A half adder is another building block of the multiplier. We B2, B1, and B0 are pulses varying from 0 to 1. The operating
used total four half adders in the multiplier design. The frequency of the proposed multiplier is 3.84GHz. The
schematic of the half adder is shown in Fig. 10, while its comparison of the proposed multiplier with another multiplier is
behavior at different frequencies is shown in table 3. The shown in Table.4.
average dynamic power of half adder at 3GHz is 9.66μW with a Desi Technique Del Fr Dyna Static Power PDP
delay of 0.03 nS. The graphical representation of PDP of Half gn ay eq mic A=1111 (fJ)
adder at different frequencies is shown in Fig. 13. Adder Multiplier
(ns) (G Powe A=0000
Hz r B=1111
) (μW) B=0000
(mW)
(μW)
Prop 0.0 3.8 184.3 0.015 16.58
osed Hybrid Dadda 9 4 27.29 7
Algorithm
[8] 0.2 3.8 623 1.034 241.8
Reduced Dadda 620 1 59.6 26
Sp-D3Lsum Algorithm
[6] 0.2 3.3 1100 1.287 323.6
Sp-D3Lsum Dadda 942 9 1.04 2
Algorithm
[9] CMOS Row by 0.6 1.5 784 1.054 79 500.1
Passing 379 6 14

Table 4: Multiplier Behaviour at different Frequencies

Figure 12: Half Adder Fig. 15 and Fig.16 shows the dynamic power and power delay
Frequency(GHz) Power(μW) Delay(nS) PDP (fj) product comparison of the proposed multiplier with other
multiplier designs. It is also shown from the graphical
1 3.18 0.05 0.159
representation that the proposed designed is better in terms of
2 6.38 0.04 0.255 power and PDP. Fig. 17 shows the zoomed portion of the layout
3 9.66 0.03 0.289 of the proposed multiplier. The layout is designed using DSCH
Table 3: Behavior of half adders at different frequencies 2.6c and Micro wind 2.6a. The layout is verified using the
Verilog file generated by the DSCH for the proposed multiplier.

Figure 15: Graphical representation of Dynamic Power of

different Multipliers
Figure 13: Graphical representation of Power delay product of
Half Adder
D. BUFFER
The buffer is an amplifier having unity gain. The main function
of the buffer is to provide drive capability to pass signals to the
final stage. Voltage buffer is used to increase the available
current for the circuits having low impedance while retaining
the voltage level. On the other hand, current buffers keep the
current same and drive the high impedance inputs at higher
voltage levels. The average dynamic power of buffer at 3GHz is Figure 16: Graphical representation of Power delay product of
6.877μW with a delay of 0.03 nS. different Multipliers

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