VISVESVARAYA TECHNOLOGICAL UNIVERSITY
“Jnana Sangama”, Belagavi-18, Karnataka, India.
Synopsis on
“Design and Implementation of a Low-Latency UART
Communication System with Adaptive Baud Rate and
Packet Protocol on FPGA”
Mini-Project Submitted in partial fulfillment of the requirement for the degree of
Bachelor of Engineering
In
Electronics and Telecommunication Engineering
By
Aditya 1DS24ET009
Divyanka Rajhans 1DS24ET033
Samarthya Sharan 1DS24ET087
Mayuresh Pai 1DS24ET060
th
4 sem B.E
Under the guidance of
Dr. Anitha Suresh
Assistant Professor
Department of Electronics and Telecommunication Engineering
DAYANANDA SAGAR COLLEGE OF ENGINEERING
BENGALURU -560078
2025-26
ABSTRACT
Universal Asynchronous Receiver Transmitter (UART) is a widely used serial communication
protocol for reliable data exchange between digital devices due to its simple architecture and low
hardware requirements. This project presents the design and implementation of an enhanced UART
communication system using Verilog Hardware Description Language (HDL) on an FPGA
platform. The main objective of the project is to develop a robust UART transmitter and receiver
architecture while improving communication efficiency through the integration of adaptive baud
rate control, FIFO buffering, and a packet-based command protocol.
The proposed system consists of several functional modules including the baud rate generator,
UART receiver, FIFO buffer, packet parser, command decoder, and UART transmitter. The baud
rate generator produces the required timing signals and allows dynamic selection of communication
speeds using hardware switches. The UART receiver converts incoming serial data into parallel
form, which is temporarily stored in the FIFO buffer to prevent data loss and manage differences in
processing speed between modules. The packet parser identifies valid communication packets
using predefined start and stop markers, and extracts the command and data fields. The command
decoder interprets the received commands and performs the corresponding operations. The UART
transmitter then converts the processed data or response into serial form for transmission.
The entire system is designed using Verilog HDL and verified through simulation to ensure correct
functionality of all modules. The design is implemented on a Cyclone IV FPGA development
board, enabling real-time hardware testing and demonstration. Additional input controls such as
push buttons are used to generate test commands, further illustrating system functionality.
The results demonstrate that the proposed design enables reliable UART communication with
improved data handling through buffering and structured packet-based communication. The
modular architecture also allows easy expansion and integration with other digital systems such as
displays, sensors, and embedded controllers. This project highlights the practical application of
FPGA-based digital design techniques and provides a foundation for developing more advanced
communication interfaces used in embedded systems, industrial automation, and Internet of Things
(IoT) applications.
Literature Survey
FPGA-Based UART Communication Systems
Serial communication protocols are widely used in embedded systems for reliable data exchange
between digital devices. One of the most common protocols is the Universal Asynchronous
Receiver Transmitter (UART), which allows asynchronous serial communication between devices
without a shared clock signal. UART communication is commonly implemented in
microcontrollers, FPGAs, and communication interfaces because of its simplicity and reliability.
Recent research has focused on improving UART systems by enhancing transmission speed, error
detection capability, hardware efficiency, and reliability when implemented on FPGA platforms.
Several studies have explored the design and implementation of UART modules using Verilog
HDL and FPGA devices.
Title Key Findings Draw Backs
1. Design and ● UART can efficiently
Implementation of transmit data using ● The design primarily
UART Based on asynchronous focuses on basic
Verilog HDL communication UART operation and
[2023] without clock does not include
synchronization advanced error
between devices. detection or
correction
● The modular mechanisms.
architecture simplifies
the design process and ● Hardware
improves flexibility. implementation
analysis such as power
● The system allows consumption and
configurable baud FPGA resource
rates to support utilization is limited.
different
communication
speeds.
2. Verilog-Based ● The proposed ● The study focuses
High-Speed UART architecture supports primarily on
Communication configurable baud improving
System rate generation, communication speed
[2024] allowing flexible and does not provide
communication significant
speeds. improvements in error
detection capability.
● High-speed serial
communication can be ● FPGA resource
achieved while utilization analysis is
maintaining reliable minimal, limiting
asynchronous insights into hardware
transmission. optimization.
● The design
demonstrates efficient
data transfer between
FPGA modules.
3. Low-Latency UART ● The design achieves ● The research does not
Communication reduced incorporate advanced
Interface communication error detection
Implemented on latency, making it mechanisms such as
FPGA suitable for real-time CRC or parity
[2025] systems. verification.
● FPGA implementation ● The study focuses
shows stable operation primarily on
and reliable communication delay
communication. rather than power
optimization or
● Optimized FSM hardware efficiency.
control improves
system efficiency.
4. FPGA-Based UART ● FSM-based control ● Increasing the data
Protocol Design enables efficient width results in higher
Using Verilog HDL management of UART FPGA resource
[2025] communication states. usage.
● The architecture ● Error detection
allows transmission of techniques are limited,
larger data blocks, which may affect
improving reliability in noisy
communication environments.
flexibility.
● FPGA implementation
confirms correct
operation of the
transmitter and
receiver modules.
5. Design and Developed a high-speed ● The design focuses
Implementation of UART architecture mainly on power and
Verilog-Based optimized for speed optimization,
High-Speed reduced power with limited discussion
Low-Power UART consumption. of communication
[2024] reliability.
● Implemented using
Verilog HDL and Does not implement
FPGA development packet-based
tools. communication
protocols or advanced
● Demonstrated efficient data handling
clock management techniques.
and state machine
optimization. System validation is
limited to simulation
● Achieved reduced and small-scale
power usage and FPGA testing.
improved
transmission speed
compared to traditional
UART designs.
● Suitable for
low-power embedded
and IoT
communication
systems.
Research Gap
From the literature survey, several limitations are identified:
1. Many UART implementations focus only on basic transmission and reception mechanisms.
2. Advanced error detection and correction mechanisms are rarely integrated.
3. Few studies combine UART communication with real-time hardware interfaces such as
display modules, sensors, or control systems.
4. Optimization of power consumption, FPGA resource utilization, and system scalability
remains limited.
Therefore, the proposed project focuses on designing a UART communication system with
integrated error detection and FPGA-based hardware implementation, improving reliability and
practical usability in embedded systems.
Objectives
1. To design and implement a UART communication system on FPGA using
Verilog HDL for reliable serial data transmission and reception.
2. To enhance UART performance using FIFO buffering and adaptive baud
rate control in order to improve communication flexibility and reduce latency.
3. To implement a packet-based communication protocol that enables
structured command-based interaction between the PC and FPGA system
Methodology
The methodology describes the system design, implementation, and testing process used to develop the
FPGA-based UART communication system with adaptive baud rate, FIFO buffering, and packet-based
command protocol.
1. System Design and Architecture
The project follows a modular hardware design approach implemented on the Cyclone IV FPGA using
Verilog HDL. Each module performs a specific task in the communication pipeline.
The system architecture consists of the following blocks:
1. Adaptive Baud Rate Generator
2. UART Receiver
3. FIFO Buffer
4. Packet Parser
5. Command Decoder
6. UART Transmitter
Overall data flow:
PC → UART_RX → FIFO → Packet Parser → Command Decoder → UART_TX → PC
This modular design improves scalability, debugging, and system reliability.
2. Adaptive Baud Rate Implementation
To support multiple communication speeds, an adaptive
baud rate generator was implemented.
The module calculates the number of FPGA clock cycles
required to represent one UART bit:
CLKS_PER_BIT = FPGA Clock Frequency / Baud Rate
Two FPGA switches are used to select the baud rate
dynamically. The generated CLKS_PER_BIT value
controls the timing of both the UART receiver and
transmitter.
This approach allows flexible communication with different external devices without modifying the
hardware design.
3. UART Receiver Design
The UART receiver module converts incoming serial data into parallel 8-bit bytes.
A finite state machine (FSM) is implemented with four states:
1. IDLE – waits for the start bit
2. START – verifies the start bit and aligns sampling
3. DATA – receives 8 data bits sequentially
4. STOP – detects the stop bit and signals byte completion
The receiver samples the serial input at the middle of each bit period using the CLKS_PER_BIT
parameter to ensure accurate data reception.
Once all bits are received, the receiver asserts the data valid signal , indicating that a complete byte has
been successfully received.
4. FIFO Buffer Implementation
A FIFO (First-In-First-Out) buffer is implemented between the UART receiver and packet parser to
temporarily store incoming data.
The FIFO consists of:
● Memory array for storing received bytes
● Write pointer to track write position
● Read pointer to track read position
When the UART receiver receives a byte, the FIFO
stores it using the write pointer. The packet parser
reads bytes sequentially using the read pointer.
Advantages of using FIFO include:
● Prevents data loss during high-speed
communication
● Handles speed mismatch between modules
● Maintains correct byte order
This buffering mechanism improves the reliability and latency performance of the communication
system.
5. Packet Parser Implementation
To enable structured communication, a packet-based protocol was implemented.
The packet structure used in this project is:
START | COMMAND | DATA | STOP
AA CMD DATA 55
The packet parser reads bytes from the FIFO
and identifies packet boundaries using the
start and stop markers.
The packet parser uses a finite state machine
with the following states:
1. IDLE – waits for start byte
2. CMD – stores command byte
3. DATA – stores data byte
4. STOP – verifies packet termination
6. Command Decoder Implementation
The command decoder interprets the command extracted by the packet parser and executes the
corresponding system operation.
The decoder uses a case statement to identify the command type.
Example commands implemented:
Command Function
0x01 Display received data
0x02 Send response byte
Default Ignore unknown command
When a valid command is received, the decoder generates the appropriate output signals such as display data
or UART response data.
This module provides command-based control of the FPGA system.
7. UART Transmitter Design
The UART transmitter converts parallel data into a serial bit stream for transmission to the PC.
The transmitter also uses a finite state machine consisting of four states:
1. IDLE – waits for transmission request
2. START – sends start bit
3. DATA – sends 8 data bits sequentially
4. STOP – sends stop bit and completes transmission
Each bit is transmitted according to the timing defined by CLKS_PER_BIT.
The transmitter sends response bytes generated by the command decoder or test data triggered by push
buttons.
8. Hardware Integration
All modules are integrated in the top module implemented in Verilog.
Key connections include:
● Baud rate generator output connected to UART modules
● UART receiver output connected to FIFO buffer
● FIFO output connected to packet parser
● Packet parser connected to command decoder
● Command decoder connected to UART transmitter
The complete design is synthesized and implemented on the Cyclone IV EP4CE10 FPGA.
Block Diagram
Block Diagram Explanation
Explanation of the Block Diagram (UART Communication System)
1. PC to FPGA Communication
The PC sends serial data through the UART interface to the FPGA system. This data contains
command packets that follow the defined packet protocol.
2. UART Receiver
The UART receiver module in the FPGA converts the incoming serial data stream into parallel 8-bit
bytes based on the selected baud rate.
3. FIFO Buffer
The received bytes are temporarily stored in the FIFO buffer, which prevents data loss and manages
speed differences between the UART receiver and the packet parser.
4. Packet Parser
The packet parser reads data from the FIFO and identifies valid packets using the defined format:
Start Byte (0xAA) → Command Byte → Data Byte → Stop Byte (0x55).
It extracts the command and data fields from the packet.
5. Command Decoder
The command decoder interprets the received command and determines the appropriate action,
such as processing the data or generating a response.
6. Push Buttons (Optional Control)
Push buttons connected to the FPGA can be used to trigger specific commands or responses for
demonstration purposes.
7. UART Transmitter
The UART transmitter converts the processed data or response from the FPGA back into serial
format and sends it through the UART interface.
8. Baud Rate Generator
The baud rate generator provides the CLKS_PER_BIT timing for the UART modules. The baud
rate can be selected using switches to support different communication speeds.
9. Overall Operation
The system receives UART data, buffers it, interprets command packets, executes the
corresponding action, and optionally transmits a response back through the UART transmitter.
Hardware Components
1. FPGA Development Board (Cyclone IV)
The FPGA board is the main hardware platform used to implement the UART communication
system and error detection logic using Verilog HDL.
2. USB-to-UART Interface
This interface enables serial communication between the FPGA board and the computer through a
USB connection.
3. TM1638 Display Module
The TM1638 module is used to display the received data or system status using LEDs and
7-segment displays.
4. Personal Computer (PC)
The computer is used for writing Verilog code, running simulation tools, programming the FPGA,
and sending or receiving serial data.
5. Power Supply
Provides the required power for the FPGA development board and connected modules.
Software Components
1. Verilog Hardware Description Language (HDL)
Used to design and implement the UART transmitter, receiver, and error detection modules.
2. Quartus Prime
FPGA design software used for coding, synthesis, compilation, and programming the Cyclone IV
FPGA.
3. ModelSim
Simulation tool used to verify the functionality of the Verilog modules before hardware
implementation.
4. Serial Terminal Software (e.g., Tera Term / PuTTY)
Used to send and receive serial data between the PC and the FPGA through the UART interface.
5. EDA Tools
Used for waveform analysis, debugging, and verifying the correct operation of the UART
communication system during simulation.
Project Outcomes
1. Successful implementation of a UART communication system on FPGA
using Verilog HDL for reliable serial data transmission and reception.
2. Development of an adaptive baud rate mechanism allowing the system to
operate at multiple communication speeds using switch selection.
3. Implementation of a FIFO buffering mechanism to improve data handling
efficiency and prevent data loss during high-speed communication.
4. Integration of a packet-based command protocol enabling structured
communication and command decoding between the PC and FPGA.
5. Demonstration of a modular FPGA design architecture including UART
receiver, transmitter, FIFO buffer, packet parser, and command decoder
modules working together as a complete communication system.
REFERENCES
[1] T. Zhan et al., “Design and Implementation of UART Based on Verilog HDL,”
Highlights in Science, Engineering and Technology, 2023.
[2] A. Kumar et al., “Design and Implementation of Verilog Based High Speed
UART,” International Research Journal of Advanced Engineering and Hub, 2024.
[3] S. Patel et al., “Low-Latency UART Communication Interface Implemented
Using Verilog,” International Journal of Creative Research Thoughts, 2025.
[4] Y. Zhang et al., “Digital System Design of FPGA-Based UART Protocol Using
Verilog HDL,” 2025.
[5] B. Kumari, K. Jindal, and A. Bindal, “Design and Implementation of
Verilog-Based High-Speed Low-Power UART,” 2024.