Phụ lục – CÁC TẬP LỆNH CỦA CPU RISC – V 32I
A B D E I J L M O R S X
1 add beq div ecall inst jal la mret or rem sb xor
2 addi bge divu ebreak jalr lb mul ori remu sh xori
3 and bgeu lbu mulh ret sll
4 andi blt lh mulsu slli
5 auipc bltu lhu mulu slt
6 bne lui mv slti
7 li sltu
8 lw sltui
9 sra
10 srai
11 srl
12 srli
13 sub
14 sw
25
Chi tiết các lệnh được liệt kê như sau:
Instruction Decription Operation Example
Logic, Shift and Arithmetic instructions
and rd = rs1 & rs2 Performs the bitwise “and” add rd, rs1, rs2
operation on rs1 and rs2 and
stores the result on rd.
andi rd = rs1 & imm Performs the bitwise “and” andi rd, rs1, imm
operation on rs1 and imm and
stores the result on rd.
or rd = rs1 | rs2 Performs the bitwise “or” or rd, rs1, rs2
operation on rs1 and rs2 and
stores the result on rd.
ori rd = rs1 | imm Performs the bitwise “or” ori rd, rs1, imm
operation on rs1 and imm and
stores the result on rd.
xor rd = rs1 ˆ rs2 Performs the bitwise “xor” xor rd, rs1, rs2
operation on rs1 and rs2 and
stores the result on rd.
xori rd = rs1 ˆ imm Performs the bitwise “xor” xori rd, rs1, imm
operation on rs1 and imm and
stores the result on rd.
sll rd = rs1 << rs2 Performs a logical left shift on sll rd, rs1, rs2
the value at rs1 and stores the
result on rd. The amount of
left shifts is indicated by the
value on rs2.
slli rd = rs1 << imm[0:4] Performs a logical left shift on slli rd, rs1, imm
the value at rs1 and stores the
result on rd. The amount of
left shifts is indicated by the
immediate value imm.
srl rd = rs1 >> rs2 Performs a logical right shift srl rd, rs1, rs2
on the value at rs1 and stores
the result on rd. The amount of
right shifts is indicated by the
value on rs2.
srli rd = rs1 >> imm[0:4] Performs a logical right shift srli rd, rs1, imm
on the value at rs1 and stores
the result on rd. The amount of
left shifts is indicated by the
immediate value imm.
sra rd = rs1 >> rs2 Performs an arithmetic right sra rd, rs1, rs2
shift on the value at rs1 and
stores the result on rd. The
amount of right shifts is
indicated by the value on rs2.
srai rd = rs1 >> imm[0:4] Performs an arithmetic right srai rd, rs1, imm
shift on the value at rs1 and
stores the result on rd. The
amount of left shifts is
indicated by the immediate
value imm.
add rd = rs1 + rs2 Adds the values in rs1 and rs2 add rd, rs1, rs2
and stores the result on rd.
addi rd = rs1 ˆ imm Adds the value in rs1 to the addi rd, rs1, imm
immediate value imm and
stores the result on rd.
sub rd = rs1 - rs2 Subtracts the value in rs2 from sub rd, rs1, rs2
the value in rs1 and stores the
result on rd.
mul rd = (rs1 * rs2)[31:0] Multiplies the values in rs1 mul rd, rs1, rs2
and rs2 and the lower 32 bits
of the result in rd.
mulh rd = (rs1 * rs2)[63:32] Multiplies 2 signed operands mulh rd, rs1, rs2
rs1 and rs2 and stores the
upper 32 bits in rd.
mulsu rd = (rs1 * rs2)[63:32] Multiplies signed operand rs1 mulsu rd, rs1, rs2
and unsigned operand rs2 and
stores the upper 32 bits in rd.
mulhu rd = (rs1 * rs2)[63:32] Multiplies 2 unsigned mulhu rd, rs1, rs2
operands rs1 and rs2 and
stores the upper 32 bits in rd.
div{u} rd = rs1 / rs2 Divides the value in rs1 by the div{u} rd, rs1, rs2
value in rs2 and stores the
result on rd. The U suffix is
optional and must be used to
indicate that the values in rs1
and rs2 are unsigned.
rem{u} rd = rs1 % rs2 Calculates the remainder of rem{u} rd, rs1, rs2
the division of the value in rs1
by the value in rs2 and stores
the result on rd. The U suffix is
optional and must be used to
indicate that the values in rs1
and rs2 are unsigned.
Unconditional control – flow instructions
jal rd = PC+4; PC += imm Stores the return address jal lab
(PC+4) on the return register
(ra), then jumps to label lab
jalr rd = PC+4; PC = rs1 + imm Stores the return address jalr rd, rs1, imm
(PC+4) on register rd, then
jumps to the address
calculated by adding the
immediate value imm to the
value on register rs1.
ecall Transfer control to OS Generates a software ecall
interruption. Used to perform
system calls
mret Returns from an interrupt mret
handler.
ret Jumps to the address stored on ret
the return register (ra)
Control – flow and Conditional set instructions
beq if(rs1 == rs2) PC += imm Jumps to label lab if the value beq rs1, rs2, lab
in rs1 is equal to the value in
rs2.
bne if(rs1 != rs2) PC += imm Jumps to label lab if the value bne rs1, rs2, lab
in rs1 is different from the
value in rs2.
beqz if(rs1 == 0) PC += imm Jumps to label lab if the value beqz rs1, lab
in rs1 is equal to zero.
bnez if(rs1 != 0) PC += imm Jumps to label lab if the value bnez rs1, lab
in rs1 is not equal to zero.
blt if(rs1 < rs2) PC += imm Jumps to label lab if the signed blt rs1, rs2, lab
value in rs1 is smaller than the
signed value in rs2.
bltu if(rs1 < rs2) PC += imm Jumps to label lab if the bltu rs1, rs2, lab
unsigned value in rs1 is
smaller than the unsigned
value in rs2.
bge if(rs1 >= rs2) PC += imm Jumps to label lab if the signed bge rs1, rs2, lab
value in rs1 is greater or equal
to the signed value in rs2.
bgeu if(rs1 >= rs2) PC += imm Jumps to label lab if the bgeu rs1, rs2, lab
unsigned value in rs1 is
greater or equal to the
unsigned value in rs2.
slt rd = (rs1 < rs2)?1:0 Sets rd with 1 if the signed slt rd, rs1, rs2
value in rs1 is less than the
signed value in rs2, otherwise,
sets it with 0.
slti rd = (rs1 < imm)?1:0 Sets rd with 1 if the signed slti rd, rs1, imm
value in rs1 is less than the
sign-extended immediate
value imm, otherwise, sets it
with 0.
sltu rd = (rs1 < rs2)?1:0 Sets rd with 1 if the unsigned sltu rd, rs1, rs2
value in rs1 is less than the
unsigned value in rs2,
otherwise, sets it with 0.
sltui rd = (rs1 < imm)?1:0 Sets rd with 1 if the unsigned sltui rd, rs1, imm
value in rs1 is less than the
unsigned immediate value
imm, otherwise, sets it with 0.
Data movement instructions
mv rd = rs + 0 Copies the value from register mv rd, rs
rs into register rd.
li rd = imm Loads the immediate value li rd, imm
imm into register rd.
la rd = address(rot) Loads the label address rot la rd, rot
into register rd.
lw rd = M[rs1+imm][0:31] Loads a 32-bit signed or lw rd, imm(rs1)
unsigned word from memory
into register rd. The memory
address is calculated by adding
the immediate value imm to
the value in rs1.
lh rd = M[rs1+imm][0:15] Loads a 16-bit signed lh rd, imm(rs1)
halfword from memory into
register rd. The memory
address is calculated by adding
the immediate value imm to
the value in rs1.
lhu rd = M[rs1+imm][0:15] Loads a 16-bit unsigned lhu rd, imm(rs1)
halfword from memory into
register rd. The memory
address is calculated by adding
the immediate value imm to
the value in rs1.
lb rd = M[rs1+imm][0:7] Loads a 8-bit signed byte from lb rd, imm(rs1)
memory into register rd. The
memory address is calculated
by adding the immediate value
imm to the value in rs1.
lbu rd = M[rs1+imm][0:7] Loads a 8-bit unsigned byte lbu rd, imm(rs1)
from memory into register rd.
The memory address is
calculated by adding the
immediate value imm to the
value in rs1.
sw M[rs1+imm][0:31] = rs2[0:31] Stores the 32-bit value at sw rs1, imm(rs2)
register rs1 into memory. The
memory address is calculated
by adding the immediate value
imm to the value in rs2.
sh M[rs1+imm][0:15] = rs2[0:15] Stores the 16 least significant sh rs1, imm(rs2)
bits from register rs1 into
memory. The memory address
is calculated by adding the
immediate value imm to the
value in rs2.
sb M[rs1+imm][0:7] = rs2[0:7] Stores the 8 least significant sb rs1, imm(rs2)
bits from register rs1 into
memory. The memory address
is calculated by adding the
immediate value imm to the
value in rs2.