Exception and Interrupt
Handling
Exception Handlers
• Exception is a condition that needs to halt the normal sequential execution of
instructions
• Responsible for handling errors, interrupts and other events generated by
external system
• Examples
• ARM core is reset
• when an instruction fetch or memory access fails
• when an undefined instruction is encountered
• when a software interrupt instruction is execute
• when an external interrupt has been raised
➢ Most exceptions have an associated Software Exception Handler
➢ Software Exception Handler:A software routine that executes when an exception occurs.
➢ Example:
➢ A Data Abort exception will have a Data Abort handler.
➢ The handler first determines the cause of the exception and then services the exception.
➢ Servicing takes place either within the handler or by branching to a specific service
routine.
➢ The Reset exception is a special case; it is used to initialize an embedded system.
ARM Processor Exceptions and Modes
➢ Each exception causes the core to enter a specific mode
➢ Any ARM processor modes can be entered manually by changing CPSR
➢ When an exception causes a mode change, the core automatically
✓ saves the ‘cpsr’ to the ‘spsr’ of the exception mode
✓ saves the ‘pc’ to the ‘lr’ of the exception mode
✓ sets the ‘cpsr’ to the exception mode
✓ Sets ‘pc’ to the address of the exception handler
➢ User and system modes cannot be entered by using an exception
➢ CPSR must be modified to enter these modes
Vector table
A table of addresses that the ARM core branches to when an exception is raised. These addresses commonly
contain branch instructions of one of the following forms:
B <address>
This branch instruction provides a branch relative from the pc.
LDR pc, [pc, #offset]
This load register instruction loads the handler address from memory to the pc. The address is an absolute 32-bit
value stored close to the vector table
LDR pc, [pc, #-0xff0]
This load register instruction loads a specific interrupt service routine address from address0xfffff030to the pc.
This specific instruction is only used when a vector interrupt controller is present (VIC PL190)
MOV pc, #immediate
This move instruction copies an immediate value into the pc. It lets you span the full address space but at limited
alignment
EXCEPTION PRIORITIES
Exceptions can occur simultaneously, so the processor has to Certain exceptions also disable interrupts by
setting the I an F bits in CPSR Register
adopt a priority mechanism.
•Reset exception is the highest priority and occurs when
power is applied to the processor.
•When a Data Abort occurs, it takes precedence over all
other exceptions apart from a Reset exception.
•The lowest priority level is shared by two exceptions, the
Software Interrupt and Undefined Instruction exceptions.
Exception Priorities
➢ The Reset exception is the highest priority exception and is always taken whenever it is signaled.
➢ The reset handler initializes the system, including setting up memory and caches.
➢ External interrupt sources should be initialized before enabling IRQ or FIQ interrupts to avoid the possibility of
spurious interrupts occurring before the appropriate handler has been set up.
➢ The reset handler must also set up the stack pointers for all processor modes
➢ During the first few instructions of the handler, it is assumed that no exceptions/interrupts will occur.
➢ The code should be designed to avoid SWIs, undefined instructions, and memory accesses that may abort
Data Abort exceptions occur when,
➢ the memory controller or MMU indicates that an invalid memory address has been accessed
➢ the current code attempts to read or write to memory without the correct access permissions.
➢ An FIQ exception can be raised within a Data Abort handler since FIQ exceptions are not disabled.
➢ When the FIQ is completely serviced, control is returned back to the Data Abort handler
➢ A Fast Interrupt Request (FIQ) exception occurs when an external
peripheral sets the FIQ pin to nFIQ.
➢ An FIQ exception is the first highest priority interrupt.
➢ The core disables both IRQ and FIQ exceptions on entry into the FIQ handler.
➢ Thus, no external source can interrupt the processor unless the IRQ and/or FIQ
exceptions are re enabled by software.
➢ An Interrupt Request (IRQ) exception occurs when an external peripheral sets the
IRQ pin to nIRQ.
➢ An IRQ exception is the second highest priority interrupt.
➢ The IRQ handler will be entered if neither an FIQ exception nor data Abort
exception occurs.
➢ On entry to the IRQ handler, the IRQ exceptions are disabled and should remain
disabled until the current interrupt source has been cleared
➢ A Pre fetch Abort exception occurs when an attempt to fetch an instruction results
in a memory fault (non existing memory regions).
➢ This exception is raised when the instruction is in the execute stage of the pipeline
and if none of the higher exceptions have been raised.
➢ On entry to the handler, IRQ exceptions will be disabled, but the FIQ exceptions will
remain unchanged.
➢ If FIQ is enabled and an FIQ exception occurs, it can be taken while servicing the Pre
fetch Abort
A Software Interrupt (SWI) exception occurs when the SWI instruction is executed and
none of the other higher-priority exceptions have been flagged.
➢ On entry to the handler, the cpsr will be set to supervisor mode.
➢ For nested SWI calls, link register r14 and spsr must be stored away before branching to nested
SWI
An Undefined Instruction exception occurs when an instruction not in the ARM
or Thumb instruction set reaches the execute stage of the pipeline and none of the
other exceptions have been flagged.
➢ The ARM processor “asks” the coprocessors if they can handle this as a coprocessor
instruction.
➢ If none of the coprocessors claims the instruction, an Undefined Instruction exception
is raised.
➢ Both the SWI instruction and Undefined Instruction have the same level of priority, since
they cannot occur at the same time
Link Register Offsets
When an exception occurs, the link register is set to a specific address based on the current pc
Different methods of returning from an IRQ or FIQ exception handler:
Ex1:
This example shows that a typical method of returning from an IRQ and FIQ handler is to use a SUBS instruction:
handler <handler code>...SUBS pc, r14, #4 ; pc=r14-4
Because there is an S at the end of the SUB instruction and the pc is the destination register, the cpsr is automatically
restored from the spsr register
Ex2: This example shows another method that subtracts the offset from the link register r14 at the beginning of
the handler.
handler SUB r14, r14, #4 ; r14-=4...<handler code>...
MOVS pc, r14 ; return
After servicing is complete, return to normal execution occurs by moving the link register r14 into the pc and
restoring cpsr from the spsr
Ex 3: The final example uses the interrupt stack to store the link register.
This method first subtracts an offset from the link register and then stores it onto the interrupt stack.
handler SUB r14, r14, #4 ; r14-=4
STMFD r13!,{r0-r3, r14} ; store context
...<handler code>...
LDMFD r13!,{r0-r3, pc}ˆ ; return
To return to normal execution, the LDM instruction is used to load the pc. The ˆ symbol in the
instruction forces the cpsr to be restored from the spsr
Interrupts
IRQ and FIQ Exceptions
An IRQ or FIQ exception causes the processor hardware to go through a standard procedure (Interrupts
must not be masked):
1. The processor changes to a specific interrupt request mode, which reflects the interrupt being raised
2. The previous mode’s cpsr is saved into the spsr of the new interrupt request mode
3. The pc is saved in the lr of the new interrupt request mode
4. Interrupt/s are disabled—either IRQ or both IRQ and FIQ exceptions are disabled in the cpsr. This
immediately stops another interrupt request of the same type being raised
5. The processor branches to a specific entry in the vector table.
Note: The procedure varies slightly depending upon the type of interrupt being raised
What happens when an IRQ exception is raised when processor is in user mode??
State 1
➢ In this example both the IRQ and FIQ exception bits in the cpsr are enabled.
➢ When an IRQ occurs the processor moves into state 2
State 2
➢ This transition sets the IRQ bit to one, disabling any further IRQ exceptions.
➢ The FIQ remains enabled as FIQ has a higher priority. The cpsr processor mode changes
to IRQ mode.
➢ The user mode cpsr is copied into spsr_irq
➢ Register r14_irq is assigned the value of the pc when the interrupt was raised.
➢ The pc is then set to the IRQ entry +0x18 in the vector table.
State 3
➢ The software handler takes over and calls the appropriate interrupt service routine to
service the source of the interrupt.
➢ Upon completion, processor mode reverts back to the original user mode code in state 1.
What happens when an FIQ exception is raised when processor is in user mode??
State 1
➢ In this example both the IRQ and FIQ exception bits in the cpsr are enabled.
➢ When an IRQ occurs the processor moves into state 2
State 2
➢ This transition sets both IRQ and FIQ bits to one, disabling any further IRQ/FIQ
exceptions.
➢ The cpsr processor mode changes to FIQ mode.
➢ The user mode cpsr is copied into spsr_fiq
➢ Register r14_fiq is assigned the value of the pc when the interrupt was raised.
➢ The pc is then set to the IRQ entry +0x1C in the vector table.
State 3
➢ The software handler takes over and calls the appropriate interrupt service routine to
service the source of the interrupt.
➢ Upon completion, processor mode reverts back to the original user mode code in state 1.
Enabling FIQ and IRQ Exceptions
FIQ and IRQ can be manually enabled by modifying the cpsr when the processor is in a privileged mode.
Table shows how IRQ and FIQ interrupts are enabled.
1. The first instruction MRS copies the contents of
the cpsr into register r1.
2. The second instruction clears the IRQ or FIQ mask
bit.
3. The third instruction then copies the updated
contents in register r1 back into the cpsr
Thus enabling the interrupt request.
Disabling FIQ and IRQ Exceptions
FIQ and IRQ can be manually disabled by modifying the cpsr when the processor is in a privileged mode.
Table shows how IRQ and FIQ interrupts are disabled/masked
1. The first instruction MRS copies the contents of the cpsr into
register r1.
2. The second instruction sets the IRQ or FIQ mask bit. Here
logical OR operation is used to perform this task
3. The third instruction then copies the updated contents in
register r1 back into the cpsr
Thus disabling/masking any new interrupt request.
NOTE:
1. The interrupt request is either enabled/disabled only once the MSR instruction has
completed the execution stage of the pipeline.
2. Interrupts can still be raised or masked prior to the MSR completing this stage
This IRQ handler example assumes that the IRQ stack has been correctly set up by the
initialization code.
In the preceding code there are two ISRs: timer_isr and button_isr. They are mapped to specific
bits in the IRQStatus register, 0x0080 and 0x0001, respectively.