CSPE3010 Embedded Systems | Module I & II Notes

CSPE3010
EMBEDDED SYSTEMS
(3-0-0)

Complete Notes
Module I & Module II

Covers All PYQs | Predicted Questions | Exam-Ready

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 CSPE3010 Embedded Systems | Module I & II Notes

MODULE I: Embedded System Fundamentals & Hardware Basics

1. Characteristics and Classification of Embedded Systems

1.1 What is an Embedded System?
An embedded system is a dedicated computer system designed to perform specific, predefined
functions as part of a larger system. Unlike general-purpose computers, embedded systems are built
around a microprocessor or microcontroller and are optimized for a particular task.

Definition
An embedded system is a combination of hardware and software designed to perform a specific
function
within a larger mechanical or electrical system.
Examples: Washing machine controller, ATM machine, digital camera, anti-lock braking system
(ABS).

1.2 Characteristics of Embedded Systems

• Single-functioned: Designed to perform one or few specific tasks (e.g., a pacemaker monitors
heart rate only)
• Tightly constrained: Must meet strict limitations on cost, size, power consumption, and
performance
• Reactive and real-time: Must respond to events/inputs within strict time limits (hard or soft real-
time)
• Microprocessor/Microcontroller based: Built around dedicated processors
• Memory constraints: Limited RAM and ROM; often uses Flash memory for firmware storage
• Power constraints: Battery-operated systems must minimize power consumption
• Reliability and dependability: Must operate continuously and reliably; often mission-critical
• Connected: Modern systems interface with external sensors, actuators, and communication
networks
• Not user programmable: End users generally cannot reprogram the device

1.3 Classification of Embedded Systems

Embedded systems are classified based on performance, functional requirements, and complexity:

Classification Description & Examples

Small Scale Simple, 8/16-bit processors, minimal memory.
Examples: calculators, digital watches
Medium Scale More complex, 16/32-bit processors, RTOS
may be used. Examples: printers, routers

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Classification Description & Examples

Large Scale Complex SoC or DSP, multitasking. Examples:
smartphones, flight control systems
Real-Time (Hard) Strict timing deadlines; missing them causes
catastrophic failure. Example: airbag controller
Real-Time (Soft) Deadlines important but not catastrophic if
missed. Example: video streaming
Mobile Embedded Battery-powered, wireless communication.
Examples: smartwatch, GPS
Networked Embedded Connected via LAN/internet. Examples: IoT
sensors, smart meters
Standalone Embedded Operates independently without connection.
Example: microwave oven

1.4 Difference: Embedded vs Non-Embedded Systems

Embedded System Non-Embedded (General Purpose) System
Designed for specific function Designed for multiple general functions
Optimized hardware for task Generic hardware components
Runs firmware (not OS typically) Runs full operating system (Windows, Linux)
Low power consumption Higher power consumption
Limited memory and resources Expandable memory and resources
Real-time constraints apply No strict real-time requirements
Example: ABS brake controller Example: Personal computer

2. Embedded Hardware Components

2.1 Processor / Microcontroller
The processor is the brain of an embedded system. It executes instructions and controls the operation
of the entire system.

• Microprocessor: Only the CPU core; requires external RAM, ROM, and peripherals
• Microcontroller (MCU): Integrates CPU, RAM, ROM, I/O, timers, ADC in a single chip
• DSP (Digital Signal Processor): Optimized for signal processing algorithms
• FPGA: Reconfigurable hardware; used for parallel processing tasks

Types of Processors in Embedded Systems

1. General Purpose Processor (GPP): Versatile but less optimized. Example: Intel Atom

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2. Application Specific Standard Parts (ASSP): Tailored for specific domains. Example: Ethernet
controller
3. Application Specific Integrated Circuit (ASIC): Custom-designed for one application
4. Programmable Logic Device (PLD/FPGA): Reprogrammable hardware logic

2.2 Memory Types in Embedded Systems

Memory stores program code, data, and intermediate results:

Memory Type Volatile? Use in Embedded Systems

ROM (Read Only Memory) No Store firmware permanently
EEPROM No Store configuration data; byte
erasable
Flash Memory No Store firmware; block erasable
SRAM (Static RAM) Yes Fastest RAM; used for stack
and variables
DRAM (Dynamic RAM) Yes Larger data storage; needs
refresh cycles
SDRAM Yes High-speed data RAM in
complex systems
Cache Memory Yes High-speed buffer between
CPU and RAM

2.3 Big Endian vs Little Endian Memory Organization

Endianness defines how multi-byte data is stored in memory:

Big Endian Little Endian

MSB (Most Significant Byte) stored at lowest LSB (Least Significant Byte) stored at lowest
address address
Used in Motorola 68K, SPARC, ARM Used in Intel x86, ARM (default mode)
(configurable)
Example: 0x12345678 stored as 12 34 56 78 Example: 0x12345678 stored as 78 56 34 12
Network byte order uses big endian Most embedded processors use little endian

2.4 I/O Devices in Embedded Systems

• Input Devices: Keypad, touch screen, sensors (temperature, pressure, motion), ADC
• Output Devices: LCD display, LEDs, DAC, actuators, motors
• Serial Ports: UART, SPI, I2C for communication
• Parallel Ports: Data buses for high-speed data transfer

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• Timer/Counter: Generate precise time delays, measure pulse widths, generate PWM

2.5 ADC and DAC in Embedded Systems

ADC (Analog-to-Digital Converter): Converts analog signals from real-world sensors into digital values
readable by the processor.
• Key parameters: Resolution (bits), Sampling rate (Hz), Reference voltage
• Example: A 12-bit ADC with Vref=3.3V gives resolution of 3.3/4096 = 0.8 mV per step
• Used for: Reading temperature sensors, microphones, pressure sensors

DAC (Digital-to-Analog Converter): Converts digital values from the processor into analog signals.
• Used for: Audio output, controlling analog actuators, waveform generation
• Key parameters: Resolution, settling time, output range

2.6 Timers in Embedded Systems

Timers are hardware modules that count clock pulses and generate interrupts or output signals:
• System Timer: Generates periodic interrupts for OS tick or task scheduling
• Watchdog Timer (WDT): Resets the system if the software fails to refresh it within a set period
• PWM Timer: Generates Pulse Width Modulated signals for motor control, LED dimming
• Capture/Compare Timer: Measures external signal timing or generates precise output signals

Watchdog Timer (WDT)

Purpose: Recover from software hangs/crashes automatically
Working: Software must periodically 'kick' or 'feed' the WDT register
If not kicked in time: WDT expires and generates a system reset
Types: Window WDT (must be kicked in a specific time window); Simple WDT (kick before
timeout)

3. Embedded Software Concepts

3.1 Firmware
Firmware is low-level software stored in non-volatile memory (Flash/ROM) that controls the hardware
directly. It acts as the bridge between hardware and higher-level software.

Firmware Application Software

Stored in ROM/Flash on the device Stored in OS file system or external memory
Controls hardware at a low level Uses OS APIs and drivers
Updated via special flashing process Updated through standard package managers
Runs at boot or exclusively Runs on top of OS
Example: BIOS, router firmware Example: Web browser, calculator app

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Firmware Development Steps:

1. Define hardware platform and requirements
2. Set up toolchain (compiler, linker, debugger)
3. Write initialization code (startup files, vector tables)
4. Implement peripheral drivers
5. Develop application logic
6. Test and debug using JTAG/SWD
7. Flash the binary to device memory

3.2 Device Drivers

A device driver is a software module that provides an abstraction layer between hardware and
application software. It allows applications to use hardware without knowing hardware details.

• Physical Drivers: Directly interact with hardware registers

• Virtual Drivers: Provide abstraction; interact with physical drivers

Advantages of Device Drivers:

• Hardware independence: Application code doesn't change when hardware changes
• Code reuse: Same driver can be used by multiple applications
• Easier debugging and maintenance
• Security: Controlled access to hardware

3.3 Bootloader
A bootloader is the first program that executes when a microcontroller or embedded processor powers
up. Its primary role is to initialize hardware and load the main application firmware into memory.

Role of Bootloader:
• Initialize the CPU, clock, and memory systems
• Verify integrity of application firmware (CRC check)
• Load application firmware from Flash to RAM (if needed)
• Jump to the application entry point (main function)
• Enable field firmware updates (OTA or via UART/USB)

Bootloader Stages
Stage 1 (First Stage): ROM bootloader baked into chip by manufacturer
Stage 2 (Second Stage): Loaded by Stage 1; handles more complex initialization
Application: Main firmware loaded by bootloader
Examples: U-Boot (Linux embedded), ARM Cortex-M startup code

3.4 Toolchain Overview

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A toolchain is the complete set of programming tools used to develop embedded software:

Tool Function
Compiler Converts C/C++ source code to
assembly/object files
Assembler Converts assembly code to machine code
(object files)
Linker Combines object files into a single executable;
assigns memory addresses
Loader Transfers executable to target device memory
Debugger Allows step-by-step execution, breakpoints,
variable inspection
IDE Integrates all tools into one interface (Eclipse,
Keil, IAR)

3.5 Cross-Compilation vs Native Compilation

Cross-Compilation Native Compilation
Code compiled on Host machine for Target Code compiled on the same machine it runs on
machine
Host: PC (x86); Target: ARM microcontroller Host and target are the same architecture
Required when target lacks OS/resources to Used in PC/server software development
compile
Example: arm-none-eabi-gcc on Windows for Example: gcc on Linux for Linux programs
STM32
Faster compilation using powerful host Compilation is slower on resource-limited
resources targets

3.6 Linker and Loader

Linker: Combines multiple object (.o) files into a single executable file. It:
• Resolves symbolic references between modules
• Assigns final memory addresses based on linker script
• Produces map file showing memory usage

Loader: Transfers the final executable image to the target device's memory:
• Used during programming/flashing process
• In bare-metal systems, a programmer (J-Link, ST-Link) acts as loader
• In Linux-based embedded systems, OS loader (execve) handles loading

3.7 IDE (Integrated Development Environment)

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An IDE integrates all development tools into one application:

• Source code editor with syntax highlighting
• Build system integration (make, CMake)
• Debugger interface (GDB, JTAG)
• Flash programming support

Common Embedded IDEs: Keil MDK, IAR Embedded Workbench, Eclipse with GNU ARM plugin,
STM32CubeIDE, PlatformIO

4. ARM Architecture Basics

4.1 RISC Principles Followed by ARM
ARM (Advanced RISC Machine) follows RISC (Reduced Instruction Set Computer) design philosophy:

• Fixed-length instructions: All ARM instructions are 32 bits wide (Thumb: 16 bits)
• Load-Store architecture: Only load/store instructions access memory; operations on registers
only
• Large register file: 16 general-purpose registers (R0-R15)
• Single-cycle execution: Most instructions execute in one clock cycle
• Simple addressing modes: Fewer addressing modes for simpler decode logic
• Hardwired control: No microcode; control implemented directly in hardware
• Pipeline: 3-stage pipeline (Fetch, Decode, Execute) in ARM7; 5-stage in ARM9

4.2 RISC vs CISC Architecture

RISC (ARM) CISC (x86)
Few, simple instructions Many complex instructions
Fixed instruction length (32-bit) Variable instruction length
Load-Store architecture Instructions can access memory directly
Large register file Fewer general-purpose registers
Simple, fast decode Complex decode logic
Multiple registers Accumulator-based operations
Examples: ARM, MIPS, SPARC Examples: Intel x86, AMD64

4.3 ARM Register Model

ARM has 16 visible registers in any mode:
• R0-R12: General-purpose registers for data operations
• R13 (SP - Stack Pointer): Points to top of current stack
• R14 (LR - Link Register): Stores return address during function calls
• R15 (PC - Program Counter): Points to current instruction being fetched

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Status Registers:
• CPSR (Current Program Status Register): Stores condition flags (N, Z, C, V), processor mode,
interrupt disable bits, thumb mode bit
• SPSR (Saved Program Status Register): Saves CPSR when an exception occurs; allows
restoration on return

CPSR Flags
N (Negative): Set if result is negative
Z (Zero): Set if result is zero
C (Carry): Set if unsigned overflow
V (Overflow): Set if signed overflow
I bit: Disables IRQ interrupts when set
F bit: Disables FIQ interrupts when set
T bit: Thumb mode (1=Thumb, 0=ARM)

4.4 ARM Processor Modes

ARM supports 7 operating modes:
Mode Description
User Normal program execution; least privileged
FIQ (Fast IRQ) Fast interrupt handling; has extra banked
registers
IRQ Normal interrupt handling
Supervisor OS kernel mode; entered on reset or SVC call
Abort Memory access violation
Undefined Undefined instruction encountered
System Privileged mode sharing User registers

4.5 ARM Instruction Groups

• Data Processing Instructions: ADD, SUB, MUL, AND, ORR, EOR, MOV, CMP
• Load-Store Instructions: LDR (load register), STR (store register), LDRB/STRB (byte),
LDRH/STRH (halfword)
• Branch Instructions: B (branch), BL (branch with link - for function calls), BX (branch and
exchange - switch ARM/Thumb)
• Multiply Instructions: MUL, MLA (multiply-accumulate)
• PSR Transfer: MRS (move PSR to register), MSR (move register to PSR)
• Coprocessor Instructions: CDP, LDC, STC - for FPU and memory management
• Swap Instructions: SWP, SWPB - atomic read-modify-write

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4.6 Load-Store Instructions (ARM)

LDR and STR: Load and store 32-bit word

LDR/STR Examples
LDR R0, [R1] ; Load word at address R1 into R0
STR R0, [R1] ; Store R0 to address R1
LDRB R0, [R1] ; Load byte (zero extended) from address R1
STRB R0, [R1] ; Store lowest byte of R0 to address R1
LDR R0, [R1, #4] ; Load from address R1+4 (pre-indexed)
LDR R0, [R1], #4 ; Load from R1, then R1 = R1+4 (post-indexed)

4.7 ARM Branching Instructions

• B label: Unconditional branch to label (PC-relative offset, +/- 32MB range)
• BL label: Branch with link; saves PC+4 to LR, then branches (used for function calls)
• BX Rn: Branch and exchange; jumps to address in Rn; if bit0=1, switches to Thumb mode
• BEQ, BNE, BGT, BLT: Conditional branches based on CPSR flags

4.8 Thumb Mode (ARM7TDMI)

Thumb mode is a secondary instruction set where instructions are 16-bit instead of 32-bit:
ARM Mode Thumb Mode
32-bit instructions 16-bit instructions
Better performance Better code density (smaller code size)
Access all 16 registers Access only R0-R7 directly
All instructions conditional Only branch instructions conditional
Used where performance critical Used where memory is limited

4.9 ARM Pipeline Architecture

ARM7 uses a 3-stage pipeline:
• Stage 1 - Fetch: Instruction fetched from memory and stored in instruction pipeline
• Stage 2 - Decode: Instruction decoded; registers read from register file
• Stage 3 - Execute: ALU operation performed; registers updated; memory access if needed

While Stage 3 executes instruction N, Stage 2 decodes instruction N+1, and Stage 1 fetches instruction
N+2. This gives effective throughput of one instruction per cycle.

4.10 ARM Architecture Block Diagram - Key Units

• ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations
• Barrel Shifter: Hardware shift unit integrated with ALU for shift operations in one cycle
• Instruction Decoder: Decodes the instruction and generates control signals

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• Register Bank: 16 general-purpose registers + status registers

• Address Register/Incrementer: Computes next instruction address
• Data/Address Bus Interface: Connects to memory system
• Multiplier: Hardware multiply unit

5. Embedded System Design Flow

The complete process of designing an embedded system from specification to deployment:

8. Requirements Specification: Define functionality, performance, power, cost constraints

9. Hardware-Software Partitioning: Decide which functions are in hardware vs software
10. Hardware Design: Select processor, memory, peripherals; design PCB
11. Software Design: Design firmware architecture, drivers, RTOS integration
12. Cross-compilation: Build firmware on host computer for target processor
13. Integration & Testing: Combine hardware and software; test on actual hardware
14. Debugging: Use JTAG/SWD debugger, logic analyzer, oscilloscope
15. Optimization: Optimize for speed, memory, and power
16. Deployment: Flash firmware to production devices

5.1 Host vs Target System

Host Computer System Target System
Development machine (PC/workstation) Final embedded hardware product
Runs full OS (Linux/Windows) Runs firmware or RTOS
Has cross-compiler toolchain Has application-specific hardware
Connected to target via JTAG/USB Connected to real-world sensors/actuators
More powerful resources (RAM, storage) Resource-constrained (small RAM/Flash)
Example: Engineer's laptop Example: STM32 microcontroller board

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MODULE II: Interfacing & Communication Protocols

6. Digital I/O Concepts

6.1 GPIO (General Purpose I/O)
GPIO pins can be configured as input or output under software control:
• Output mode: Processor drives the pin high (Vcc) or low (GND) to control LEDs, relays,
transistors
• Input mode: Processor reads pin state; used with buttons, switches, sensors
• Pull-up/Pull-down resistors: Ensure defined logic level when no device is connected
• Open-drain output: Can only pull low; requires external pull-up (used in I2C)

6.2 Serial vs Parallel Communication

Serial Communication Parallel Communication
Data sent one bit at a time on a single wire Multiple bits sent simultaneously on multiple
wires
Fewer wires; lower cost More wires; higher cost
Suitable for long distances Limited to short distances due to timing skew
Examples: UART, SPI, I2C, CAN Example: 8-bit/16-bit data bus to memory
Lower data rate (generally) Higher data rate (generally)

7. Timers and Interrupts

7.1 Timer Operation
A timer is a counter that counts clock pulses. It can be configured to:
• Generate periodic interrupts (e.g., every 1 ms for RTOS tick)
• Measure elapsed time (input capture)
• Generate PWM signals (output compare)
• Count external events (event counter mode)

Timer Registers
TCR (Timer Control Register): Configure timer mode, clock source, prescaler
TDR (Timer Data Register): Current counter value
TPSR (Timer Prescale Register): Divides clock for lower frequency counting
TOR (Timer Output Register): Compare value for output generation

7.2 Interrupts in Embedded Systems

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An interrupt is a signal that causes the processor to stop its current activity and execute a special
routine called an Interrupt Service Routine (ISR).

Types of Interrupts:
• Hardware Interrupt (IRQ): Generated by external hardware (GPIO, timer, UART)
• Software Interrupt (SWI): Generated by software instruction; used for OS system calls
• NMI (Non-Maskable Interrupt): Cannot be disabled; used for critical events (power failure)
• FIQ (Fast IRQ): Higher priority interrupt with faster response in ARM

ISR Execution Flow:

17. Interrupt signal asserted by peripheral
18. Processor completes current instruction
19. CPSR saved to SPSR; PC saved to LR
20. CPU jumps to interrupt vector table address
21. ISR executes
22. ISR ends with MOVS PC, LR (returns, restoring CPSR)

7.3 Polling vs Interrupt-Driven I/O

Polling (Busy-Waiting) Interrupt-Driven I/O
CPU continuously checks status register Hardware signals CPU when ready
Wastes CPU cycles CPU free to do other work
Simple to implement More complex (ISR, vector table setup)
Predictable timing Non-deterministic response time
Good for: High-speed, predictable events Good for: Rare, unpredictable events
Example: Checking UART TX buffer Example: Button press handling

8. PWM (Pulse Width Modulation)

PWM is a technique where a digital output signal's duty cycle is varied to control power delivered to an
analog load.

Period: Time for one complete on-off cycle: T = 1/frequency

Duty Cycle: Percentage of time signal is HIGH: Duty = (TON / T) * 100%
50% Duty Cycle: Signal is HIGH half the time and LOW half the time

Applications of PWM:
• Motor speed control (varying average voltage)
• LED brightness control (dimming)
• Audio signal generation
• Servo motor position control

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PWM Generation Using Timers:

• Configure timer period register with desired frequency
• Configure compare register with duty cycle value
• When counter < compare value: output HIGH
• When counter >= compare value: output LOW
• Timer auto-reloads and cycle repeats

9. ADC and DAC Interfacing

9.1 ADC Interfacing
Steps to interface an ADC with a microcontroller:
23. Configure ADC clock and reference voltage
24. Select input channel (MUX selection)
25. Start conversion (set start bit in ADC control register)
26. Wait for conversion complete (poll status bit or use interrupt)
27. Read digital result from ADC data register
28. Apply formula: Voltage = (ADC_Value / (2^n - 1)) x Vref

ADC Key Parameters

Resolution: Number of bits (8, 10, 12, 16-bit). Higher = finer measurement
Sampling Rate: How many samples per second (kHz to MHz)
Reference Voltage (Vref): Maximum measurable voltage
SNR (Signal-to-Noise Ratio): Measure of ADC quality
Successive Approximation (SAR): Most common ADC type in MCUs

9.2 DAC Interfacing

Steps to interface a DAC with a microcontroller:
29. Configure DAC reference voltage and output channel
30. Write digital value to DAC data register
31. DAC converts digital value to analog voltage automatically
32. Formula: Vout = (Digital_Value / (2^n - 1)) x Vref
33. Add output buffer or amplifier if higher current needed

10. Communication Protocols

10.1 UART (Universal Asynchronous Receiver Transmitter)
UART is an asynchronous serial communication protocol using two wires (TX and RX):
• No shared clock; both devices configured with same baud rate
• Data frame: Start bit + 5-9 data bits + optional parity + 1-2 stop bits
• Common baud rates: 9600, 19200, 38400, 115200 bps

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• Full-duplex: Can transmit and receive simultaneously

• RS-232: Electrical standard for UART; uses voltage levels (-12V to +12V)

UART Feature Details

Wires needed 2 (TX, RX) + GND
Clock No shared clock (asynchronous)
Masters 2 (peer-to-peer)
Speed Up to ~115200 bps typically
Use case Debug console, GPS, GSM modules

10.2 SPI (Serial Peripheral Interface)

SPI is a synchronous, full-duplex serial communication protocol:
• 4-wire: SCLK (clock), MOSI (master out slave in), MISO (master in slave out), CS/SS (chip
select)
• Master provides clock; one master, multiple slaves
• Each slave has separate CS line; master pulls CS low to select slave
• No addressing; slave selected by hardware CS line
• Very high speed: up to 100 MHz

SPI Master-Slave Communication Flow

1. Master pulls CS LOW to select slave
2. Master generates SCLK pulses
3. On each clock edge: MOSI bit sent to slave; MISO bit received from slave
4. Data shifts out MSB first (or LSB first, depending on mode)
5. Master pulls CS HIGH to end transaction
SPI Modes (0-3): Defined by Clock Polarity (CPOL) and Clock Phase (CPHA)

10.3 I2C (Inter-Integrated Circuit)

I2C is a synchronous, half-duplex, multi-master bus protocol:
• 2-wire: SDA (Serial Data) and SCL (Serial Clock)
• Both lines are open-drain with external pull-up resistors
• SDA carries data; SCL is clock generated by master
• Each device has unique 7-bit (or 10-bit) address
• Master initiates communication with START condition and device address
• Speed: 100 kHz (standard), 400 kHz (fast), 1 MHz (fast-plus), 3.4 MHz (high-speed)

I2C Communication Protocol:

34. Master sends START condition (SDA falls while SCL is HIGH)
35. Master sends 7-bit slave address + R/W bit
36. Slave sends ACK bit (SDA = LOW)
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37. Data bytes exchanged with ACK after each byte

38. Master sends STOP condition (SDA rises while SCL is HIGH)

I2C Write Byte Format

[START] [7-bit Address] [W bit=0] [ACK] [8-bit Data] [ACK] [STOP]

I2C Read Byte Format:

[START] [7-bit Address] [R bit=1] [ACK] [8-bit Data] [NACK] [STOP]

10.4 CAN (Controller Area Network)

CAN is a robust differential serial bus designed for automotive and industrial applications:
• 2-wire differential: CAN_H and CAN_L (noise immune)
• Multi-master: Any node can transmit when bus is idle
• Message-based: Frames have 11-bit (or 29-bit extended) identifier, not node address
• Priority arbitration: Lower identifier = higher priority
• Built-in error detection: CRC, bit stuffing, frame check, ACK error
• Speed: Up to 1 Mbps (classical CAN); CAN FD up to 8 Mbps
• Applications: Automotive ECU communication, industrial automation, medical devices

10.5 USB (Universal Serial Bus) Fundamentals

USB is a high-speed serial bus standard for connecting peripherals:
• Differential pair: D+ and D- data lines
• Host/Device model: PC is always host; embedded device is peripheral
• Speeds: USB 1.1 (12 Mbps), USB 2.0 (480 Mbps), USB 3.0 (5 Gbps)
• Hot-plug capable: Devices can be connected/disconnected without system restart
• Power delivery: USB can supply 500 mA at 5V (USB 2.0); more with USB PD
• Classes: HID (keyboard/mouse), CDC (serial), Mass Storage, Audio, Video

10.6 RS-232C Interface Standard

RS-232C is the electrical standard for serial communication (used with UART):
• Logic 1 (MARK): -3V to -15V; Logic 0 (SPACE): +3V to +15V
• Handshaking signals: RTS (Request to Send), CTS (Clear to Send), DTR, DSR, DCD, RI
• Maximum cable length: ~15 meters at 9600 bps
• Single-ended; not differential; susceptible to noise
• DB-9 or DB-25 connector standard

11. Protocol Comparison

Protocol Wires Clock Speed Masters Use Case
UART 2 (TX,RX) None (async) ~115200 bps Peer-to-peer Debug, GPS

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Protocol Wires Clock Speed Masters Use Case

SPI 4 Shared (sync) Up to 100 1 master, N Flash, sensors
(MOSI/MISO/CLK/CS) MHz slaves

I2C 2 (SDA, SCL) Shared (sync) 100K-3.4M Multi-master Sensors,

bps EEPROMs

CAN 2 diff (H, L) None (async) Up to 1 Mbps Multi-master Automotive,

industrial
USB 4 (D+,D-,V,G) Shared (sync) Up to 5 Gbps Host-Device PC peripherals

12. Device Drivers

12.1 Need for Device Drivers
• Hardware abstraction: Applications don't need to know hardware-specific details
• Portability: Change hardware, keep application code same
• Multi-access: Multiple processes can access hardware through driver
• Security: Controlled access prevents conflicts

12.2 Basic Structure of a Device Driver

A device driver typically provides the following interface functions:

Driver Function Interface

open() - Initialize device and claim resources
close() - Release device resources
read() - Read data from device
write() - Write data to device
ioctl() - Device-specific control commands
irq_handler() - ISR for device-generated interrupts

Steps to Write a Device Driver:

39. Identify hardware: Read datasheet; understand registers and behavior
40. Map registers: Define register addresses as constants
41. Write init function: Configure hardware (clock, pins, mode)
42. Write ISR: Handle interrupts if using interrupt-driven mode
43. Write read/write functions: Implement data transfer
44. Test with hardware: Verify correct operation with oscilloscope or logic analyzer

12.3 Polling vs Interrupt-Driven Drivers

Polling Driver Interrupt-Driven Driver
CPU continuously checks status flag CPU does other work; ISR called when ready
Simple code structure Requires ISR setup, shared data structures

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Polling Driver Interrupt-Driven Driver

Good for very frequent events Good for infrequent or unpredictable events
Wastes CPU power Efficient CPU usage
Deterministic timing Small interrupt latency overhead
Example: SPI flash read loop Example: UART receive buffer ISR

13. DMA (Direct Memory Access)

DMA allows peripherals to transfer data directly to/from memory without CPU involvement:
• Frees CPU to execute other tasks during data transfer
• Much faster for large data blocks (e.g., audio buffer, ADC samples)
• DMA controller has separate bus access to memory

DMA Transfer Types:

• Single transfer: One unit at a time, alternating with CPU
• Burst transfer: Block of data transferred in continuous burst
• Cycle stealing: DMA steals bus cycles from CPU without halting it

DMA Operation Steps

1. CPU configures DMA: source address, destination address, transfer size
2. CPU enables DMA and continues executing other code
3. DMA controller requests bus access
4. DMA transfers data directly (memory to peripheral or peripheral to memory)
5. DMA raises interrupt when complete
6. CPU checks/processes transferred data

14. Watchdog Timer (WDT) - Detailed

Power-up Reset vs Watchdog Timer Reset:
Power-up Reset Watchdog Timer Reset
Occurs when power is first applied to system Occurs when software fails to kick WDT in time
Initializes all hardware to default state Resets system to recover from software hang
Not related to software behavior Indicates software malfunction
Expected and controlled event Emergency recovery mechanism
Triggered by POR (Power-On Reset) circuit Triggered by WDT counter overflow

15. Quick Revision - Key Definitions

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 CSPE3010 Embedded Systems | Module I & II Notes

Term Definition
Embedded System Special-purpose computer system for specific
function within larger system
Firmware Low-level software stored in non-volatile
memory; controls hardware directly
Bootloader First code to run on power-up; initializes
hardware and loads application
Cross-compilation Compiling code on Host machine (PC) for
execution on Target (MCU)
Watchdog Timer Hardware timer that resets system if software
does not refresh it periodically
ISR Interrupt Service Routine - code executed in
response to an interrupt
PWM Pulse Width Modulation - varies duty cycle to
control power to load
ADC Analog-to-Digital Converter - converts real-
world analog signals to digital
DAC Digital-to-Analog Converter - converts digital
values to analog voltage/current
CPSR Current Program Status Register - holds ARM
processor status flags and mode
SPSR Saved Program Status Register - saves CPSR
during exception handling
Thumb Mode 16-bit ARM instruction set; smaller code size,
lower memory usage
DMA Direct Memory Access - peripheral transfers
data directly to/from memory
Device Driver Software layer abstracting hardware from
application code
Linker Combines object files; resolves symbols;
assigns final memory addresses
RISC Reduced Instruction Set Computer - simple,
fixed-length, load-store architecture

— End of Notes —
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