CPU CONTROL UNIT DESIGN:

 Hardwired CU: In Hardwired CU, control signals are produced by hardware. There are three types of
Hardwired Control Units, i.e.
1) STATE TABLE METHOD
2) DELAY ELEMENT METHOD
3) SEQUENCE COUNTER METHOD
1) STATE TABLE METHOD:
 It is the most basic type of hardwired control unit.
 Here the behaviour of the control unit is represented in the form of a table called the state table.
 The rows represent the T-states and the columns indicate the instructions.
 Each intersection indicates the control signal to be produced, in the corresponding T-state of every instruction.
 A circuit is then constructed based on every column of this table, for each instruction.

ADVANTAGE: It is the simplest method and is ideally suited for very small instruction sets.

DRAWBACK:
 As the number of instructions increase, the circuit becomes bigger and hence more complicated.
 As a tabular approach is used, instead of a logical approach (flowchart), there are duplications of many circuit
elements in various instructions.
2. DELAY ELEMENT METHOD:
 Here the behaviour of the control unit is represented in the form of a flowchart.
 Each step in the flowchart represents a control signal to be produced.
 Once all steps of a particular instruction, are performed, the complete instruction gets executed.
 Control signals perform Micro-Operations, which require one T-states each.
 Hence between every two steps of the flowchart, there must be a delay element.
 The delay must be exactly of one T-state. This delay is achieved by D Flip-Flops.
 These D Flip-Flops are inserted between every two consecutive control signals.
  Out of all D Flip-Flops only one will be active at a time. So, the method is also called “One Hot Method”.
 In a multiple entry point, to combine two or more paths, we use an OR gate.

 A decision box is replaced by a set of two complementing AND gates

 A multiple entry point is substituted by an OR gate.

ADVANTAGE:
 As the method has a logical approach, it can reduce the circuit complexity.
 This is done by re-utilizing common elements between various instructions.
DRAWBACK:
 As the number of instructions increase, the number of D Flip-Flops increase, so the cost increases.
 Moreover, only one of those D Flip-Flops are actually active at a time.
3. SEQUENCE COUNTER METHOD:

 This is the most popular form of hardwired control unit. The goal of this circuit is to provide triggers to different
parts of the circuit after gaps of 1-Tstate.
 It follows the same logical approach of a flowchart, like the Delay element method, but does not use all those
unnecessary D Flip-Flops because at any point of time only one delay element is active and a complex circuitry
would involve many delay elements which is very inefficient. The D-Flip-flops are replaced by trigger points which
are activated after gaps of one T-state.
Following are the steps involved in designing a CU using Sequence Counter Method.
1) First a flowchart is made representing the behaviour of a control unit.
2) It is then converted into a circuit using the same principle of AND & OR gates.
3) We need a delay of 1 T-state (one clock cycle) between every two consecutive control signals.
4) That is achieved by the above circuit.
5) If there are “k” number of distinct steps producing control signals, we employ a “mod k” and “k” output
decoder.
6) The counter will start counting at the beginning of the instruction.
7) The “clock” input via an AND gate ensures each count will be generated after 1 T-state.
8)The count is given to the decoder which triggers the generation of “k” control signals, each after a delay of 1 T-
state.
9)When the instruction ends, the counter is reset so that next time, it begins from the first count.
ADVANTAGE:
 Avoids the use of too many D Flip-Flops.

GENERAL DRAWBACKS OF A HARDWIRED CONTROL UNIT

1) Since they are based on hardware, as the instruction set increases, the circuit becomes more and more
complex. For modern processors having hundreds of instructions, it is virtually impossible to create Hardwired
Control Units.
2) Such large circuits are very difficult to debug.
3) As the processor gets upgraded, the entire Control Unit has to be redesigned, due to the rigid nature of
hardware design.
Microprogrammed CU
WILKES’ DESIGN FOR A MICROPROGRAMMED CONTROL UNIT:
 Microprogrammed Control Unit produces control signals by software, using micro-instructions.
 A program is a set of instructions.
 An instruction requires a set of Micro-Operations.
 Micro-Operations are performed by control signals.
 Instead of generating these control signals by hardware, we use micro-instructions. This means every instruction
requires a set of micro-instructions This is called its micro-program.
 Microprograms for all instructions are stored in a small memory called “Control Memory”. The Control memory is
present inside the processor.
 Consider an Instruction that is fetched from the main memory into the Instruction Register (IR).
 The processor uses its unique “opcode” to identify the address of the first micro-instruction. That address is
loaded into CMAR (Control Memory Address Register). CMAR passes the address to the decoder.
 The decoder identifies the corresponding micro-instruction from the Control Memory.
 A micro-instruction has two fields: a control filed and an address field.
Control field: Indicates the control signals to be generated.
Address field: Indicates the address of the next micro-instruction.
 This address is further loaded into CMAR to fetch the next micro-instruction.
 For a conditional micro-instruction, there are two address fields. This is because, the address of the next
micro-instruction depends on the condition. The condition (true or false) is decided by the appropriate
control flag.
 The control memory is usually implemented using FLASH ROM as it is writable yet non-volatile.
ADVANTAGES:
1. The biggest advantage is flexibility.
2. Any change in the control unit can be performed by simply changing the micro-instruction.
3. This makes modifications and up gradation of the Control Unit very easy.
4. Moreover, software can be much easily debugged as compared to a large Hardwired Control Unit.
DRAWBACKS:
1. Control memory has to be present inside the processor, increasing its size.
2. This also increases the cost of the processor.
3. The address field in every micro-instruction adds more space to the control memory. This can be easily avoided by
proper micro-instruction sequencing.
TYPICAL MICROPROGRAMMED CONTROL UNIT
 Microprogrammed Control Unit produces control signals by software, using micro-instructions.
 A program is a set of instructions.
 An instruction requires a set of Micro-Operations.
 Micro-Operations are performed by control signals.
 Here, these control signals are generated using micro-instructions.
 This means every instruction requires a set of micro-instructions.
 This is called its micro-program.
 Microprograms for all instructions are stored in a small memory called “Control Memory”.
 The Control memory is present inside the processor.
 Consider an Instruction that is fetched from the main memory into the Instruction Register (IR).
 The processor uses its unique “opcode” to identify the address of the first micro-instruction.
 That address is loaded into CMAR (Control Memory Address Register) also called μIR.
  This address is decoded to identify the corresponding μ-instruction from the Control Memory.
 There is a big improvement over Wilkes’ design, to reduce the size of micro-instructions.
 Most micro-instructions will only have a Control field.
 The Control field Indicates the control signals to be generated.
 Most micro-instructions will not have an address field.
 Instead, μPC will simply get incremented after every micro-instruction.
 This is as long as the μ-program is executed sequentially.
 If there is a branch μ-instruction only then there will be an address filed.
 If the branch is unconditional, the branch address will be directly loaded into CMAR.
 For Conditional branches, the Branch condition will check the appropriate flag.
 This is done using a MUX which has all flag inputs.
 If the condition is true, then the MUX will inform CMAR to load the branch address.
 If the condition is false CMAR will simply get incremented.
 The control memory is usually implemented using FLASH ROM as it is writable yet non-volatile.
ADVANTAGES:
1. The biggest advantage is flexibility.
2. Any change in the control unit can be performed by simply changing the micro-instruction.
3. This makes modifications and up gradation of the Control Unit very easy.
4. Moreover, software can be much easily debugged as compared to a large Hardwired Control Unit.
5. Since most micro-instructions are executed sequentially, they don’t need for an address field.
6. This significantly reduces the size of micro-instructions, and hence the Control Memory.
DRAWBACKS:
1. Control memory has to be present inside the processor, increasing its size.
2. This also increases the cost of the processor.
 Hardwired Control Unit Micro-programmed Control Unit

With the help of a hardware circuit, we can implement While with the help of programming, we can
the hardwired control unit. In other words, we can say implement the micro-programmed control unit.
that it is a circuitry approach.

The hardwired control unit uses the logic circuit so that The micro-programmed CU uses microinstruction so
it can generate the control signals, which are required that it can generate the control signals. Usually, control
for the processor. memory is used to store these microinstructions.

In this CU, the control signals are going to be generated It is very easy to modify the micro-programmed
in the form of hard wired. That's why it is very difficult control unit because the modifications are going to be
to modify the hardwired control unit. performed only at the instruction level.

In the form of logic gates, everything has to be realized The micro-programmed control unit is less costly as
in the hardwired control unit. That's why this CU is compared to the hardwired CU because this control
more costly as compared to the micro-programmed unit only requires the microinstruction to generate the
control unit. control signals.

The complex instructions cannot be handled by a The micro-programmed control unit is able to handle
hardwired control unit because when we design a the complex instructions.
circuit for this instruction, it will become complex.

Because of the hardware implementation, the The micro-programmed control unit is able to generate
hardwired control unit is able to use a limited number control signals for many instructions.
of instructions.

The hardwired control unit is used in those types of The micro-programmed control unit is used in those
computers that also use the RISC (Reduced instruction types of computers that also use the CISC (Complex
Set Computers). instruction Set Computers).

In the hardwired control unit, the hardware is used to In this CU, the microinstructions are used to generate
generate only the required control signals. That's why the control signals. That's why this CU is slower than
this control unit is faster as compared to the micro- the hardwired control unit.
programmed control unit.
Memory System Design:
 Semiconductor Memory Technologies:
 Semiconductor random-access memories (RAMs) are available in a wide range of speeds.
 Their cycle times range from 100 ns to less than 10 ns.
 Semiconductor memory is used in any electronics assembly that uses computer processing technology.
 The use of semiconductor memory has grown, and the size of these memory cards has increased as the need for
larger and larger amounts of storage is needed.
There are two main types or categories that can be used for semiconductor technology.
 RAM - Random Access Memory:
 As the names suggest, the RAM or random-access memory is a form of semiconductor memory technology that is
used for reading and writing data in any order - in other words as it is required by the processor.
 It is used for such applications as the computer or processor memory where variables and other stored and are
required on a random basis.
 Data is stored and read many times to and from this type of memory.

 ROM - Read Only Memory:

 A ROM is a form of semiconductor memory technology used where the data is written once and then not
changed.
 In view of this it is used where data needs to be stored permanently, even when the power is removed - many
memory technologies lose the data once the power is removed.
 As a result, this type of semiconductor memory technology is widely used for storing programs and data that must
survive when a computer or processor is powered down.
 For example, the BIOS of a computer will be stored in ROM.
 As the name implies, data cannot be easily written to ROM.
 Depending on the technology used in the ROM, writing the data into the ROM initially may require special
hardware.
 Although it is often possible to change the data, this gain requires special hardware to erase the data ready for
new data to be written in.
The different memory types or memory technologies are detailed below:
 DRAM:
 Dynamic RAM is a form of random-access memory.
 DRAM uses a capacitor to store each bit of data, and the level of charge on each capacitor determines whether
that bit is a logical 1 or 0.
 However, these capacitors do not hold their charge indefinitely, and therefore the data needs to be refreshed
periodically.
 As a result of this dynamic refreshing, it gains its name of being a dynamic RAM. DRAM is the form of
semiconductor memory that is often used in equipment including personal computers and workstations where it
forms the main RAM for the computer.
 EEPROM:
 This is an Electrically Erasable Programmable Read Only Memory. Data can be written to it and it can be erased
using an electrical voltage.
 This is typically applied to an erase pin on the chip. Like other types of PROM, EEPROM retains the contents of the
memory even when the power is turned off.
 Also, like other types of ROM, EEPROM is not as fast as RAM.
 EPROM:
 This is an Erasable Programmable Read Only Memory. This form of semiconductor memory can be programmed
and then erased at a later time.
 This is normally achieved by exposing the silicon to ultraviolet light.
 To enable this to happen there is a circular window in the package of the EPROM to enable the light to reach the
silicon of the chip.
 When the PROM is in use, this window is normally covered by a label, especially when the data may need to be
preserved for an extended period.
 The PROM stores its data as a charge on a capacitor. There is a charge storage capacitor for each cell and this can
be read repeatedly as required.
 However, it is found that after many years the charge may leak away and the data may be lost.
 Nevertheless, this type of semiconductor memory used to be widely used in applications where a form of ROM
was required, but where the data needed to be changed periodically, as in a development environment, or where
quantities were low.
 FLASH MEMORY:
 Flash memory may be considered as a development of EEPROM technology.
 Data can be written to it and it can be erased, although only in blocks, but data can be read on an individual cell
basis.
 To erase and re-programme areas of the chip, programming voltages at levels that are available within electronic
equipment are used.
 It is also non-volatile, and this makes it particularly useful.
 As a result, Flash memory is widely used in many applications including memory cards for digital cameras, mobile
phones, computer memory sticks and many other applications.
 F-RAM:
 Ferroelectric RAM is a random-access memory technology that has many similarities to the standard DRAM
technology.
 The major difference is that it incorporates a ferroelectric layer instead of the more usual dielectric layer and this
provides its non-volatile capability.
 As it offers a non-volatile capability, F-RAM is a direct competitor to Flash.

 MRAM:
 This is Magneto-resistive RAM, or Magnetic RAM.
 It is a non-volatile RAM memory technology that uses magnetic charges to store data instead of electric charges.
 Unlike technologies including DRAM, which require a constant flow of electricity to maintain the integrity of the
data, MRAM retains data even when the power is removed.
 An additional advantage is that it only requires low power for active operation.
 As a result, this technology could become a major player in the electronics industry now that production
processes have been developed to enable it to be produced.

 P-RAM / PCM:
 This type of semiconductor memory is known as Phase change Random Access Memory, P-RAM or just Phase
Change memory, PCM.
 It is based around a phenomenon where a form of chalcogenide glass changes is state or phase between an
amorphous state (high resistance) and a polycrystalline state (low resistance).
 It is possible to detect the state of an individual cell and hence use this for data storage. Currently this type of
memory has not been widely commercialized, but it is expected to be a competitor for flash memory.

 PROM:
 This stands for Programmable Read Only Memory.
 It is a semiconductor memory which can only have data written to it once - the data written to it is permanent.
 These memories are bought in a blank format and they are programmed using a special PROM programmer.
 Typically, a PROM will consist of an array of useable links some of which are "blown" during the programming
process to provide the required data pattern.

 SDRAM:
 Synchronous DRAM. This form of semiconductor memory can run at faster speeds than conventional DRAM.
 It is synchronised to the clock of the processor and is capable of keeping two sets of memory addresses open
simultaneously.
 By transferring data alternately from one set of addresses, and then the other, SDRAM cuts down on the delays
associated with non-synchronous RAM, which must close one address bank before opening the next.

 SRAM:
 Static Random Access Memory.
 This form of semiconductor memory gains its name from the fact that, unlike DRAM, the data does not need to be
refreshed dynamically.
 It is able to support faster read and write times than DRAM (typically 10 ns against 60 ns for DRAM), and in
addition its cycle time is much shorter because it does not need to pause between accesses.
 However, it consumes more power, is less dense and more expensive than DRAM.
 As a result of this it is normally used for caches, while DRAM is used as the main semiconductor memory
technology.
MEMORY ORGANIZATION:
 MEMORY HIERARCHY
 The memory unit is an essential component in any digital computer since it is needed for storing programs
and data. A very small computer with a limited application may be able to fulfil its intended task without
the need of additional storage capacity.
 Most general-purpose computers would run more efficiently if they were equipped with additional storage
beyond the capacity of the main memory.
 It is more economical to use low-cost storage devices to serve as a backup for storing the information that
is not currently used by the CPU.
 The memory unit that communicates directly with the CPU is called the main memory. Devices that
provide backup storage are called auxiliary memory. The most common auxiliary memory devices used
in computer systems are magnetic disks and tapes. They are used for storing system programs, large data
files, and other backup information. Only programs and data currently needed by the processor reside in
main memory. All other information is stored in auxiliary memory and transferred to main memory when
needed.
 The memory hierarchy system consists of all storage devices employed in a computer system from the
slow but high-capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster
cache memory accessible to the high-speed processing logic.

 The main memory occupies a central position by being able to communicate directly with the CPU and
with auxiliary memory devices through an I/O processor.
 When programs not residing in main memory are needed by the CPU, they are brought in from auxiliary
memory. Programs not currently needed in main memory are transferred into auxiliary memory to provide
space for currently used programs and data.
 A special very-high speed memory called a cache is sometimes used to increase the speed of processing
by making current programs and data available to the CPU at a rapid rate. The cache memory is employed
in computer systems to compensate for the speed differential between main memory access time and
processor logic.
 CPU logic is usually faster than main memory access time, with the result that processing speed is limited
primarily by the speed of main memory.
 A technique used to compensate for the mismatch in operating speeds is to employ in extremely fast, small
cache between the CPU and main memory whose access time is close to processor logic clock cycle time.
 The reason for having two or three levels of memory hierarchy is economics.
 As the storage capacity of the memory increases, the cost per bit for storing binary information decreases
and the access time of the memory becomes longer.
 The overall goal of using a memory hierarchy is to obtain the highest-possible average access speed while
minimizing the total cost of the entire memory system.
 Auxiliary and cache memories are used for different purposes. The cache holds those parts of the program
and data that are most heavily used, while the auxiliary memory holds those parts that are not presently
used by the CPU. Moreover, the CPU has direct access to both cache and main memory but not to auxiliary
memory. The transfer from auxiliary to main memory is usually done by means of direct memory access
of large blocks of data. The typical access time ratio between cache and main memory is about 1 to 7. For
example, a typical cache memory may have an access time of 100ns, while main memory access time may
be 700ns. Auxiliary memory average access time is usually 1000 times that of main memory. Block size in
auxiliary memory typically ranges from256 to 2048 words, while cache block size is typically from 1 to 16
words.
 Many operating systems are designed to enable the CPU to process a number of independent programs
concurrently. This concept, called multiprogramming, refers to the existence of two or more programs in
different parts of the memory hierarchy at the same time.
 In a multiprogramming system, when one program is waiting for input or output transfer, there is another
program ready to utilize the CPU.
 Computer programs are sometimes too long to be accommodated in the total space available in main
memory.
 When the program or a segment of the program is to be executed, it is transferred to main memory to be
executed by the CPU.
 It is the task of the operating system to maintain in main memory a portion of this information that is
currently active.
 The part of the computer system that supervises the flow of information between auxiliary memory and
main memory is called the memory management system.
 MAIN MEMORY:
 The main memory is the central storage unit in a computer system. It is a relatively large and fast memory used to
store programs and data during the computer operation.
 The principal technology used for the main memory is based on semiconductor integrated circuits.
 Integrated circuit RAM chips are available in two possible operating modes, static and dynamic. The static RAM
consists essentially of internal flip-flops that store the binary information. The stored information remains valid as
long as power is applied to unit. The dynamic RAM stores the binary information in the form of electric charges
that are applied to capacitors. The capacitors are provided inside the chip by MOS transistors. The stored charge
on the capacitors tends to discharge with time and the capacitors must be periodically recharged by refreshing the
dynamic memory.
 The dynamic RAM offers reduced power consumption and larger storage capacity in a single memory chip.
 The static RAM is easier to use and has shorted read and write cycles.
 Most of the main memory in a general-purpose computer is made up of RAM integrated circuit chips, but a portion
of the memory may be constructed with ROM chips.
 RAM refers to a random-access memory, but it is used to designate a read/write memory to distinguish it from a
read-only memory, although ROM is also random access.
 RAM is used for storing the bulk of the programs and data that are subject to change. ROM is used for storing
programs that are permanently resident in the computer.
 The ROM portion of main memory is needed for storing an initial program called a bootstrap loader. The bootstrap
loader is a program whose function is to start the computer software operating when power is turned on.
 Since RAM is volatile, its contents are destroyed when power is turned off. The contents of ROM remain unchanged
after power is turned off and on again.
 The startup of a computer consists of turning the power on and starting the execution of an initial program. Thus,
when power is turned on, the hardware of the computer sets the program counter to the first address of the
bootstrap loader. The bootstrap program loads a portion of the operating system from disk to main memory and
control is then transferred to the operating system, which prepares the computer for general use.
 RAM and ROM chips are available in a variety of sizes. If the memory needed for the computer is larger than the
capacity of one chip, it is necessary to combine a number of chips to form the required memory size. Ex: 1024 × 8
memory can be constructed with 128 × 8 RAM chips and 512 × 8 ROM chips.
 AUXILIARY MEMORY:
 The most common auxiliary memory devices used in computer systems are magnetic disks and magnetic tapes.
Other components used, but not as frequently, are magnetic drums, magnetic bubble memory, and optical disks.
 The important characteristics of any device are its access mode, access time, transfer rate, capacity, and cost.
 The average time required to reach a storage location in memory and obtain its contents is called the access time.
The access time consists of a seek time required to position the read write head to a location and a transfer time
required to transfer data to or from the device.
 Auxiliary storage is organized in records or blocks. A record is a specified number of characters or words. Reading
or writing is always done on entire records. The transfer rate is the number of characters or words that the device
can transfer per second, after it has been positioned at the beginning of the record.
 Magnetic drums and disks are quite similar in operation. Both consist of high-speed rotating surfaces coated with
a magnetic recording medium. The rotating surface of the drum is a cylinder and that of the disk, a round flat plate.
Bits are recorded as magnetic spots on the surface as it passes a stationary mechanism called a write head. Stored
bits are detected by a change in magnetic field produced by a recorded spot on the surface as it passes through a
read head.

 ASSOCIATIVE MEMORY:
 Many data-processing applications require the search of items in a table stored in memory. An assembler program
searches the symbol address table in order to extract the symbol’s binary equivalent.
 The number of accesses to memory depends on the location of the item and the efficiency of the search algorithm.
Many search algorithms have been developed to minimize the number of accesses while searching for an item in a
random or sequential access memory.
 The time required to find an item stored in memory can be reduced considerably if stored data can be identified for
access by the content of the data itself rather than by an address.
 A memory unit accessed by content is called an associative memory or content addressable memory (CAM).
 When a word is to be read from an associative memory, the content of the word, or part of the word, is specified.
The memory locates all words which match the specified content and marks them for reading.
 An associative memory is more expensive than a random-access memory because each cell must have storage
capability as well as logic circuits for matching its content with an external argument. For this reason, associative
memories are used in applications where the search time is very critical and must be very short.
HARDWARE ORGANIZATION:
 The block diagram of an associative memory is
Shown in Fig.
 It consists of a memory array and logic for m
Words with n bits per word. The argument
register A and key register K each have n bits,
one for each bit of a word. The match register
M has m bits, one for each memory word.
 Each word in memory is compared in parallel
with the content of the argument register.
The words that match the bits of the argument
register set a corresponding bit in the match
register.
 After the matching process, those bits in the
match register that have been set indicate the
fact that their corresponding words have been
matched.
 Reading is accomplished by a sequential access to memory for those words whose corresponding bits in the match
register have been set.
 The key register provides a mask for choosing a particular field or key in the argument word.
 The entire argument is compared with each memory word if the key register contains all 1’s. Otherwise, only those
bits in the argument that have 1’s in their corresponding position of the key register is compared.
 To illustrate with a numerical example, suppose that the argument registers A and the key register K have the bit
configuration shown below. Only the three leftmost bits of A are compared with memory words because K has 1’s
in these positions.
A 101 111100
K 111 000000
Word 1 100 111100 no match
Word 2 101 000001 match
 The relation between the memory array and external registers in an associative memory is shown in Fig.
 The cells in the array are marked by the letter C with two subscripts. The first subscript gives the word number and
the second specifies the bit position in the word. Thus, cell Cij is the cell for bit j in word i.
 A bit Aj in the argument register is compared with all the bits in column j of the array provided that Kj = 1. This is
done for all columns j = 1, 2,…,n.
 If a match occurs between all the unmasked bits of the argument and the bits in word i, the corresponding bit Mi in
the match register is set to 1. If one or more unmasked bits of the argument and the word do not match, Mi is
cleared to 0.
 The internal organization of a typical cell Cij is shown in Fig.
 It consists of a flipflop storage element Fij and the circuits for reading, writing, and matching the cell.
 The input bit is transferred into the storage cell during a write operation. The bit stored is read out during a read
operation.
 The match logic compares the content of the storage cell with the corresponding unmasked bit of the argument
and provides an output for the decision logic that sets the bit in Mi.
 CACHE MEMORY:
 Locality of Reference: The references to memory at any given time interval tends to be confined within a localized area.
 When a program loop is executed, the CPU repeatedly refers to the set of instructions in memory that constitute the
loop.
 Every time a given subroutine is called, its set of instructions is fetched from memory. Thus, loops and subroutines tend
to localize the references to memory for fetching instructions.
 Iterative procedures refer to common memory locations and array of numbers are confined within a local portion of
memory.
 If the active portions of the program and data are placed in a fast small memory, the average memory access time can
be reduced, thus reducing the total execution time of the program. Such a fast small memory is referred to as a cache
memory. The cache is the fastest component in the memory hierarchy and approaches the speed of CPU components.
 When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is read from the fast
memory. If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the word. A
block of words containing the one just accessed is then transferred from main memory to cache memory. The
performance of cache memory is frequently measured in terms of a quantity called hit ratio. When the CPU refers to
memory and finds the word in cache, it is said to produce a hit. If the word is not found in cache, it is in main memory
and it counts as a miss. The ratio of the number of hits divided by the total CPU references to memory (hits plus misses)
is the hit ratio.
 The average memory access time of a computer system can be improved considerably by use of a cache.
 The transformation of data from main memory to cache memory is referred to as a mapping process. Three types of
mapping procedures are:
1. Associative mapping
2. Direct mapping
3. Set-associative mapping.
 Consider the following memory organization:
Memory Hierarchy:
 A memory unit is an essential component in any digital computer since it is needed for storing programs and data.
Typically, a memory unit can be classified into two categories:
1. The memory unit that establishes direct communication with the CPU is called Main Memory. The main memory is
often referred to as RAM (Random Access Memory).
2. The memory units that provide backup storage are called Auxiliary Memory. For instance, magnetic disks and
magnetic tapes are the most commonly used auxiliary memories.
 Apart from the basic classifications of a memory unit, the memory hierarchy consists all of the storage devices available
in a computer system ranging from the slow but high-capacity auxiliary memory to relatively faster main memory.
The following image illustrates the components in a typical memory hierarchy.

Auxiliary Memory:
 Auxiliary memory is known as the lowest-cost, highest-capacity and slowest-access storage in a computer system.
 Auxiliary memory provides storage for programs and data that are kept for long-term storage or when not in immediate
use.
 The most common examples of auxiliary memories are magnetic tapes and magnetic disks.
 A magnetic disk is a digital computer memory that uses a magnetization process to write, rewrite and access data. For
example, hard drives, zip disks, and floppy disks.
 Magnetic tape is a storage medium that allows for data archiving, collection, and backup for different kinds of data.
Main Memory:
 The main memory in a computer system is often referred to as Random Access Memory (RAM). This memory unit
communicates directly with the CPU and with auxiliary memory devices through an I/O processor.
 The programs that are not currently required in the main memory are transferred into auxiliary memory to provide
space for currently used programs and data.
I/O Processor:
 The primary function of an I/O Processor is to manage the data transfers between auxiliary memories and the main
memory.
Cache Memory:
 The data or contents of the main memory that are used frequently by CPU are stored in the cache memory so that the
processor can easily access that data in a shorter time.
 Whenever the CPU requires accessing memory, it first checks the required data into the cache memory.
 If the data is found in the cache memory, it is read from the fast memory. Otherwise, the CPU moves onto the main
memory for the required data.
Main Memory:
 The main memory acts as the central storage unit in a computer system. It is a relatively large and fast memory which
is used to store programs and data during the run time operations.
 The primary technology used for the main memory is based on semiconductor integrated circuits. The integrated
circuits for the main memory are classified into two major units.
1. RAM (Random Access Memory) integrated circuit chips
2. ROM (Read Only Memory) integrated circuit chips
RAM integrated circuit chips:
 The RAM integrated circuit chips are further classified into two possible operating modes, static and dynamic.
 The primary compositions of a static RAM are flip-flops that store the binary information. The nature of the stored
information is volatile, i.e. it remains valid as long as power is applied to the system. The static RAM is easy to use and
takes less time performing read and write operations as compared to dynamic RAM.
 The dynamic RAM exhibits the binary information in the form of electric charges that are applied to capacitors. The
capacitors are integrated inside the chip by MOS transistors. The dynamic RAM consumes less power and provides large
storage capacity in a single memory chip.
 RAM chips are available in a variety of sizes and are used as per the system requirement. The following block diagram
demonstrates the chip interconnection in a 128 * 8 RAM chip.

 A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits (one byte) per word. This requires a 7-bit
address and an 8-bit bidirectional data bus.
 The 8-bit bidirectional data bus allows the transfer of data either from memory to CPU during a read operation or
from CPU to memory during a write operation.
 The read and write inputs specify the memory operation, and the two chip select (CS) control inputs are for
enabling the chip only when the microprocessor selects it.
 The bidirectional data bus is constructed using three-state buffers.
 The output generated by three-state buffers can be placed in one of the three possible states which include a signal
equivalent to logic 1, a signal equal to logic 0, or a high-impedance state.
Note: The logic 1 and 0 are standard digital signals whereas the high-impedance state behaves like an open circuit,
which means that the output does not carry a signal and has no logic significance.
 The following function table specifies the operations of a 128 * 8 RAM chip.

 From the functional table, we can conclude that the unit is in operation only when CS1 = 1 and CS2 = 0. The bar on top
of the second select variable indicates that this input is enabled when it is equal to 0.
ROM integrated circuit
 The primary component of the main memory is RAM integrated circuit chips, but a portion of memory may be
constructed with ROM chips.
 A ROM memory is used for keeping programs and data that are permanently resident in the computer.
 Apart from the permanent storage of data, the ROM portion of main memory is needed for storing an initial program
called a bootstrap loader. The primary function of the bootstrap loader program is to start the computer software
operating when power is turned on.
 ROM chips are also available in a variety of sizes and are also used as per the system requirement. The following block
diagram demonstrates the chip interconnection in a 512 * 8 ROM chip.

 A ROM chip has a similar organization as a RAM chip. However, a ROM can only perform read operation; the data bus
can only operate in an output mode.
 The 9-bit address lines in the ROM chip specify any one of the 512 bytes stored in it.
 The value for chip select 1 and chip select 2 must be 1 and 0 for the unit to operate. Otherwise, the data bus is said to
be in a high-impedance state.
Auxiliary Memory:
 An Auxiliary memory is known as the lowest-cost, highest-capacity and slowest-access storage in a computer system.
 It is where programs and data are kept for long-term storage or when not in immediate use.
 The most common examples of auxiliary memories are magnetic tapes and magnetic disks.
Magnetic Disks
 A magnetic disk is a type of memory constructed using a circular plate of metal or plastic coated with magnetized
materials.
 Usually, both sides of the disks are used to carry out read/write operations.
 However, several disks may be stacked on one spindle with read/write head available on each surface.
The following image shows the structural representation for a magnetic disk.

 The memory bits are stored in the magnetized surface in spots along the concentric circles called tracks.
 The concentric circles (tracks) are commonly divided into sections called sectors.
Magnetic Tape:
 Magnetic tape is a storage medium that allows data archiving, collection, and backup for different kinds of data.
 The magnetic tape is constructed using a plastic strip coated with a magnetic recording medium.
 The bits are recorded as magnetic spots on the tape along several tracks. Usually, seven or nine bits are recorded
simultaneously to form a character together with a parity bit.
 Magnetic tape units can be halted, started to move forward or in reverse, or can be rewound.
 However, they cannot be started or stopped fast enough between individual characters. For this reason, information is
recorded in blocks referred to as records.
Associative Memory:
 An associative memory can be considered as a memory unit whose stored data can be identified for access by the
content of the data itself rather than by an address or memory location.
 Associative memory is often referred to as Content Addressable Memory (CAM).
 When a write operation is performed on associative memory, no address or memory location is given to the word. The
memory itself is capable of finding an empty unused location to store the word.
 On the other hand, when the word is to be read from an associative memory, the content of the word, or part of the
word, is specified. The words which match the specified content are located by the memory and are marked for reading.
 The following diagram shows the block representation of an Associative memory.

 From the block diagram, we can say that an associative memory consists of a memory array and logic for 'm' words
with 'n' bits per word.
 The functional registers like the argument register A and key register K each have n bits, one for each bit of a word.
The match register M consists of m bits, one for each memory word.
 The words which are kept in the memory are compared in parallel with the content of the argument register.
 The key register (K) provides a mask for choosing a particular field or key in the argument word.
 If the key register contains a binary value of all 1's, then the entire argument is compared with each memory word.
 Otherwise, only those bits in the argument that have 1's in their corresponding position of the key register are
compared.
 Thus, the key provides a mask for identifying a piece of information which specifies how the reference to memory is
made.
 The following diagram can represent the relation between the memory array and the external registers in an
associative memory.
 The cells present inside the memory array are marked by the letter C with two subscripts.
 The first subscript gives the word number and the second specifies the bit position in the word. For instance, the cell
Cij is the cell for bit j in word i.
 A bit Aj in the argument register is compared with all the bits in column j of the array provided that Kj = 1.
 This process is done for all columns j = 1, 2, 3......, n.
 If a match occurs between all the unmasked bits of the argument and the bits in word i, the corresponding bit Mi in
the match register is set to 1.
 If one or more unmasked bits of the argument and the word do not match, M i is cleared to 0.
Cache Memory:
 The data or contents of the main memory that are used frequently by CPU are stored in the cache memory so that the
processor can easily access that data in a shorter time.
 Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not found in cache memory,
then the CPU moves into the main memory.
 Cache memory is placed between the CPU and the main memory.
 The block diagram for a cache memory can be represented as:

 The cache is the fastest component in the memory hierarchy and approaches the speed of CPU components.
 Cache memory is organised as distinct set of blocks where each set contains a small fixed number of blocks.

 As shown in the above sets are represented by the rows.

 The example contains N sets and each set contains four blocks.
 Whenever an access is made to cache, the cache controller does not search the entire cache in order to look for a
match.
 Rather, the controller maps the address to a particular set of the cache and therefore searches only the set for a
match.
 If a required block is not found in that set, the block is not present in the cache and cache controller does not search
it further.
 This kind of cache organisation is called set associative because the cache is divided into distinct sets of blocks. As
each set contains four blocks the cache is said to be four ways set associative.
The basic operation of a cache memory is as follows:
 When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is read from the
fast memory.
 If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the word.
 A block of words one just accessed is then transferred from main memory to cache memory. The block size may vary
from one word (the one just accessed) to about 16 words adjacent to the one just accessed.
 The performance of the cache memory is frequently measured in terms of a quantity called hit ratio.
 When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
 If the word is not found in the cache, it is in main memory and it counts as a miss.
 The ratio of the number of hits divided by the total CPU references to memory (hits plus misses) is the hit ratio.
Levels of memory:
 Level 1: It is a type of memory in which data is stored and accepted that are immediately stored in CPU. Most
commonly used register is accumulator, Program counter, address register etc.
 Level 2: It is the fastest memory which has faster access time where data is temporarily stored for faster access.
 Level 3: It is memory on which computer works currently. It is small in size and once power is off data no longer
stays in this memory.
 Level 4: It is external memory which is not as fast as main memory but data stays permanently in this memory.
Cache Mapping:
There are three different types of mapping used for the purpose of cache memory which are as follows:
1. Direct mapping,
2. Associative mapping
3. Set-Associative mapping
1. Direct Mapping -
 In direct mapping, the cache consists of normal high-speed random-access memory.
 Each location in the cache holds the data, at a specific address in the cache.
 This address is given by the lower significant bits of the main memory address.
 This enables the block to be selected directly from the lower significant bit of the memory address.
 The remaining higher significant bits of the address are stored in the cache with the data to complete the
identification of the cached data.
  As shown in the above figure, the address from processor is divided into two field a tag and an index.
 The tag consists of the higher significant bits of the address and these bits are stored with the data in cache.
 The index consists of the lower significant b of the address.
 Whenever the memory is referenced, the following sequence of events occurs
1. The index is first used to access a word in the cache.
2. The tag stored in the accessed word is read.
3. This tag is then compared with the tag in the address.
4. If two tags are same this indicates cache hit and required data is read from the cache word.
5. If the two tags are not same, this indicates a cache miss. Then the reference is made to the main memory to
find it.
 For a memory read operation, the word is then transferred into the cache. It is possible to pass the information to
the cache and the process simultaneously.
 In direct mapped cache, there can also be a line consisting of more than one word as shown in the following figure

 In such a case, the main memory address consists of a tag, an index and a word within a line. All the words within
a line in the cache have the same stored tag
 The index part in the address is used to access the cache and the stored tag is compared with required tag
address.
 For a read operation, if the tags are same, the word within the block is selected for transfer to the processor.
 If tags are not same, the block containing the required word is first transferred to the cache.
 In direct mapping, the corresponding blocks with the same index in the main memory will map into the same
block in the cache, and hence only blocks with different indices can be in the cache at the same time.
 It is important that all words in the cache must have different indices. The tags may be the same or different.
2. Set Associative Mapping -
 In set associative mapping a cache is divided into a set of blocks.
 The number of blocks in a set is known as associativity or set size. Each block in each set has a stored tag. This tag
together with index completely identify the block.
 Thus, set associative mapping allows a limited number of blocks, with the same index and different tags.
  An example of four way set associative cache having four blocks in each set is shown in the following figure

 In this type of cache, the following steps are used to access the data from a cache:
1. The index of the address from the processor is used to access the set.
2. Then the comparators are used to compare all tags of the selected set with the incoming tag.
3. If a match is found, the corresponding location is accessed.
4. If no match is found, an access is made to the main memory.
 The tag address bits are always chosen to be the most significant bits of the full address, the block address bits are
the next significant bits and the word/byte address bits are the least significant bits.
 The number of comparators required in the set associative cache is given by the number of blocks in a set.
 The set can be selected quickly and all the blocks of the set can be read out simultaneously with the tags before
waiting for the tag comparisons to be made.
 After a tag has been identified, the corresponding block can be selected.
3. Fully associative mapping:
 In fully associative type of cache memory, each location in cache stores both memory address as well as data.
  Whenever a data is requested, the incoming memory address a simultaneously compared with all stored
addresses using the internal logic the associative memory.
 If a match is found, the corresponding is read out. Otherwise, the main memory is accessed if address is not
found in cache.
 This method is known as fully associative mapping approach because cached data is related to the main memory
by storing both memory address and data in the cache.
 In all organisations, data can be more than one word as shown in the following figure.

 A line constitutes four words, each word being 4 bytes. In such case, the least significant part of the address selects
the particular byte, the next part selects the word, and the remaining bits form the address.
 These address bits are compared to the address in the cache.
 The whole line can be transferred to and from the cache in one transaction if there are sufficient data paths
between the main memory and the cache.
 With only one data word path, the words of the line have to be transferred in separate transactions.
 The main advantage of fully associative mapped cache is that it provides greatest flexibility of holding combinations
of blocks in the cache and conflict for a given cache.

It suffers from certain disadvantages:

1. It is expensive method because of the high cost of associative memory.
2. It requires a replacement algorithm in order to select a block to be removed whenever cache miss occurs.
3. Such an algorithm must be implemented in hardware to maintain a high speed of operation.
The fully associative mechanism is usually employed by microprocessors with small internal cache.
Peripheral devices:
 A peripheral device is any external device connected to a computer that adds functionality but is not part of the
core computer system.
 These devices typically handle input, output, or both, and are also known as input-output (I/O) devices.
 The most common peripherals are keyboards, display units, and printers.
 Types of peripheral devices:
1. Input device
2. Output device
3. Input/output device
 An Input device sends data or instructions to the computer, such as a mouse, keyboard, image scanner, barcode
reader, light pen, microphone and webcam;
 An Output device provides output data from the computer, such as a computer monitor, projector, printer,
headphones and computer speaker;
 An Input/Output device performs both input and output functions, such as a computer data storage device
(including a disk drive, solid-state drive, USB flash drive, memory card and tape drive).
Characteristics of peripheral devices:
1. Enhancing Functionality:
 Peripherals add extra capabilities to a computer, allowing it to perform a wider range of tasks.
 They are not essential for basic operation but are crucial for many common and advanced uses.
2. Input/Output (I/O) Devices:
 Input Devices: Allow users to enter data and instructions into the computer (e.g., keyboard, mouse, microphone).
 Output Devices: Present processed data to the user (e.g., monitor, printer, speaker).
 Input/Output Devices: Can perform both functions, such as a USB drive or a modem.
3. Data Storage:
 Storage devices like hard drives, SSDs, and USB drives are peripherals that store data for later use.
 They provide long-term data storage and retrieval.
4. Communication:
 Peripherals like modems and network cards allow the computer to connect to networks and other devices.
 They facilitate data transfer between the computer and other systems.
5. Connecting Options:
 Peripherals connect to the computer through various interfaces, such as USB, Bluetooth, Wi-Fi, and HDMI.
 Each connection method offers different speeds, ranges, and compatibility levels.
6. Synchronization and Control:
 Peripheral devices often have different data transfer rates and operating modes compared to the CPU, requiring
synchronization mechanisms.
 The computer's operating system and drivers manage the communication and control of peripherals.
Advantage of Peripherals Devices:
 It is helpful for taking input very easily.
 It is also provided a specific output.
 It has a storage device for storing information or data.
 It also improves the efficiency of the system.
Input-Output Interface
 Input-output interface provides a method for transferring information between internal I/O to rage and external I/0
devices.
 The purpose of the communication link is to resolve the differences that exist between the central computer and each
peripheral
 The major differences are:
1. Peripherals are electromechanical and electromagnetic devices and their manner of operation is different from
the operation of the CPU and memory, which are electronic devices. Therefore, a conversion of signal values may
be required.
2. The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, and consequently, a
synchronization mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format in the CPU and memory.
4. The operating modes of peripherals are different from each other and each must be controlled so as not to
disturb the operation of other peripherals connected to the CPU.
 To resolve these differences, computer systems include special hardware components between the CPU and
peripherals to supervise and synchronize all input and output transfers.
 These components are called interface units because they interface between the processor bus and the peripheral
device.

 The I/O bus consists of data lines, address lines, and control lines.
 The magnetic disk, printer, and terminal are employed in practically any general-purpose computer.
 Each peripheral device has associated with it an interface unit. Each interface decodes the address and control received
from the I/O bus, interprets them for the peripheral, and provides signals for the peripheral controller.
 It also synchronizes the data flow and supervises the transfer between peripheral and processor.
 The I/O bus from the processor is attached to all peripheral interfaces.
 To communicate with a particular device, the processor places a device address on the address lines.
 Each interface attached to the I/0 bus contains an address decoder that monitors the address lines.
 When the interface detects its own address, it activates the path between the bus lines and the device that it controls.
 All peripherals whose address does not correspond to the address in the bus are disabled by their interface.

I/O Commands:
 An interface receives any of the following four commands:
 Control Command:
o A command control is given to activate the peripheral and to inform its next task.
o This control command depends on the peripheral, and each peripheral receives its sequence of control
commands, depending on its mode of operation.
 Status Command:
o A status command is used to test various status conditions in the interface and the peripheral.
o For example, the computer may wish to check the status of the peripheral before a transfer is initiated.
 Output data command:
o A data output command creates the interface counter to the command by sending data from the bus to
one of its registers.
 Input Data command:
o The data input command is opposite to the data output command.
o In data input, the interface gets an element of data from the peripheral and places it in its buffer.
I/O versus Memory Bus:
 There are three ways that computer buses can be used to communicate with memory and I/O:
1. Separate set of address, control and data bus to I/O and memory.
2. Have common bus (data and address) for I/O and memory but separate control lines. (Isolated I/O)
3. Have common bus (data, address, and control) for I/O and memory. (Memory Mapped I/O)
Isolated I/O:
 It has common bus (data and address) for I/O and memory but separate read and write control lines for I/O
 when CPU decode instruction then if data is for I/O then it places the address on the address line and set I/O read
or write control line on due to which data transfer occurs between CPU and I/O.
 The address for I/O here is called ports.
Memory Mapped I/O:
 The isolated I/O method isolates memory and addresses so that memory address values are not affected by
interface address assignment since each has its own address space.
 In Memory mapped I/O, the CPU uses same address space for both memory and I/O.
 The computers that employ only one set of read and write signals and do not distinguish between memory and
I/O addresses.
 The computer treats an interface register as being part of the memory system.
 The assigned addresses for interface registers cannot be used for memory words, which reduces the memory
address range available.
Example of I/O Interface:

 It consists of two data registers called ports, a control register, a status register, bus buffers, and timing and
control circuits. The interface communicates with the CPU through the data bus.
 The chip select and register select inputs determine the address assigned to the interface. The I/O read and
write are two control lines that specify an input or output, respectively.
 The four registers communicate directly with the I/O device attached to the interface.
 The I/O data to and from the device can be transferred into either port A or port B.
 The control register receives control information from the CPU. The bits in the status register are used for
status conditions and for recording errors that may occur during the data transfer.
Data Transfer:
 The internal operations in a digital system are synchronized by means of clock pulses supplied by a common pulse
generator. Clock pulses are applied to all registers within a unit and all data transfers among internal registers occur
simultaneously during the occurrence of a clock pulse.
 Two type of Data Transfer takes place between peripherals:
1. Synchronous data transfer
2. Asynchronous data transfer
Synchronous Data Transfer:
 If the registers in the interface share a common clock with the CPU registers, the transfer between the two units is
said to be synchronous.
Example: In a Master-Slave Flip Flop
 The master is designed to supply the data at a time when the slave is definitely ready for it. Usually, the master will
introduce sufficient delay to take into account the slow response of the slave, without any request from the slave.
 The master does not expect any acknowledgment signal from the slave when data is sent by the master to the slave.
Advantages:
1. The design procedure is easy. The master does not wait for any acknowledges signal from the slave, though the master
waits for a time equal to slave’s response time.
2. The slave does not generate an acknowledge signal, though it obeys the timing rules as per the protocol set by the master
or system designer.
Disadvantages:
1. If a slow speed unit connected to a common bus, it can degrade the overall rate of transfer in the system.
2. If the slave operates at a slow speed, the master will be idle for some time during data transfer and vice versa.
Asynchronous Data Transfer:
 The internal timing in each unit is independent from the other in that each uses its own private clock for internal
registers. In that case, the two units are said to be asynchronous to each other. This approach is widely used in
most computer systems.
 The Asynchronous data transfer is done by using two Method:
1. Strobe Control Method
2. Handshaking
1. Strobe control Method:
 The strobe control method of asynchronous data transfer employs a single control line to time each transfer.
 The strobe may be activated by either the source (source-initiated transfer) or the destination unit (Destination
initiated transfer).
 In A source-initiated transfer, the source unit first places the data on the data bus. After a brief delay to ensure that
the data settle to a steady value, the source activates the strobe pulse. The information on the data bus and the
strobe signal remains in the active state for a sufficient time period to allow the destination unit to receive the data.
 The source removes the data from the bus a brief period after it disables its strobe pulse.
 In Destination Initiated Strobe, data transfer initiated by the destination unit. In this case the destination unit activates
the strobe pulse, informing the source to provide the data.
 The source unit responds by placing the requested binary information on the data bus. The data must be valid and
remain in the bus long enough for the destination unit to accept it.
 The destination unit then disables the strobe. The source removes the data from the bus after a predetermined time
interval.

B. Handshaking Control:
 The disadvantage of the strobe method is that the source unit that initiates the transfer has no way of knowing
whether the destination unit has actually received the data item that was placed in the bus.
 Similarly, a destination unit that initiates the transfer has no way of knowing whether the source unit has actually
placed the data on the bus.
 The handshake method solves this problem by introducing a second control signal that provides a reply to the unit
that initiates the transfer.
 The basic principle of the two-wire handshaking method of data transfer is as follows.
1. One control line is in the same direction as the data flow in the bus from the source to the destination. It is
used by the source unit to inform the destination unit whether there are valid data in the bus.
2. The other control line is in the other direction from the destination to the source. It is used by the destination
unit to inform the source whether it can accept data.
 The two handshaking lines are data valid, which is generated by the source unit, and data accepted, generated by
the destination unit.
 In a Source initiated Transfer, the source unit initiates the transfer by placing the data on the bus and enabling its
data valid signal.
 The data accepted signal is activated by the destination unit after it accepts the data from the bus.
 The source unit then disables its data valid signal, which invalidates the data on the bus.
 The destination unit then disables its data accepted signal and the system goes into its initial state.
 In a Destination initiated Transfer, the source unit in this case does not place data on the bus until after it receives
the ready for data signal from the destination unit.
 Here Data accept line of Source initiated Transfer is replaced by ready for data signal.
Advantage of the Handshaking method:
1. The Handshaking scheme provides degree of flexibility and reliability because the successful completion of data
transfer relies on active participation by both units.
2. If any of one unit is faulty, the data transfer will not be completed. Such an error can be detected by means of a
Timeout mechanism which provides an alarm if the data is not completed within time
INTERRUPTS:
 An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate
attention.
 It alerts the processor to a high priority process requiring interruption of the current working process. In I/O devices
one of the bus control lines is dedicated for this purpose and is called the Interrupt Service Routine (ISR).
 An interrupt in computer architecture is a signal that requests the processor to suspend its current execution and
service the occurred interrupt.
 To service the interrupt the processor executes the corresponding interrupt service routine (ISR). After the execution
of the interrupt service routine, the processor resumes the execution of the suspended program.
Modes of Data Transfer:
 Data transfer between the central computer and I/O devices may be handled in a variety of modes.
 Some modes use the CPU as an intermediate path; others transfer the data directly to and from the memory unit.
 Data transfer to and from peripherals may be handled in one of three possible modes.
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
1. Programmed I/O:
 In the programmed I/0 method, the I/O device does not have direct access to memory.
 A transfer from an I/O device to memory requires the execution of several instructions by the CPU, including an
input instruction to transfer the data from the device to the CPU and a store instruction to transfer the data from
the CPU to memory.
Example of Programmed I/O:
 The device transfers bytes of data one at a time as they are available. When a byte of data is available, the device places
it in the I/O bus and enables its data valid line. The interface accepts the byte into its data register and enables the data
accepted line.
 The interface sets a bit in the status register that we will refer to as an F or "flag" bit. The device can now disable the
data valid line, but it will not transfer another byte until the data accepted line is disabled by the interface.
 A program is written for the computer to check the flag in the status register to determine if a byte has been placed in
the data register by the I/O device. This is done by reading the status register into a CPU register and checking the value
of the flag bit.
 If the flag is equal to 1, the CPU reads the data from the data register. The flag bit is then cleared to 0 by either the CPU
or the interface, depending on how the interface circuits are designed. Once the flag is cleared, the interface disables
the data accepted line and the device can then transfer the next data byte.
Disadvantages:
 In the programmed I/0 method, the CPU stays in a program loop until the I/0 unit indicates that it is ready for data
transfer. This is a time-consuming process since it keeps the processor busy needlessly. CPU continuously check status
register until status flag is set.

2. Interrupt-initiated I/O
 An alternative to the CPU constantly monitoring the flag is to let the interface inform the computer when it is ready to
transfer data. This mode of transfer uses the interrupt facility. While the CPU is running a program, it does not check
the flag.
 However, when the flag is set, the computer is momentarily interrupted from proceeding with the current program and
is informed of the fact that the flag has been set.
 The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack
and then control branches to a service routine that processes the required I/O transfer.
 There are two ways of choosing the branch address:
1. Vectored Interrupt
2. Non-vectored Interrupt
 In vectored interrupt the source that interrupt the CPU provides the branch information. This information is called
interrupt vectored.
 In non-vectored interrupt, the branch address is assigned to the fixed address in the memory.
[Link] memory access (DMA):
 Direct Memory Access (DMA) transfers the data between the memory and peripheral devices of the system,
without the participation of the processor. The unit that controls the activity of accessing memory directly is
called a DMA controller.
 The bus request (BR) input is used by the DMA controller to request the CPU to leave control of the buses. When
this input is active, the CPU terminates the execution of the current instruction and places the address bus, the
data bus, and the read and write lines into a high-impedance state.
 The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in the high-
impedance state.
 The DMA that originated the bus request can now take control of the buses to conduct memory transfers without
processor intervention

 When the DMA terminates the transfer, it disables the bus request line. The CPU disables the bus grant, takes
control of the buses, and returns to its normal operation.
 When the DMA takes control of the bus system, it communicates directly with the memory.
DMA Controller:

 The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O device. In
addition, it need address register, a word count register and a set of address lines.
 The Address register and address lines are used for direct communication with the memory.
 The data transfer may be done directly between the device and memory under control of the DMA.
 The DMA unit communicates with the CPU via the data bus and control lines.
 The DMA controller has three registers:
1. Address Register
2. Word Count Register
3. Control Register
 Address Register: - Address Register contains an address to specify the desired location in memory.
 Word Count Register: - WC holds the number of words to be transferred. The register is increase/decrease by one
after each word transfer and internally tested for zero.
 Control Register: - Control Register specifies the mode of transfer.
 The unit communicates with the CPU via the data bus and control lines. The registers in the DMA are selected by
the CPU through the address bus by enabling the DS (DMA select) and RS (Register select) inputs. The RD (read) and
WR (write) inputs are bidirectional.
 When the BG (Bus Grant) input is 0, the CPU can communicate with the DMA registers through the data bus to read
from or write to the DMA registers.
 When BG =1, the DMA can communicate directly with the memory by specifying an address in the address bus and
activating the RD or WR control.
Privileged Instructions:
 Privileged instructions are the instructions that are only executed in kernel mode.
 If a privileged instruction is attempted to get executed in user mode, that instruction will get ignored and treated

as an illegal instruction. It is trapped in the operating system by the hardware.

 It is the responsibility of the operating system to ensure that the Timer is set to interrupt before transferring control

to any user application. As a result, the operating system can regain control if the timer is interrupted.
 The operating system uses privileged instruction to ensure proper operation.
Examples of privileged instructions:
Some examples of privileged instructions include-
1. I/O instructions
2. Context switching
3. Clear memory
4. Set the timer of the CPU
5. Halt instructions
6. Interrupt management
7. Modify entries in the Device-status table
Non-Privileged Instructions:
 Non-Privileged instructions are the instructions that are only executed in user mode, which provides limited access
to system resources and ensures that processes cannot interfere with one another.
 Non-privileged instructions are those that can be executed by any process, including user-level processes.

 These instructions are typically used for performing computations, accessing user-level resources such as files and
memory, and managing process control.
 Non-privileged instructions are executed in user mode,
Examples of Non-privileged instructions:
1. Generate trap instruction
2. Reading system time
3. Reading status of processor
4. Sending the output to the printer
5. Performing arithmetic operations
Some key differences between privileged and non-privileged instructions:
1. Access to resources: Privileged instructions have direct access to system resources, while non-privileged instructions have
limited access.
2. Execution mode: Privileged instructions are executed in kernel mode, while non-privileged instructions are executed in
user mode.
3. Execution permissions: Privileged instructions require special permissions to execute, while nonprivileged instructions
do not.
4. Purpose: Privileged instructions are typically used for performing low-level system operations, while non-privileged
instructions are used for general-purpose computing.
5. Risks: Because privileged instructions have access to system resources, they pose a higher risk of causing system crashes
or security vulnerabilities if not used carefully. Non-privileged instructions are less risky in this regard.
Software Interrupts and Exceptions:
Interrupt:
 Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to
access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine),
which is a short program to instruct the microprocessor on how to handle the interrupt. The following image shows
the types of interrupts.

Hardware Interrupts:
 Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the
microprocessor. (i.e., INTR)
 Hardware interrupts were introduced as a way to avoid wasting the processor’s valuable time in polling loops and
waiting for external events.
 For example, when an I/O operation is completed such as reading some data into the computer from a tape drive.
o An interrupt is generated by a mouse when a button is clicked
o An interrupt is generated by a network card when data is received
o An interrupt is generated by a disk drive when a read or write operation is completed

Software Interrupts:
 Some instructions are inserted at the desired position into the program to create interrupts. These interrupt
instructions can be used to test the working of various interrupt handlers. It includes INT Interrupt instruction
with type number It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.
• TYPE 0 interrupt represents division by zero situation. (INT 0)
• TYPE 1 interrupt represents single-step execution during the debugging of a program. (INT 1)
• TYPE 2 interrupt represents non-maskable NMI interrupt. (INT 2)
• TYPE 3 interrupt represents break-point interrupt. (INT 3)
• TYPE 4 interrupt represents overflow interrupt. (INT 4)
 For example, output to the screen, execute file, etc.
o A system call to read or write data to a file
o A page fault exception
Exception:
 Exceptions occur during program execution and are so extraordinary that they cannot be handled by the program
itself. If you give the processor the command to divide a number by zero, for instance, it will give a divide-by-zero
exception, which will cause the computer to either stop the operation or display an error notice.

Difference Between Hardware Interrupt and Software Interrupt

Hardware Interrupt Software Interrupt

Hardware interrupt is an interrupt generated from Software interrupt is the interrupt that is generated by
an external device or hardware. any internal system of the computer.

It do not increment the program counter. It increment the program counter.

Hardware interrupt can be invoked with some

Software interrupt can be invoked with the help of INT
external device such as request to start an I/O or
instruction.
occurrence of a hardware failure.

It has lowest priority than software interrupts It has highest priority among all interrupts.

Hardware interrupt is triggered by external Software interrupt is triggered by software and

hardware and is considered one of the ways to considered one of the ways to communicate with
communicate with the outside peripherals, kernel or to trigger system calls, especially during error
hardware. or exception handling.

It is an asynchronous event. It is synchronous event.

Hardware interrupts can be classified into two

Software interrupts can be classified into two types
types they are: 1. Maskable Interrupt. 2. Non
they are: 1. Normal Interrupts. 2. Exception
Maskable Interrupt.

Keystroke depressions and mouse movements are

All system calls are examples of software interrupts
examples of hardware interrupt.
Programs and Processes:
The difference between Program and Process:
Program Process
Program contains a set of instructions designed to Process is an instance of an executing program
complete a specific task.
Program is a passive entity as it resides in the secondary Process is a active entity as it is created during execution
memory. and loaded into the main memory.
Program exists at a single place and continues to exist until Process exists for a limited span of time as it gets
it is deleted. terminated after the completion of task.
Program is a static entity. Process is a dynamic entity. Process has a high resource requirement, it needs
Program does not have any resource requirement; it only resources like CPU, memory address, I/O during its lifetime.
requires memory space for storing the instructions.
Program does not have any control block. Process has its own control block called Process Control
Block.
Program has two logical components: code and data. In addition to program data, a process also requires
additional information required for the management and
execution.