International Journal of Emerging Research in Computer Science

©IJERCS | Volume 1 | Issue 1 | December 2025 | ISSN: 3139-101X (Online)

Available online at: [Link]

Memory Management Techniques in Modern

Operating Systems: A Review
Shubham Sharma,1 Er. Abhay Dwivedi2
1
Department of Computer Application, Shri Lal Bahadur Shastri Degree College, Gonda
2
Assistant Professor, Department of Computer Application, Shri Lal Bahadur Shastri Degree College, Gonda

Received: 05 December 2025 | Accepted: 12 December 2025 | Published: 15 December 2025

ABSTRACT
Modern operating systems need to manage memory effectively for a range of applications. Memory
management deals with large, fast, and very cheap volatile storage; dealing with many programs, each with their own
memory needs and characteristics; operating on a shared medium; and doing all of the above efficiently across the
hardware/software boundary. In order to manage memory, operating systems must support abstraction and provide
security through separations; facilitate efficient allocation; ensure that memory can accommodate instruction
streams to exploit locality and minimize latency; and allocate based on actual usage to keep the memory hierarchy,
caches, and CPUs busy and reduce swapping or compression (Andrew Shidal, 2016). Memory management has
changed over time; originally systems were small enough to store directly in RAM, then abstracted to the notion of
segments (basic CM usage), and now layer on virtual memory (David Berger, 2002). In modern systems, locality is
more than an allocation problem; the CPU interacts with memory through caches that layer on top of the memory
hierarchy. Similarly, evolving programming languages and hardware abstractions create new dimensions of memory
management: global memory, multiple threads, off-chip memory and GPUs, and languages with their own
automated memory managers.
Keywords: Modern operating systems, memory, Paging.

1. Introduction
Classifier keystroke patterns exhibit distinct longitudinal and temporal features across users, indicating that
keystroke dynamics possess user-specific characteristics. Longitudinal features, including total keystroke duration,
total keystroke delay, and average keystroke-on-press duration, reflect individual typing habits that change
infrequently over time. Temporal features, such as pause time and time between strokes, also exhibit variability both
among individuals and over time, but these variations can be relatively stable for a few weeks to several months.

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A recent study has established a longitudinal pattern classification paradigm capable of successfully authenticating
users over long durations, up to 80 days. The paradigm builds user-specific longitudinal models and extracts
longitudinal features to minimize user uncertainty. An analytical model characterizes language-dependent temporal
variations analyzed through large text corpora. Real-world evaluations demonstrate different levels of user
admissibility, associating each user with a corresponding admissibility class, compatible with existing keystroke
dynamics models yet enabling secure access over extended periods. (David Berger, 2002)

2. History and Core Concepts of Memory Management

Modern operating systems incorporate sophisticated memory management techniques that draw on a long
tradition of research. A historic overview helps elucidate how memory management relates to other system functions
and sets the stage for a deeper examination of contemporary approaches. Since many concepts are discussed
throughout the review, the following overview presents an executive summary organized into four key themes: the
definition of memory management, basic techniques and performance indicators, an introduction to the two
leading models of memory management, and a comparison of static and dynamic management policies.
Memory management occurs at a level that is inherently lower than application services and resource management.
Memory management covers four major functions: allocation, protection, sharing, and cohesion. Allocation
determines which processes receive resources and how much; protection restricts processes from interfering with
each other; sharing controls how they cooperate; and cohesion specifies how components develop within any given
process. These functions apply to heterogeneous resources, including both memory and storage. Memory
management therefore assists the resource manager in covering these aspects.
One of the earliest and most widely discussed resource management models introduces two distinct levels of
abstraction: the entire system (usually referred to as the system) and individual programs (commonly termed jobs).
This distinction gives rise to the terms central memory, main memory, and primary memory for the system. Memory
management thus encompasses the complementary phenomena of resource allocation and the corresponding supply
of resources. Resource management permits multiple jobs to be accommodated concurrently, thereby increasing
throughput while greatly enhancing the overall efficiency, economy, and dependability of the operating system.
Resource managers that cater to multiple jobs must also address resource contention on the individual job level.
Only a small subset of resources requires such attention: those that a job cannot accommodate wholly within its
own job space. One universal resource of this type is memory (David Berger, 2002).

3. Contiguous Memory Allocation and Paging

Paging is an elegant solution for managing memory on systems with limited resources, supporting both
separation and commitment of addressing spaces. It maintains system stability even under extreme fragmentation,
maintaining performance via independence of paging unit size from physical frames and utilization of intelligent

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predictive caches. It imposes overall slowness but is still preferable to contiguous memory management (Douglas,
2011). Contiguous memory requires simultaneous observance of object, area, and compartment addressability
within permanent regions and subregions defined by length and base rules set at compartment establishment and
allocation.
The processing unit processes physical frames specified by compartments allocated from subregions. Each segment-
mounted process receives an uncompacted, exclusive address area defined by the length and base of a general
compartment chosen arbitrarily. Zero-length segments also serve renamings, frames or ears kept on the stack, and
file-name subsystems. Contiguous paging retains the requisite management structure and accumulates precise
information about confined processes, objects, and areas, aiding server productivity and discharge while permitting
multitasking and support for both sequentially packed area distributions and independent packing per configurable
unit formation per compartment and language.
The influence of paging, virtual memory, and other addressability techniques on program efficiency prompts
attempts to create page-access-free objects across multitasking objects and entire address spaces to eliminate needless
page-boundary crossings. Paging is grouped into a three-element array of consecutive zeros holding inner sequence
(length or boundary), outer sequence (initial base), and marking of pages already carried for partial completion or
emergency study before sealing into occupancy or permanent-bearing. Such abandonment enables reconstruction
if the program reverts to the compartment at a later point. Length precisely documents the upper boundary only in
such schemes supporting variations in frame size, length, and base.

3.1. Paging Architecture and Page Tables

Paging architecture uses page tables to map virtual addresses to physical memory. At the system level, each
process operates in its own virtual address space; a mapping associates each process’s global position in that space
with a physical address. Virtual memory extends paging to enable segments of memory that are not recently used to
be stored on secondary storage, freeing up RAM for other applications. This process is transparent to applications
and enhances security by isolating process memory (James Piehl, 2012). A page table maintains these mappings,
translating a virtual address into a physical one, and is memory resident. If a process attempts to reference a virtual
address not in its page table, a page fault occurs; the operating system must then read from disk and allocate a physical
address.
Page size is a trade-off between internal fragmentation, the number of page table entries, and I/O transfer times. To
relieve the page table overhead, alternative page-table structures have been developed. A hierarchical page table
reduces the average time for address translation and paging information transfer. Compared to linear page tables,
multi-level page tables have considerably fewer pages, as less than 120MB of virtual memory only requires seven
entries under a two-level page-table structure, despite a 4KB page-size assumption of 32-bit address space

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(Klimiankou, 2014). To further reduce the size of a linear page table, an inverted page table maintains one entry for
each physical frame, whereas conventional page tables contain an entry for every virtual page.
A page-table entry consists of a frame number and status bits. The status bits can indicate whether a frame is allocated
and whether it contains a valid mapping. A page table is required for each process; the operating system must
therefore take care to switch page-table addresses when changing processes. To maintain an efficient mapping ratio,
each address-space is limited. Contiguous memory allocation, partitioning, and paging are three approaches for
allocating memory to processes. Paging divides the physical memory into fixed-size blocks called frames and divides
the logical memory into blocks of the same size, referred to as pages. Thus, a process is allocated physical memory
when its pages are loaded into a number of frames. No external fragmentation occurs and no limit is imposed on the
logical address space of a process. However, paging must still be considered as it involves fragmentation, the size of
the pages, and the time consumed when mapping a logical address into a physical address. Examination of the paging
unit within a process at a certain point in time is required to handle the paging.

3.2. Segmentation and Segmentation with Paging

In segmented systems, a program’s logical address space is divided into segments of varying lengths. Each
segment has a number and an offset. A segment table maintains the starting physical address of each segment, and
its length. When a logical address is presented, the segment number is used to index into the segment table to obtain
the segment’s base address and length. To check for logical address violations, a two-register assignment is performed:
the base register is loaded with the segment’s starting address, while the limit register is loaded with its length. The
bounds-checking hardware then adds the base to the offset to obtain a physical address and checks that this value is
less than the limit.
Segment sizes are not fixed at load time. After the system starts, segments can be created and deleted based on user
demands. Segments are not always text, data, or stack. Rather, a user’s program can be organized to reflect a personal
programming style—only the user knows the appropriate segment style. Common segment types are *functions*,
which contain control transfer points for large programs; *modules*, which correspond to assistant programs for the
main control program; and *data* segments, which differ from one data structure to another (Klimiankou, 2014).
Segmentation can be combined with paging to yield the advantages of both. In this scheme, a program is subdivided
into a number of segments, with each segment made up of one or more pages (James Piehl, 2012). Address space
consideration continues to treat the collection of text, data, and stack segments as one contiguous sequence.
Consecutive page assignments to different segments are allowed. Such an organization allows the assignment of
program segments to be carried out independently of page allocation. Even a complete memory-bound program can
therefore be accepted in cases where there is still large enough but fragmented memory. The segmentation system
for Freon comprises segment descriptors stored in a segment descriptor table; each descriptor defines a segment, its

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attributes, and a pointer to an internal page table. The page descriptor table for each segment stores the
corresponding page descriptor, enabling small segments to be managed entirely in a memory buffer or shared buffer
either on LAN or application grounds.

4. Virtual Memory and Demand Paging

Memory management is an essential component of modern operating systems and encapsulates a range of
techniques that read and write data to and from memory. With the reduced cost and high-speed of random-access
memory (RAM), it has become feasible for processes to work within the confines of an address space that is larger
than the physical memory available on a machine, paving the way to virtual memory. In practice, any process
operating with local memory needs to store data periodically to free primary memory, and it is important to keep
the processor busy without allowing memory allocation requests to interfere negatively. On the other hand, locality
of reference manifests itself in both the code and the data that an application accesses at any point in time; since
addresses within code are likely to be accessed multiple times in sequence, one can cache commonly-accessed data
with relative confidence whether it is a particular instruction or data item that is often accessed (Teabe et al., 2020)
, (Gerber et al., 2019).
Virtual memory architecture relies on operating systems choosing dynamic page replacement policy schemes. Every
page request must therefore be either present or brought in from a storage device; those pages that cannot be
accommodation will need to be written out, resulting in page faults when inserting a page that is not resident
(Klimiankou, 2014). Although the TLB is partially configured, the time required to access local memory is
determined by the level of non-locality of the access being attempted. Each process in the system is assigned a priority
and is granted access to either local or external memory in relation to its normal memory allocation. As external
memory is specially handled within the paging segment, the locality of pages requested when the processor is
handling external data becomes minimal.
When a page-ins will occur for a certain process, the replacement algorithm becomes relevant in choosing which
page will be selected for a write-out. Since 2002, the Cache Replacement Algorithm has suggested that replacement
policies such as FIFO, LRU, or LFU as cache-replacement algorithms could be applied to pages shared,. In some
cases, different memory banks may accompany binary objects from which layouts may be reconstructed from the
application run, thus enabling locality to be retained at the file storage level even when the process itself cannot be
executed in the locality.

4.1. Page Replacement Algorithms

In any paging system, a page replacement algorithm determines which page in memory to swap out when a new page
must be loaded. Several page replacement algorithms have been developed, each varying in performance and
complexity. This section briefly examines five representative algorithms—First-In-First-Out (FIFO) (Rexha et al.,

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2015) , Least Recently Used (LRU), Least Frequently Used (LFU), CLOCK, and adaptive algorithms—and situates
these algorithms in the context of workload characteristics and memory pressure.
Page replacement algorithms are at the core of virtual memory management and are crucial to the performance of
computing systems. With limited memory available, the page replacement algorithm governs which pages to keep in
memory and which to swap to secondary storage. Recent years have seen considerable growth in workload diversity,
driven by trends such as cloud computing and the Internet of Things. The variation in the access pattern of different
workloads directly results in different page replacement needs; long-term locality still exists, but the best replacement
policy depends on the memory pressure imposed by the workload.

4.2. TLBs and the Memory Management Unit

Multi-level page tables exhibit reduced memory and TLB pressure, yet they necessitate multiple memory accesses to
locate the appropriate page table entry. In the GRASP architecture, a two-level page table is implemented to
accommodate varying page-table-entry sizes, allowing a single memory access at the top level and an immediate TLB
check (Kanellopoulos et al., 2023). A 64-bit virtual address is divided into four segments—32 bits for the page-table
index, 16 bits for the TLB index, and 16 bits for the page offset—enabling TLB lookups concurrently with the
second page-table access.
With each process possessing distinct page and segment tables, the page tables undergo administrative page-fault
processing. TLB entries consist of three fields: the page number, the segment number, and the frame number. Each
entry interacts with an administrative page-table structure to maintain coherence. When an entry is added or
refreshed, the corresponding administrative list undergoes a two-field update, specifying the segment number and a
unique entry number to inform the page-table structure.
The TLB contrasts with cache architectures by circumventing cache-coherency protocols, as the MMU administers
all page-table updates and full coherence is a system-level requirement. Page-table entries or segments containing the
same page number are not concurrently TLB-addable, thereby simplifying the administrative structures (Gerber et
al., 2019).

4.3. Copy-on-Write and Shared Pages

Memory management in operating systems seeks to efficiently support the execution of processes and applications,
balancing competing reguirements such as resource allocation, multi-process/module coordination, and security.
Copy-on-write (COW) and shared pages are widely used in both OS and persistent memory (PMEM) systems to
optimize performance and data sharing through low-cost MRs (Garg et al., 2023). These techniques enable single-
page sharing among multiple processes while postponing actual copying of data until a write occurs. In COW, the
operating system uses kernel-maintained reference counting to track the number of references to a shared page,
delaying the expensive copy operation until one of the processes attempts to write to the page.

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5. Cache-Aware Memory Management

Cache-aware memory management encompasses the optimization of memory systems for performance
enhancement. Current investigations extend to hybrid and persistent memories, and tiered memory systems.
Lightweight persistent-storage-aware programming models and holistic memory-management approaches target
large-scale data-processing workloads. Structure-aware page-management (Nimble) techniques and file systems
designed for Storage-Class Memory boost throughput. Cache-management solutions for many-core processors and
graphics-processing units—focused on latency reduction and bandwidth improvement—are also under scrutiny
(Kannan et al., 2020) ; (Teran, 2018).

6. Memory Allocation in Multithreaded and Multiprogramming

Environments
Memory management for modern multi-threaded systems has become one of the most important areas driving
operating systems. Multi-threaded systems try to improve the performance of programs by executing them
concurrently. Memory usage is another important element addressed, especially for real-time and embedded systems.
Memory management systems are expected to minimize memory usage and maximize memory re-use, while fast
execution speed should also be guaranteed. The thread memory model and automatic variable thread model are two
different methods available to achieve these goals (David Berger, 2002).
Multi-threaded programs can be executed as multi-process programs. Shared memory and message passing are the
two types of multi-process programs. These two types of multi-process programs are inherently compatible with
separate and shared allocation models, and some systems are designed with a clear distinction between shared and
separate allocation models. Large memory regions management is one of the first issues that should be addressed in
order to have a complete threading system. Keeping thread-local storage allocation (TLS) separate from action thread
heap is an approach that can be helpful, although its main usage is to separate thread-local allocator from general
allocator.

7. Garbage Collection in Managed Runtime Environments

Garbage collection constitutes a core component of many managed runtime environments. It can be seen as
automating memory management, a feature that has been widely adopted by mainstream programming languages.
Two families of algorithms have emerged: reference counting and tracing (E. Jones, 2007). The reference counting
approach is based on the idea that a memory object can be safely reclaimed the moment its reference count reaches
zero. The tracing approach, in contrast, relies on the detection of “reachable” objects. An object is deemed
unreachable if it is not accessible directly or through a sequence of pointers starting from a set of “root” pointers,
which are logical, fixed locations such as global variables or the variables stored on the call stack. Support for tracing

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garbage collection has integrated itself into mainstream languages due to the complexity involved in implementing
reference counting without unknown delays.
Garbage collection techniques differ significantly in aspects such as maximum pause times, support for concurrent
collection, application of generational or non-generational models, and estimation of the amount of memory reuse
after collection (Andrew Shidal, 2016). Tracing traces either “live” objects during the “mark” phase or “dead” objects
during the “sweep” phase. Generational schemes seek to improve tracing performance through the observation that
most objects tend to have a short lifetime.
The overhead introduced by garbage collection appears trivially low for many applications due to the sizes of datasets
involved, which increases the difficulty of estimating the quality of garbage collection in relation to that overhead.
Cache locality constraints and their influence on garbage collection performance have been researched extensively.
Callback functions known as “finalizers” are also intermittently associated with language objects to implement
coarse, single-point, yet non-deterministic resource reclamation.

8. Memory Management in Modern Hardware Architectures

Modern processor architectures present new challenges for memory management systems. In traditional memory
hierarchies, processors could communicate with a single memory system containing multiple memory banks. With
the introduction of non-uniform memory access (NUMA) architectures, memory-managed systems must allocate
pages near the processor that owns the data to ensure access remains efficient. Because of this complexity, it becomes
essential to consider the processor organization and cache coherence hardware when designing a memory-
management system.
Graphics processing units (GPUs) epitomize complex memory-management systems. The increased performance of
GPUs relies on stacking more processor cores on the die, allowing specialised cores for different tasks to co-exist.
Memory-management techniques for GPUs generally depend on the language abstraction. Even proprietary
languages add or restrict specific syntactic constructs. As a consequence, the only universal method of comparison
for GPU memory management involves examining the memory space model.
Decoupled from conventional memory-management methods, even the experience gained from designing
embedded systems and management systems for complex memory architectures still does not apply, as they rely
heavily on dynamic programming techniques and the operating environment (James Piehl, 2012).

9. Security and Reliability Considerations in Memory Management

Memory management security and reliability now include addressing battery-backed NV memory, maintaining low
latency and balancing DRAM and NVM, and managing large nonvolatile memory and non-uniform memory
architecture with high reliability. Virtual memory has become a standard baseline but exposes high-level data
metadata and influences the trade-offs for pointers, which can lead to memory corruption. The evolution of hybrid

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memory management must consider platform diversity. Memory corruption exploits continue to evolve with ever
more powerful tools now rendering basic strategies highly inadequate. Memory corruption is obsolete as a research
topic yet basic techniques showed up as foundational elements throughout modern operating systems (Garg et al.,
2023).

10. Trends and Emerging Techniques in Memory Management

Demand for efficient and robust memory management continues to grow, driven by virtualized hardware
architectures, extensive process or application ensemble operating system designs, and pervasive high-level
programming languages. Techniques that offer improved performance, greater reliability, or reduced energy
consumption continue to emerge. Many modern operating systems also encapsulate diverse services or products that
fulfil different compatibility, performance, robustness, or energy-consumption requirements. Memory managers
can thus evolve independently of a particular programming environment; they provide generic mapping, allocation,
and garbage-collection features to diverse application environments.
Virtualization technology enables multiple operating-system instances to operate directly on a platform; the
hypervisor maps memory pages between guest and host operating systems. Emerging software initiatives and new
programming languages emphasise high-level programming abstractions and model-driven developments, devoid of
memory-management concerns. For instance, the .NET framework, Java, and Android have gained wide acceptance
among various programming communities. In the distributed-model computing environment, real-time
compilation technology allows web applications to run across multiple operating-system instances. Emerging
programming languages such as Scala, Python, JavaScript, and Erlang continue to gain traction, displaying
characteristics suitable for the distributed-computing model. Such extensive operating-system or application
ensembles remain popular.
The rapid increase in video, graphic, and virtual-reality information across computer, mobile, and
telecommunication devices places severe pressure on memory-access bandwidth. Consequently, the development of
new memory systems capable of supporting such devices occupies a position of paramount importance. Retaining
state-of-the-art compression, encryption, and partition features, the new-architecture memory manager has been
designed to fulfil such requirements (David Berger, 2002).

11. Evaluation Metrics and Methodologies

Evaluating memory management techniques is essential for identifying configuration trade-offs and designing new
algorithms. The broader area of operating system research may employ various benchmarks, tools, or methodologies,
yet many studies prioritize memory performance, leading to an emphasis on metrics and methods tailored to
memory management evaluation. Consequently, academic and industry approaches converge on broadly similar
workloads, benchmarks, and methodologies. A comprehensive overview and analysis of evaluation metrics for

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memory management, particularly under the constraints imposed by contemporary operating systems and
hardware, underscores the commonalities among a range of selections (Kannan et al., 2020).
Various workloads characterize operating systems as inherently multitasking and multiprogramming,
accommodating multiple concurrent applications that submit memory allocation requests. Resource contention is
unavoidable under memory pressure, and changing the total pool of addressable memory within the confines of a
single physical campus similarly affects memory management policies. Experiments must therefore include a diverse
assortment of concurrent applications, isolates individual applications from other processes, or utilize synthetic
workloads aggregating relevant characteristics of operating-system-managed memory to identify low-level
performance details (Garg et al., 2023). All approaches require compatible synthetic workloads amenable to easy
modification and a detailed workload specification.

12. Case Studies and Comparative Analyses

Two broadly representative systems, [Link] and KLOC, have been used as case studies to illustrate design
constraints and trade-offs in different microkernel architectures. KLOC is employed for performance evaluation.
KLOC is a microkernel supporting kernel object management in a tiered memory environment while maintaining
compatibility with a variety of mobile workloads. It provides an efficient, predictable platform for numerous real-
time applications, such as the telecommunications sector, that require attention to safety and timing properties
among the miscellaneous constraints and challenges. KLOC was built as an experimental kernel built to deliver
better performance and maintain more critical properties than those of [Link].
Performance evaluations have been performed against an L4 microkernel version. Results consistently indicated that
KLOC outperformed [Link] in workloads with realistic data and usage patterns by 15%–86%. The evaluations
have confirmed that incompatibilities between design requirements, the operating principles of tiered memory
systems, and microkernel architecture hinder [Link] from better serving mobile workloads. Each design
architecture should be studied alongside real design constraints and workload characteristics before system designs
are finalized.

13. Conclusion
Memory management in contemporary operating systems has made remarkable progress, yet it is still susceptible to
significant challenges. New hardware architectures, runtime platforms, and programming paradigms have emerged.
Consequently, systems must adapt to new types of workloads in computing environments that exhibit further
diversity in user needs. The extensive range of trends and techniques, as well as the breadth of existing scholarly
material, invites collaboration among the research community as it seeks to identify, evaluate, innovate, and develop
techniques to tackle these persistent issues. To initiate such efforts, the critical observation of existing techniques in

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contemporary memory management provides a foundational understanding of the present state of the art and
highlights key areas where the need for improvements remain evident (David Berger, 2002).

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Cite this Article:

Shubham Sharma, Er. Abhay Dwivedi, “Memory Management Techniques in Modern Operating Systems: A Review”, International
Journal of Emerging Research in Computer Science, Volume 1, Issue 1, pp. 21-31, December 2025.
Journal URL: [Link]

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