Very Large Scale Integration
VLSI
Process of integrating billions of transistors onto a semiconductor
chip to create complex integrated circuits (ICs)
Transistor for VLSI
Transistor is the fundamental physical device used to build VLSI
circuits
Metal Oxide Semiconductor
Bipolar Junction Transistor Field Effect Transistor
BJT MOSFET
Reliability Scalability
Transistor
Speed Area
Power
Concumption
Transistor as Switch
• IC can be Analog or Digital
• We Cannot make logic gates with voltage/current source, RLC
components
• Need a “switch” something where a (small) signal can control the
flow of another signal
Introduction Slide 4
Game
Design a circuit to turn on an LED when the input voltage is VIN>2V
MOSFET
Metal-Oxide-Semiconductor Field-Effect Transistor - voltage-controlled
current semiconductor device for switching and amplifying signals in
electronic circuits
4 Terminals
Gate (G), Drain (D), Source (S), Body (B)
Depelation - Enhancement Mosfet
Current flow from source to drain
External voltage create a layer of carrier in the semiconductor body known as channel
Carrier is opposte of gate voltage
Channel determine N-Type / P-Type MOSFET (Enhancement)
Monolithic integration of a large number of functions on a single chip
provides
*Less area/volume and therefore, compactness
*Less power consumption
*Less testing requirements at system level
* Higher reliability, mainly due to improved on-chip interconnects
* Higher speed, due to significantly reduced interconnection length
* Significant cost savings
Technology
MOSCAP -MOS Capacitor
Coulomb's Law and Dielectrics - a type of voltage applied on one layer of
dielectric, other layer of dielectric equal and opposite chanrge creates
MOS have Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
*Gate and body are conductors
*SiO2 (oxide) is an insulator Called metal – oxide – semiconductor (MOS) capacitor
Game Tool
Identify Symbol and Count
NMOS = ?
PMOS = ?
Identify Symbol and Count
NMOS = ?
PMOS = ?
Identify Symbol and Count
NMOS = ?
PMOS = ?
N Channel MOS Capacitor
MOS structure consists of three layers: The metal gate electrode, insulating oxide (SiO2) layer,
and the p-type bulk semiconductor (Si), called the substrate
MOS structure forms a capacitor with the gate and the substrate acting as the two
terminals (plates) and the oxide layer as the dielectric (10-50nm)
Energy band diagrams of metal, oxide and semiconductor layers in a MOS
work-function difference between the metal and the semiconductor voltage drop.
Part of this built-in voltage drop occurs across the insulating oxide layer.
The rest of the voltage drop (potential difference) occurs at the silicon surface next to the
silicon-oxide interface
MOS System under External Bias
Voltage difference forces the energy
bands of silicon to bend in this region.
MOS With Bias
Accumulation
negative voltage VG is applied to the gate electrode,
the holes in the p-type substrate are attracted to
the semiconductor-oxide interface.
The majority carrier concentration near the surface
becomes larger than the equilibrium hole
concentration in the substrate
called carrier accumulation on the surface
Deplation
small positive gate bias VG is applied to the gate
electrode.
The positive surface potential causes the energy bands
to bend downward near the surface
The majority carriers holes in the substrate, will be
repelled back.
Holes will leave negatively charged fixed acceptor ions
behind.
depletion region is created near the surface.
Inversion
High gate voltage bend downward the energy
bands
substrate semiconductor in this region
becomes n-type.
Positive gate potential attracts additional
minority carriers (electrons) from the bulk
substrate to the surface
The n-type region created near the surface by
the positive gate bias is called the inversion layer,
and this condition is called surface inversion
N-MOSFET Operation
n-channel enhancement-mode MOSFET
[Link]
Operation of MOS Transistor
structure of an n-channel MOSFET is four-terminal device consists of a p-type
substrate, in which two n+ diffusion regions, drain and source.
The surface of the substrate region between the drain and the source is covered with
a thin oxide layer and the metal (or polysilicon) gate is deposited on top
of this gate dielectric.
The two n+regions will be the current-conducting terminals of this device.
MOSFET a voltage controlled current device
Ids = f(Vgs,Vds)
channel will eventually be
formed through applied gate
voltage
The distance between the drain
and source diffusion regions is
the channel length L
lateral extent of the channel is
the channel width W
nMOS Cutoff
• 0 < VGS < Vth the gated region between the source and the
drain is depleted
• no carrier flow can be observed in the channel
• No channel Vgs = 0
g
Vgd
+ +
• Ids ≈ 0 - -
s d
n+ n+
p-type body
b
Threshold voltage --minimum difference in gate-to-source voltage needed for the
formation of channel in a MOS device.
nMOS Linear/Ohmic/Triode
• VGS > VT0, week channel appears
• At VDS = 0
Small Current flows from d to s
• Ids increases with Vds
• Current flow linearly
Transfer Characteristics Output Characteristics
nMOS Saturation
Vgs > Vt
Vgd < Vt
VDS > VDSAT, a depleted surface region at drain + g
+
- -
depletion region grows toward the source s d Ids
Effective channel length is reduced as the n+ n+
Vds > Vgs-Vt
inversion layer near the drain vanishes, p-type body
b
Electrons arriving from the source to the channel-end are
injected into the drain-depletion region and are
accelerated toward the drain in this high electric field
usually reaching the drift velocity limit.
VDS = VDsat Pinch Off occurs (Channel at drain zero)
• Channel pinches off
• Ids independent of Vds
• current saturates constant current
MOS Terminal Voltages
Vg
• Mode of operation depends on Vg, Vd, Vs
+
– Vgs = Vg – Vs +
Vgs Vgd
- -
– Vgd = Vg – Vd
Vs Vd
– Vds = Vd – Vs = Vgs - Vgd -
Vds +
• Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds 0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
– Cutoff
– Linear
– Saturation
MOS Current Equation
(Linear)
IDS is due to the electrons in the channel region traveling from the source to the drain under
the influence of electric field
Let Q(y) be the total mobile electron charge in the surface inversion layer.
This charge is function of the gate-to-source voltage VGS and of the channel voltage Vc(y)
as follows: Q(Y) =-Cox[VGS - Vc(Y)- VT0]
Differential channel Resistance
Boundary
Condition
MOS Current Equation
(Saturation)
ID does not show much variation as a function of the drain voltage.
VDS beyond the saturation boundary, ID peak value reached for VDS = VDSAT
MOSFET Current Equation
Transconductance (Gm)
Saturation mode
change in drain current(ID) with respect to the
corresponding change in gate voltage (VGS)
Body Bias Effect
Body terminal acts as 2nd gate
Potential on body terminal reduces the threshold voltage of MOSFET
Reverse substrate bias (VSB > 0)
Increases the depletion region width Forward substrate bias (VSB < 0)
Requires a higher (Vgs) to make channel Decreases the depletion region width
Increases threshold voltage. Requires low (Vgs) to make channel
Decreases threshold voltage.
Threshold voltage with body effect
Substrate bias effect
Threshold Voltage
4 Component of Vth are
Work function difference between the gate and the channel
Gate voltage component to change the surface potential
Gate voltage component to offset the depletion region charge
Voltage component to offset the fixed charges in the gate oxide and silicon-oxide
interface.