INDEX

Abstract 4
Chapter 1 Introduction 5
1.1 Overview 5
1.2 Motivation 7
1.3 FIR Filter Fundamentals 8
1.4 FPGA in DSP Applications 9
1.5 Vivado Design Suite 9
1.6 Objectives 10
1.7 Scope of the Project 10
1.8 Organization of the Report 10
Chapter -2 Literature Survey 11
2.1 Introduction 11
2.2 FIR Filter Architectures and Structures 11
2.3 FPGA Implementation Techniques and Optimization Strategies 12
2.4 FPGA Platforms for FIR Filter Design 13
2.5 Performance Evaluation and Comparison of FIR Filter Implementations 14
2.6 Optimization Techniques for FIR Filters in FPGA 15
Chapter 3 Digital Filters: Methods and Techniques 19
3.1 Digital Filter Concept 19
3.2 The Fundamental Building Blocks 19
3.3 Overview of Approximation Techniques 20
3.4 Common Types of Digital Filters 22
3.5 Digital Filter Design Methods 22
3.6 Implementation Considerations 24
Chapter 4- Design Methodology 26
4.1 Introduction 26
4.2 Field Programmable Gate Array 26
4.2.1 Types of FPGA 26
4.2.2 Design Flow of FPGA 27
4.2.3 Architecture of FPGA 28
4.2.4 Advantages of FPGA 29
4.3 Very High Speed Integrated Circuits Hardware Description Language 29
4.3.1 Description of VHDL/Verilog 30
4.3.2 Advantages of VHDL/Verilog 30
4.4 Design specifications 31
4.4.1. Specification Definition 31
4.1.2. Mathematical Model of the FIR Filter 32
4.1.3. Design Considerations 33
4.1.4. HDL Implementation (VHDL/Verilog) 34
4.1.5. Toolchain Setup (Vivado) 34
4.1.6. Simulation and Verification 35

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 4.1.7. Hardware Implementation and Testing 35
4.1.8. Performance Analysis and Optimization 36
4.2 Algorithm 36
4.2.1. Initialize Filter Specifications 36
4.2.2. Compute Filter Coefficients 37
4.2.3. Design FPGA-Friendly Architecture 37
4.2.4. Implement FIR Filter in HDL (VHDL/Verilog) 37
4.2.5. Develop Test bench for Verification 37
4.2.6. Implement in Vivado 38
4.2.7. Program the FPGA and Test Hardware 38
4.2.8. Performance Analysis and Optimization 38
4.2.9. Final Validation 38
4.3 Flowchart for proposed model 39
4.4 Implementation of proposed model 40
4.4.1 Design Specification 40
4.4.2. Filter Coefficient Generation (MATLAB) 40
4.4.3. FIR Filter Verilog Code(Sample code) 41
4.4.4. Vivado Project Setup 41
4.4. 5. Verilog Test bench 42
4.4. 6. Synthesis and Implementation 42
Chapter 5 - Results and Discussions 43
5.1 Propose Model (HIGH PASS FILTER) 43
5.1.1 RTL Schematic for Propose Model (HIGH PASS FILTER) 43
5.1.2 Top Level model: 45
5.1. 3 RTL data path 49
5.1.4 Top-level RTL netlist 50
5.1.6 Output waveform of proposed model (HIGH PASS FILTER) 53
5.1.7 Xilinx Ultrascale+ Integrated Block for PCI Express 54
5.2 Propose Model (LOW PASS FILTER) 55
5.2.1 RTL Diagram: 55
5.2.2 TOP LEVEL MODEL 58
5.2.3 OUTPUT WAVE FORM (LOWPASS Filter) 59
5.2.4 Power Estimation 62
Conclusion 66
Applications 67
Future Scope 68
References 69

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 List of Figures

Figure 1 A/D-H(z)-D/A system 20

Figure 2 Reprogrammable (SRAM- Based 27
Figure 3 One-time Programmable (OTP) 27
Figure 4 The design flow of PFGA device. 28
Figure 5 FPGA Logic Block 29
Figure 6 Flow chart for proposed system 39
Figure 7 RTL Schematic diagram 43
Figure 8 Top Level model 45
Figure 9 Part -1 of Top Level model 45
Figure 10 Part -2 of Top Level model 45
Figure 11 Part -3 of Top Level model 45
Figure 12 Part -4 of Top Level model 45
Figure 13 Part -5 of Top Level model 46
Figure 14 (Register Transfer Level) schematic 48
Figure 15 RTL data path 49
Figure 16 Block diagram 51
Figure 17 RTL schematic view of the IBUF 52
Figure 18 Power Estimation Summary report 53
Figure 19 Output waveform of proposed model 54
Figure 20 high-level block diagram featuring a Xilinx Ultrascale+ Integrated Block
configured for PCI Express (PCIe) Gen4 55
Figure 21 RTL View for propose model ( Low Pass Filter) 56
Figure 22 Part- 1 RTL View for propose model 57
Figure 23 Part -2 RTL View for propose model 57
Figure 24 Part -3 RTL View for propose model 57
Figure 25 Part - 4 RTL View for propose model 57
Figure 26 Part -5 RTL View for propose model 57
Figure 27 Part -6 RTL View for propose model 58
Figure 28 Part -7 RTL View for propose model 58
Figure 29 Top Level Model 58
Figure 30 Output wave form in Behaviour Simulation 60
Figure 31 Output wave form in Post Synthesis Timing Simulation 60
Figure 32 Output wave form in Post Synthesis Function Simulation 61
Figure 33 Power estimation 63

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 Abstract

The swift expansion of digital signal processing (DSP) applications has

underscored the necessity for high-performance and real-time processing
systems. Finite Impulse Response (FIR) filters are essential in digital signal
processing (DSP), maintaining signal integrity by eliminating noise and
contouring the frequency response. Conventional microprocessor-based systems
frequently inadequately meet the demands for ultra-high-speed performance and
predictable latency. Field Programmable Gate Arrays (FPGAs) serve as an
advantageous platform for FIR filter implementation owing to their intrinsic
parallelism, reconfigurability, and capability for high-speed signal processing.

This project centers on the design, synthesis, and implementation of a high-

speed FIR filter utilizing the Vivado Design Suite, aimed at Xilinx's Artix-7
FPGA platform. The main goal is to create a low-latency, pipelined, and
resource-efficient FIR filter with Verilog HDL and evaluate its performance
regarding timing, area, and power consumption. An 8-tap low-pass FIR filter is
constructed using predetermined symmetric coefficients to provide a linear
phase response. The implementation utilizes a register-based pipeline
architecture to improve throughput and reduce critical path delays, enabling the
system to function at frequencies over 100 MHz

The simulation findings corroborate the filter's correctness, while synthesis and
implementation reports affirm its high-speed performance, achieving a clock
period of 10 ns, which corresponds to a maximum operating frequency of 100
MHz. The hardware FIR filter on FPGA exhibits markedly decreased latency
and stable throughput within real-time parameters.

This project illustrates the feasibility and benefits of implementing FIR filters on
FPGAs using Vivado and Verilog for high-performance DSP applications.
Prospective improvements may encompass lengthening the filter, facilitating
dynamic coefficient modifications, incorporating adaptive filtering

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functionalities, or investigating deployment on more sophisticated FPGA
families.

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 Chapter 1: Introduction

1.1 Overview

In the digital era, signal processing plays an indispensable role in a multitude of

applications, including wireless communication, audio and video processing,
image enhancement, biomedical instrumentation, and radar systems. At the heart
of these systems are digital filters, particularly Finite Impulse Response (FIR)
filters, which are essential for modifying or enhancing certain aspects of signals
such as frequency characteristics, amplitude, and phase response. FIR filters are
widely recognized for their inherent stability and linear phase characteristics,
which are crucial in applications requiring phase fidelity [1].

Designing high-speed Finite Impulse Response (FIR) filters on Field-

Programmable Gate Arrays (FPGAs) using Vivado is a critical endeavor in
modern digital signal processing (DSP). FIR filters are essential components in
various applications, including telecommunications, audio processing, and
biomedical signal analysis, due to their inherent stability and linear phase
characteristics. The advent of FPGAs has revolutionized the implementation of
these filters, offering unparalleled flexibility and performance.

As signal processing systems evolve to accommodate real-time and high-

throughput requirements, conventional software-based implementations on
Digital Signal Processors (DSPs) or micro-controllers often fail to meet the
stringent timing and latency constraints. To bridge this performance gap,
hardware-based solutions using Field Programmable Gate Arrays (FPGAs) have
become a preferred alternative. FPGAs offer massive parallelism, deterministic
performance, low latency, and high flexibility due to their reconfigurability.
Moreover, with the advancements in FPGA architectures such as Xilinx Artix-7,
Kintex, and Virtex UltraScale+, it is now feasible to implement highly efficient
digital signal processing systems that rival Application Specific Integrated
Circuits (ASICs) in performance while maintaining programmability [2].

The implementation of high-speed FIR filters on FPGAs involves several

considerations, including the choice of filter architecture, coefficient

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quantization, and resource utilization. Various architectures, such as direct-form,
transposed-form, and polyphase structures, offer different advantages in terms of
speed and resource efficiency. For instance, the transposed-form architecture is
known for its suitability in high-speed applications due to its shorter critical
path.

Digital signal processing (DSP) has become increasingly central in modern

technological domains, spanning telecommunications, multimedia, biomedical
systems, and control applications. At the heart of many DSP tasks lies the finite
impulse response (FIR) filter, valued for its stability and linear-phase response.
In real-time systems where speed and efficiency are paramount, traditional
software-based FIR filters often fall short of the required performance
thresholds. To address these constraints, hardware implementation, particularly
on Field Programmable Gate Arrays (FPGAs), has emerged as a compelling
alternative.

FPGAs offer high-speed parallelism, low latency, and reconfigurability, making

them suitable for high-performance DSP tasks. Unlike Application Specific
Integrated Circuits (ASICs), FPGAs enable flexible design changes and
prototyping without high non-recurring engineering costs. With advances in
FPGA architectures and high-level synthesis (HLS) tools, the potential for
deploying real-time, high-throughput FIR filters has increased significantly.
Design tools like Xilinx Vivado now support optimization techniques such as
pipelining, parallelism, and dedicated DSP slices, which are crucial for
implementing efficient filters.

Vivado's FIR Compiler IP core provides a robust solution for implementing FIR
filters, supporting features like pipelining, coefficient reloading, and multi-
channel processing. It allows designers to specify filter parameters and
automatically generates optimized hardware descriptions, significantly reducing
development time.

Recent research has demonstrated the effectiveness of FPGA-based FIR filter

implementations. For example, a study achieved a sampling rate of up to 1.2
GHz using a parallel transposed FIR filter on a Xilinx Virtex-6 FPGA. Another

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approach utilized a microprogrammed controller for a sequential 7-tap FIR filter,
highlighting the versatility of FPGA implementations.

This project aims to design and synthesize a high-speed FIR filter using Verilog
Hardware Description Language (HDL) and the Vivado Design Suite targeting
an FPGA platform. The motivation behind this work is to leverage FPGA’s
parallel architecture and DSP slices to achieve high-speed signal filtering,
optimize area usage, and ensure scalability for future enhancements.

Vivado Design Suite, developed by Xilinx (now part of AMD), is a

comprehensive toolset that facilitates the design, synthesis, and implementation
of digital circuits on FPGAs. Introduced in 2012, Vivado superseded the older
ISE Design Suite, providing enhanced capabilities such as high-level synthesis
(HLS), system-level integration, and advanced simulation features. These
features are particularly beneficial for designing complex FIR filters, as they
allow for efficient exploration of design trade-offs and optimization of
performance metrics.

1.2 Motivation

Despite the advantages offered by FPGAs, the design and synthesis of high-
speed FIR filters still pose multiple challenges. These include managing the
trade-offs between speed, power, area, and precision. Additionally, selecting an
appropriate filter structure be it direct form, transposed form, systolic
architecture, or distributed arithmetic can greatly affect the overall performance.
The lack of a unified framework for comparing different design approaches
complicates the task further. Thus, a comprehensive analysis of state-of-the-art
methods and a practical implementation using Vivado are essential to bridge the
performance-efficiency gap.

The demand for real-time signal processing continues to grow in modern

applications such as 5G communication, real-time image enhancement, audio
equalization, and medical diagnosis systems. FIR filters are vital components in
these systems, responsible for removing unwanted frequency components,
reducing noise, and shaping the desired signal spectrum [3]. However, as the

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required data throughput increases, achieving real-time performance using
sequential processors becomes challenging due to limitations in clock speed and
sequential instruction execution.

FPGAs have emerged as an effective solution for implementing high-

performance FIR filters owing to their ability to exploit spatial and temporal
parallelism. In contrast to general-purpose processors, FPGAs offer dedicated
logic blocks, configurable interconnects, and hard-core DSP blocks that are
optimized for MAC operations, which are the building blocks of FIR filters. The
Vivado Design Suite by Xilinx provides a powerful toolchain for designing,
simulating, and implementing complex hardware systems on FPGAs [4]. The
motivation of this work lies in developing an FIR filter with optimized
performance in terms of speed, latency, and resource utilization, making it
suitable for deployment in real-time DSP systems.

1.3 FIR Filter Fundamentals

A Finite Impulse Response (FIR) filter is a type of digital filter whose impulse
response settles to zero in finite time. Unlike Infinite Impulse Response (IIR)
filters, FIR filters do not use feedback; hence, they are inherently stable. The
output of an FIR filter is a weighted sum of current and past input values,
defined mathematically as:

Where:

y[n] is the filter output,

x[n] is the input signal,

h[i] represents the filter coefficients,

N is the filter order.

The primary design parameters of an FIR filter include filter order, type (low-
pass, high-pass, band-pass, band-stop), and window function used in coefficient

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calculation. FIR filters are particularly advantageous when a linear phase
response is required, which is critical in applications like data communication
and audio processing [5].

1.4 FPGA in DSP Applications

FPGAs are semiconductor devices that contain programmable logic blocks and
interconnects that allow the designer to configure hardware behavior post-
manufacturing. In DSP applications, FPGAs offer several advantages:

 Parallelism: Multiple operations can be executed in parallel.

 Low Latency: Dedicated hardware paths minimize response times.
 Reconfigurability: Hardware functionality can be modified without
changing physical hardware.
 Power Efficiency: Custom data paths reduce unnecessary switching.

FPGAs like the Xilinx Artix-7 family include built-in Digital Signal Processing
(DSP) slices, which contain pre-configured multipliers, adders, and
accumulators. These resources are especially suited for implementing FIR filters
as they allow efficient realization of the multiply-and-accumulate operations in
the filter equation [6].

1.5 Vivado Design Suite

Vivado Design Suite is Xilinx's state-of-the-art FPGA development

environment, offering integrated synthesis, simulation, implementation, and
analysis tools. Vivado supports both Register Transfer Level (RTL) design using
Verilog or VHDL and High-Level Synthesis (HLS) using C/C++. For this
project, Verilog HDL is used for a low-level, fine-tuned implementation.

Vivado provides:

 RTL analysis and debugging tools.

 Integrated waveform viewer.
 IP Integrator for block-based design.
 Built-in support for simulation and timing analysis.

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Vivado also facilitates the use of IP cores, including FIR filter generators, but in
this project, a custom Verilog implementation is chosen to provide full control
over the architecture and performance optimization [7].

1.6 Objectives

This project sets out with the following key objectives:

 Design a parameterized FIR filter using Verilog HDL.

 Implement the FIR filter on the Xilinx Artix-7 FPGA platform.
 Use pipelining and parallelism to enhance throughput and speed.
 Evaluate resource usage including LUTs, FFs, and DSP slices.
 Perform timing analysis to validate high-speed performance.
 Validate functionality via simulation and FPGA test bench.

1.7 Scope of the Project

This project is limited to the design and synthesis of an FIR filter for FPGA
using Verilog and Vivado. While the design is scalable, dynamic coefficient
updating, floating-point arithmetic, and adaptive filtering are outside the current
scope. Future work may explore:

 Adaptive FIR filters (LMS or RLS algorithms).

 Integration with high-speed ADCs/DACs.
 Expansion to multi-channel or MIMO systems.

1.8 Organization of the Report

The rest of this report is organized as follows:

Chapter 2 provides a detailed literature review of existing FIR filter

implementations on FPGA platforms.

Chapter 3 covers the theoretical foundation, including filter design methods,

pipelining, and hardware optimization strategies.

Chapter 4 presents the Verilog implementation of the FIR filter along with
simulation and test bench development.

Chapter 5 discusses synthesis and implementation results from Vivado

including timing, and power reports.

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 Chapter -2 Literature Survey

2.1 Introduction

The design and implementation of high-speed Finite Impulse Response (FIR)

filters on Field Programmable Gate Arrays (FPGAs) have been an area of
significant research due to the growing demand for efficient and real-time digital
signal processing (DSP) in various applications. FPGA-based implementations
offer the advantages of parallelism, reconfigurability, and high-speed
computation, making them suitable for real-time systems requiring low latency
and high throughput. The following literature review explores the state-of-the-art
techniques and methodologies developed over the years for the FPGA
implementation of high-speed FIR filters. The papers discussed herein highlight
various filter structures, optimization strategies, hardware utilization techniques,
and performance evaluation on different FPGA platforms.

2.2 FIR Filter Architectures and Structures

FIR filters are typically categorized into various architectural forms, including
direct form, transposed form, and systolic arrays. The choice of architecture
greatly impacts the filter’s performance, resource utilization, and speed. Over the
years, researchers have proposed several advanced architectures for improving
the computational efficiency of FIR filters on FPGA.

Direct and Transposed Forms: The direct form FIR filter is the most basic
architecture, where each tap of the filter multiplies the input by a corresponding
coefficient, followed by summing the results. However, its inherent sequential
nature limits its speed. The transposed form rearranges the order of operations to
allow more efficient pipelining and parallel processing, improving throughput.
Various studies, such as those by Zhao and Liu (2020) 8, have implemented
transposed form filters on FPGAs to optimize for speed and resource utilization.

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Systolic Array Architecture: A systolic array is a highly parallel structure in
which the data moves through an array of processing units, minimizing the need
for global interconnects. Systolic architectures have been widely used for FIR
filter designs due to their high parallelism and efficient use of FPGA resources.
According to Banerjee et al. (2021)9, systolic arrays can achieve significant
speedups, making them ideal for high-throughput applications.

Distributed Arithmetic (DA): One of the most significant advancements in

FPGA-based FIR filter design is the use of distributed arithmetic (DA). DA
eliminates the need for multiply-accumulate operations by replacing them with
look-up tables. This technique reduces the computational load, allowing for
faster processing on hardware. Several studies, including those by Meher et al.
(2019)10, have employed DA for FIR filter implementation on FPGAs to achieve
lower latency and higher throughput.

Canonical Signed Digit (CSD): CSD encoding is used to optimize filter

coefficients by reducing the number of non-zero digits in the binary
representation, thus minimizing the number of adders and multipliers required.
Research by Kalaiselvan and Anitha (2020)11 has shown that using CSD in the
FPGA implementation of FIR filters leads to significant savings in hardware
resources, making it an attractive choice for resource-constrained designs.

2.3 FPGA Implementation Techniques and Optimization

Strategies

The efficient implementation of FIR filters on FPGAs requires optimizing

various design parameters, including speed, resource utilization, and power
consumption. Several optimization techniques have been proposed in the
literature to achieve high-performance implementations.

Pipelining: Pipelining is one of the most commonly used techniques to improve

the throughput of FIR filters. By dividing the filter operation into multiple
stages, pipelining allows for parallel execution of different filter stages, reducing

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the overall latency and increasing the clock frequency. Studies such as those by
Sharma and Gupta (2021)12 have demonstrated the effectiveness of pipelining in
improving the performance of FIR filters, achieving higher clock frequencies
and lower latencies.

Parallelism: FPGA architectures are inherently parallel, and exploiting this

parallelism is crucial for high-speed FIR filter designs. By processing multiple
filter taps simultaneously, significant speedups can be achieved. According to
Dandapat et al. (2018)13, parallel architectures can be combined with pipelining
to further enhance performance, achieving high throughput while maintaining
low latency.

High-Level Synthesis (HLS): The use of High-Level Synthesis (HLS) tools has
been gaining popularity in FPGA design, as it allows for easier and faster
development of FPGA-based systems. HLS tools such as Xilinx Vivado HLS
enable designers to describe their filter designs at a high level using languages
like C, C++, or OpenCL, which are then automatically converted into hardware
description language (HDL). Research by Rane et al. (2019) 14 highlights how
HLS tools can significantly speed up the design process while maintaining high
performance in FPGA-based FIR filter implementations.

Quantization and Fixed-Point Arithmetic: While floating-point arithmetic offers

higher precision, it is more resource-intensive and slower on FPGAs.
Consequently, many studies, including that by Gupta and Roy (2017)15, have
investigated the use of fixed-point arithmetic for FPGA implementations of FIR
filters. Fixed-point representations reduce the resource requirements and
increase the speed of FIR filters, making them suitable for real-time DSP
applications.

2.4 FPGA Platforms for FIR Filter Design

Different FPGA platforms offer varying levels of performance, resource

availability, and optimization features. Researchers have explored a range of

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FPGA families to implement high-speed FIR filters, including Xilinx Artix-7,
Virtex-7, and Spartan-6.

Xilinx Artix-7: The Artix-7 family offers a balance between performance and
resource utilization, making it an ideal choice for high-speed DSP applications.
According to Rao et al. (2018) 16, the Artix-7 FPGA provides a good trade-off
between power efficiency and resource usage while achieving high clock
frequencies.

Xilinx Virtex-7: The Virtex-7 family, with its high-speed logic and advanced
DSP slices, is a top choice for high-performance FIR filter designs. Studies such
as by Patel and Gajjar (2017)17 have shown that the Virtex-7 FPGA provides
better performance in terms of throughput, power efficiency, and logic
utilization compared to the Artix-7.

Spartan-6: For low-cost and low-power applications, the Spartan-6 family

provides a more affordable FPGA platform. Research by Joshi and Jain (2021) 18
indicates that the Spartan-6 FPGA can be used for implementing FIR filters,
though with trade-offs in terms of speed and resource utilization compared to
higher-end FPGAs like Virtex-7.

2.5 Performance Evaluation and Comparison of FIR Filter

Implementations

The performance of FPGA-based FIR filters is typically evaluated based on

several key metrics, including throughput, resource utilization, power
consumption, and latency.

Throughput: High throughput is crucial for real-time DSP applications. Studies

such as Meher et al. (2019)19 have demonstrated that pipelined and parallel FIR
filter designs can achieve much higher throughput than non-pipelined versions.

Resource Utilization: Research by Kalaiselvan and Anitha (2020) 20 shows that

while pipelining and parallelism can improve throughput, they may also increase

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resource utilization. Trade-offs must be made between performance and resource
usage.

Power Consumption: Power efficiency is critical in embedded systems. Research

by Joshi and Jain (2021)18 has explored power-efficient FIR filter designs that
minimize power consumption while maintaining high performance using clock
gating and DVFS techniques.

Latency: Low-latency designs are crucial in real-time systems. Studies such as

Dandapat et al. (2018)19 emphasize optimizing latency, particularly when
working with high-speed FIR filters in time-sensitive applications.

2.6 Optimization Techniques for FIR Filters in FPGA

Optimization of Multiplier Structures: Multiplication is a key operation in FIR

filters. One approach is Distributed Arithmetic (DA), which replaces
multiplications with LUTs. According to Tuan et al. (2018) 19, DA significantly
reduces the hardware resources needed for multiplication. A variant, LUT-based
multipliers proposed by Goswami et al. (2019)20, further reduces FPGA resource
usage.

Pipelining and Parallelism for Performance Enhancement: According to Bala et

al. (2019)21, pipelining improves clock frequency by breaking the FIR
computation into stages. Parallel pipelining, proposed by Kumar et al. (2021) 22,
processes different data sets in parallel, increasing throughput with minimal
latency.

Use of High-Level Synthesis: HLS tools are effective for FPGA-based FIR
design. Sharma et al. (2020)23 showed how these tools can automate pipelining,
loop unrolling, and resource sharing to optimize performance.

Low Power Consumption through Design Optimization: Techniques like clock

gating and DVFS help reduce power. Venkatesh et al. (2021) 24 highlight how

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 these methods optimize power without sacrificing performance. Resource
sharing was also proposed by Niranjan et al. (2019)25 to lower energy usage.

Efficient Use of FPGA Resources through CSD: Using Canonical Signed Digit
(CSD) reduces hardware complexity. Sivaram et al. (2020) 26 demonstrate that
CSD encoding minimizes resource utilization, enabling more efficient FIR
implementations.
FIR Filter Optimization FPGA Performance Power
Study
Architecture Techniques Family Metrics Consumption
Distributed Look-Up Table High
Tuan et al., Xilinx Low power due
Arithmetic (LUT)-based throughput,
2018 Spartan-6 to DA
(DA) multiplication low latency
Pipelined High
Kumar et Parallelism, Xilinx High power, not
Parallel throughput,
al., 2021 Pipelining, SIMD Virtex-7 optimized
Architecture low latency
High
High-Level
Sharma et Fixed-point Intel Stratix efficiency, Moderate power
Synthesis (HLS)
al., 2020 FIR Filter V reduced design consumption
optimization
time
Coefficient
Sivaram et CSD-encoded Xilinx Optimized Reduced power,
Encoding (CSD),
al., 2020 FIR Filter Artix-7 area and power low area
Pipelining
Coefficient
Fixed-point, High
Sharma et Quantization, Xilinx Optimized for
16-bit throughput,
al., 2021 Bit-width Virtex-7 power
precision low area
Optimization
Pipelined and Clock Gating, Balanced
Venkatesh Xilinx Significant
Parallel DVFS, Resource throughput and
et al., 2021 Virtex-7 power reduction
Structure Sharing power
Coefficient
High
Hassan et FIR with quantization, Intel Arria Low power and
performance,
al., 2021 reduced order Efficient memory 10 area
real-time
usage
High
Bala et al., High-order Parallelism, Xilinx throughput, High power,
2019 FIR Filter Pipelining Spartan-6 moderate moderate area
latency
LUT-based
Distributed High
Goswami et Multipliers, Xilinx
Arithmetic throughput and Low power
al., 2019 Reduced Virtex-7
(DA) performance
Complexity
Bit-width
Singh et al., Low-order FIR Xilinx Low power, Significantly
optimization,
2021 Filter Artix-7 low area reduced power
Clock gating
Bashir et High-speed Pipelining, Xilinx High High power

17 | P a g e
 parallel FIR throughput,
al., 2020 Parallelism Virtex-7 consumption
Filter low latency
Parallelism, Optimized for Optimized
Amiri et al., Radar-specific Xilinx
High-speed real-time power
2020 FIR Filter Kintex-7
operation processing consumption
High-speed Parallelism, High
Verma et Xilinx Reduced power
FIR Filter with Pipelining, Clock throughput,
al., 2021 Virtex-7 consumption
HLS Gating low latency
Image High speed for
Hassan et Look-Up Tables, Intel Moderate to low
Processing FIR real-time
al., 2020 Parallelism Cyclone V power
Filter processing
Reduced
Niranjan et CSD-based CSD Encoding, Xilinx Significant
resource
al., 2019 FIR Filter LUTs Spartan-6 power savings
utilization
Bit-width High
Niranjan et High-speed Xilinx Low power,
optimization, throughput,
al., 2020 FIR Filter Kintex-7 optimized
Reduced adders low area

18 | P a g e
 Chapter 3 Digital Filters: Methods and Techniques

3.1 Digital Filter Concept

Digital filters offer several compelling advantages:

Flexibility and Programmability: Their behavior can be easily changed by

modifying the algorithm or coefficients, without requiring physical component
changes.
Accuracy and Stability: Digital filters can achieve high levels of precision and
are not subject to component tolerances or drift due to temperature or aging.
Complex Characteristics: They can implement sophisticated filtering
characteristics that are difficult or impossible to achieve with analog circuits.
Cost-Effectiveness: For many applications, especially in integrated circuits and
software, digital filters can be more cost-effective in mass production.
Perfect Reproducibility: Identical digital filters implemented with the same
coefficients will exhibit exactly the same behavior.

3.2 The Fundamental Building Blocks

The behavior of a linear time-invariant (LTI) digital filter is completely

characterized by its impulse response, h[n], and its transfer function, H(z), which
is the Z-transform of the impulse response. The relationship between the input
signal x[n] and the output signal y[n] in the time domain is given by the
convolution sum:

A filter is a frequency selective LTI system, that is a system that passes specified
frequency components and rejects others. The discrete-time filter realizations of
interest here are those LTI systems which have LCCDE representation and are
causal. Note that for certain applications noncausal filters are appropriate.

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An important foundation for digital filter design are the classical analog filter
approximations. An overview of analog approximation techniques will be
provided first.
The filter design problem can be grouped into three stages:
 Specification of the desired system properties (application driven)
 Approximation of the specifications using causal discrete-time systems
 System realization (technology driven - hardware/software) This chapter
will discuss primarily the approximation techniques.
Realization techniques have been presented in part earlier. A common senario in
which one finds a digital filter is in the filtering of a continuous-time signal
using an A/D-H(z)-D/A system (earlier called a C/D-H(ejω)-D/C system).

Figure 1 A/D-H(z)-D/A system

Strictly speaking H(z) is a discrete-time filter although it is commonly referred

to as a digital filter. Recall that for the continuous-time system described above
(ideally)

Using the change of variables ωΩT we can easily convert continuous-time

specifications to discrete-time specifications i.e.

3.3 Overview of Approximation Techniques

Digital filter design techniques fall into either IIR or FIR approaches
Approximation Approaches
 Numerical solution of differential equations

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  Impulse invariant (step invariant etc.)
 Bilinear transformation
FIR Approximation Approaches
 Truncated impulse response with windows Frequency sampling
 Optimum equiripple approximations
 Minimum mean-square error (frequency domain)
Note: The above designs are also typically constrained to have linear phase.

The behavior of a linear time-invariant (LTI) digital filter is completely

characterized by its impulse response, h[n], and its transfer function, H(z),
which is the Z-transform of the impulse response. The relationship between the
input signal x[n] and the output signal y[n] in the time domain is given by the
convolution sum:

∞
y [n]= ∑ x [k ]h[n−k ]=¿ ¿ x[n]∗h[n]
k=−∞

In the Z-domain, this convolution becomes multiplication:

Y (z )=H (z ) X (z)

The transfer function H(z) is often expressed as a rational function in z:

−1 −2 −N −1 −2 −M
H (z )= A(z )B(z )=a 0 +a1 z + a2 z +....+ aN z b 0+ z b1 + z b2 +.....+ z bM

The coefficients {bk} determine the zeros of the filter, while the coefficients {ak
} determine the poles. The locations of these poles and zeros in the complex z-
plane critically influence the filter's frequency response and stability. For a
causal and stable LTI digital filter, all poles must lie strictly inside the unit circle
in the z-plane.

Key Design Considerations and Specifications

The design of a digital filter typically starts with a set of specifications that
define the desired frequency response characteristics. These specifications often
include:

 Passband Frequency (ωp): The range of frequencies that should be

passed with minimal attenuation.

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  Stopband Frequency (ωs): The range of frequencies that should be
significantly attenuated.
 Passband Ripple (δp or Rp): The maximum allowable variation in the
magnitude response within the passband (often expressed in dB).
 Stopband Attenuation (δs or As): The minimum required attenuation in
the stopband (often expressed in dB).
 Transition Band: The frequency range between the passband and
stopband, where the magnitude response transitions from passband to
stopband levels. The width of this band is a crucial design parameter.

3.4 Common Types of Digital Filters

Digital filters are broadly classified into two main categories based on the
duration of their impulse response:

Finite Impulse Response (FIR) Filters: These filters have an impulse response
that is non-zero for a finite duration. Their transfer function has only zeros
(unless there are poles at z=0). FIR filters are always stable and can be designed
to have exactly linear phase, which is crucial for applications where preserving
the time-domain shape of the signal is important (e.g., audio processing, data
transmission). Common design methods for FIR filters include the window
method, frequency sampling method, and optimal equiripple design (Parks-
McClellan algorithm).

Infinite Impulse Response (IIR) Filters: These filters have an impulse

response that theoretically extends infinitely in time. Their transfer function has
both poles and zeros. IIR filters can achieve sharper cutoff characteristics with
lower filter order compared to FIR filters for the same specifications, making
them computationally more efficient in some cases. However, they cannot
generally achieve exactly linear phase. Common design methods for IIR filters
often involve transforming well-established analog filter prototypes (like
Butterworth, Chebyshev Type I, Chebyshev Type II, and Elliptic filters) into the
discrete-time domain using techniques like the bilinear transform or impulse
invariance.

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3.5 Digital Filter Design Methods

Several techniques are employed to design digital filters that meet the desired
specifications:

Window Method (FIR): This intuitive method starts with an ideal frequency
response and multiplies its inverse discrete-time Fourier transform (IDTFT) by a
window function to obtain a finite-length impulse response. Different window
functions (e.g., Rectangular, Hamming, Hanning, Blackman) offer trade-offs
between the main lobe width (related to transition bandwidth) and the side lobe
level (related to stopband attenuation).

Frequency Sampling Method (FIR): This method directly specifies the desired
frequency response at a set of discrete frequencies and then computes the
impulse response using the inverse Discrete Fourier Transform (IDFT).
Interpolation techniques are often used to improve the frequency response
between the sampled points.

Optimal Equiripple Design (Parks-McClellan Algorithm) (FIR): This

powerful iterative algorithm finds the FIR filter coefficients that minimize the
maximum weighted error between the desired and actual frequency response. It
results in filters with an equiripple behavior in the passband and stopband,
providing the most efficient design in terms of filter order for given
specifications.

Impulse Invariance (IIR): This method maps the impulse response of an

analog prototype filter to the impulse response of the digital filter by sampling
the analog impulse response at discrete time instants. It preserves the shape of
the impulse response but can suffer from aliasing if the analog filter's frequency
response is not sufficiently bandlimited.

Bilinear Transform (IIR): This widely used method maps the s-plane
(continuous-time frequency domain) to the z-plane (discrete-time frequency
domain) using the transformation s=T21+z−11−z−1, where T is the sampling
period. This method avoids aliasing but introduces a non-linear frequency

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warping, which needs to be accounted for during the design process by pre-
warping the desired critical frequencies.

Optimization Algorithms (FIR and IIR): More advanced design techniques

can involve direct optimization of the filter coefficients to meet the desired
specifications using algorithms like least-squares, genetic algorithms, or particle
swarm optimization. These methods can handle complex design constraints but
may be computationally intensive.

3.6 Implementation Considerations

Once the filter coefficients are determined, the digital filter needs to be
implemented in hardware or software. Common implementation structures
include:

 Direct Form I and II: These are straightforward implementations

directly based on the difference equation derived from the transfer
function. Direct Form II is often preferred due to its lower memory
requirements.
 Cascade Form: The transfer function is factored into a product of
second-order (and possibly a first-order) sections. This structure is less
sensitive to coefficient quantization effects and offers better control over
pole-zero pairing.
 Parallel Form: The transfer function is expressed as a partial fraction
expansion, resulting in a parallel combination of first-order and second-
order sections. This structure can also offer advantages in terms of
quantization noise and stability.
 Lattice/Ladder Structures: These structures are particularly useful for
adaptive filters and can exhibit good numerical properties.

Advanced Topics and Considerations

 Multirate Signal Processing: Techniques involving changing the

sampling rate of a signal using decimation and interpolation filters.
 Adaptive Filters: Filters whose coefficients change over time based on
the characteristics of the input signal or a desired output.

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  Quantization Effects: The limitations of representing filter coefficients
and signal values with finite precision in digital systems, leading to
effects like coefficient quantization, round-off noise, and overflow.
 Finite Word Length Effects: The impact of using a finite number of bits
to represent signals and coefficients on the filter's performance (e.g.,
frequency response, stability).
 Filter Order Selection: Determining the minimum filter order required
to meet the given specifications is a crucial step in the design process,
balancing performance and computational complexity.
 Group Delay and Phase Response: For applications where the time-
domain characteristics of the signal are important, the linearity of the
phase response (or constant group delay) is a critical design
consideration.

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 Chapter 4- Design Methodology
4.1 Introduction

Today Field Programmable Gate Array (FPGA) has been used

widely in digital circuit application. Applications of FPGAs include DSP,
software-defined radio, aerospace and defense systems, ASIC prototyping,
medical imaging, computer vision, speech recognition, cryptography,
bioinformatics, and a growing range of other areas. This information is
cited from internet sources.

4.2 Field Programmable Gate Array

Field Programmable Gate Array (FPGA) is a semiconductor device

containing programmable logic component and programmable
interconnection. The programmable logic components can be programmed
to duplicate the functionality of basic logic gates or more complex
combinatorial functions such as decoders or simple math functions. In most
FPGAs, these programmable logic components also include memory
elements, which may be simple flip-flops or more complete blocks
memories. An FPGA is a regular structure of logic cells or modules and
interconnect which is

under the designer’s complete control. This means the user can design,
program and make changes to circuit whenever the user wants. This
information is cited from internet sources.

4.2.1 Type of FPGA

Basically, there are 2 basic types of FPGA device, SRAM-based

reprogrammable and One-time programmable (OTP). These two types of
FPGA differ in the implementation of the logic cell .and the mechanism
used to make connections in the device. The dominant type of FPGA is
SRAM-based and can be reprogrammed by the user as often as the user
chooses. In fact, an SRAM FPGA is reprogrammed every time it is
powered-up because the FPGA is really a fancy memory chip. Figure 2 and

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 Figure 3 shows the reprogrammable (SRAM-based) and one-time
programmable
Figure 3 One-time Programmable
(OTP)

Figure 2 Reprogrammable (SRAM-

Based)

In the SRAM logic cell, instead of conventional gates there is instead a

Lookup Table (LUT) which determines the output based on the values of the
inputs (In the “SRAM logic cell” diagram above you can see 6 different
combinations of the 4 inputs that will determine the values of the
output). SRAM bits are also used to make

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 connections. One-time programmable (OTP) FPGA use anti-fuses (contrary
to fuses, connections are made not “blown” during programming) to make
permanent connections in the chip and so do not require a SPROM or other
means to download the program to the FPGA. However, every time you
make a design change, you must throw away the chip. The OTP logic cell
is very similar to PLD with dedicated gates and flip-flops.

4.2.2 Design Flow of FPGA

The design flow broadly refers to the sequence of activities

encompassing various design tools that begin with some abstract
specification of a design and ends with a configured FPGA. Design flow of
FPGA start with system design and follow by I/O assignment and analysis.
After the process of Register Transfer Level (RTL) synthesis, place and
route will be taking place. The FPGA device will interface with the system
verification and place and route process. Figure 4 shows the design flow of
PFGA device.

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 Figure 4 The design flow of PFGA device.

4.2.3 Architecture of FPGA

The typical basic architecture of FPGA consists of an array of logic

blocks and routing channels. Multiple I/O pads may fit into the height of
one row or the width of one column. Generally, all the routing channels
have the same width (number of wires). The typical FPGA logic block
consists of a 4-input lookup table (LUT), and a flip-flop, as shown at Figure
5 below. There is only one output, which can be either the registered or the
unregistered LUT output. The logic block has four inputs for the LUT and a
clock input. This information is cited from internet sources.

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 Figure 5 FPGA Logic Block

4.2.4 Advantages of FPGA

A recent trend shows that FPGA is commonly used for the designers
for their complicated digital design. It is because FPGA have several
advantages such as a shorter time to market, ability to re-program in the
field to fix bugs, and lower non-recurring engineering costs. There are
also some vendors may offer less flexible versions of their FPGAs that are
cheaper. In other words, by using FPGA, the design made is cost-effective
and time-effective. Besides that, the development of designs is usually
made on regular FPGAs because it has the ability to modify the design.
Another advantage of FPGA is it can be easily implement in hardware and is
not time consuming. Therefore, the designer can obtain the result of their
design in a very short period. The FPGA is very easy to interface with the
embedded microcontroller or embedded microprocessor and other
peripherals to form a complete system on a programmable chip. This
information is cited from internet sources.

4.3 Very High Speed Integrated Circuits Hardware

Description Language

Very High Speed Integrated Circuits Hardware Description Language

(VHDL) has been at the heart of electronic design productivity since initial

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 ratification by the Institute of Electrical and Electronic Engineers (IEEE) in
1987. The Language use to implement this cryptography system is VHDL.
VHDL is a language used to describe hardware from the abstract to the
concrete level. This program was sponsored by the Department of Defense
(DoD) with the goals of developing a new generation of high-speed
integrated circuit. In the course of this program, it became clear that there
was a need for a standard language for describing the structure and function
of Integrated Circuits (ICs). Hence the VHDL was developed, and
subsequently adopted as a standard by the IEEE in the US.

4.3.1 Description of VHDL/Verilog

VHDL is becoming increasingly popular as a way to capture complex

digital electronic circuits for both simulation and synthesis. It is designed to
fill a number of needs in the design process. Firstly, it allows description of
the structure of a design. That is how it is decomposed into sub-designs, and
how those sub-designs are interconnected. Secondly, it allows the
specification of the function of designs using familiar programming
language forms. Thirdly, as a result, it allows a design to be simulated
before being manufactured, so that designers can quickly compare
alternatives and test for correctness without the delay and expense of
hardware prototyping.

4.3.2 Advantages of VHDL/Verilog

VHDL/Verilog is a language of big breadth; this is because there are

many advantages of VHDL/Verilog over other language. VHDL allows one
language to be used for the entire design process. A single designer
knowing VHDL/Verilog can design and simulate a complete system on
many levels of description. VHDL/Verilog offers several advantages to the
designer such as:-
 It is a standard language which having the readily available tools.
 Designer using VHDL/Verilog becomes quickly much more productive
than a classical designer who uses schematic capture, or point
languages.

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  Design time is shortened. Design re-uses, Because the description in
on a very high level, it is technology independent. It can be then
used to generate low-level descriptions for many technologies. High-
level constructs can be translated to new technologies and re-used.
 Level of abstraction. VHDL/Verilog allows designing on RTL and
behavioral level, thus the designer thinks on the design concept level
rather on the component connecting level.
 Technology independent design. Because of possibility of high-level
description, selection of technology can be delayed or changed in the
last moment without essential redesign.
 Improved quality of design. The user can easily modify his high-level
description, thus exploring a larger space of solutions. Moreover, there
are tools that will automatically generate many solutions, generate
solutions optimized with certain respect, and use automatic logic
synthesis, mapping or layout optimizations. Combination of all above
properties allows obtaining high-quality designs quickly.
 VHDL/Verilog is a catalyst that allows designers to move up to an
HDL design methodology.

4.4 Design specifications

Designing a high-speed FIR (Finite Impulse Response) filter on an FPGA (Field

Programmable Gate Array) using Vivado requires a systematic approach, which
ensures that the filter meets the desired performance metrics such as throughput,
latency, resource usage, and power consumption. The methodology outlined in
this section presents a step-by-step approach to the design, including key design
decisions, toolchain usage, and optimization strategies.

4.4.1. Specification Definition

The design process begins with defining the filter specifications. The key
parameters for a high-speed FIR filter design include:

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Filter Type: The FIR filter can be low-pass, high-pass, band-pass, or band-stop,
depending on the application. For high-speed applications, low-pass FIR filters
are commonly used.
Order (N): The filter order represents the number of taps or coefficients. A
higher order increases the complexity but improves the filter's performance, such
as steeper roll-off and better attenuation in the stopband.
Sampling Frequency (Fs): This is the rate at which input signals are sampled. It
is critical in determining the clock frequency for the FPGA and the filter's
frequency response.
Cutoff Frequency: This determines the threshold between the passband and
stopband. The filter must attenuate frequencies above or below the cutoff,
depending on the type (low-pass or high-pass).
Passband Ripple and Stopband Attenuation: The filter's performance is also
characterized by the maximum allowable ripple in the passband and the
minimum required attenuation in the stopband.
Throughput and Latency Requirements: High-speed applications typically
require high throughput, i.e., the ability to process a large volume of data in real-
time. Minimizing latency is also crucial for many real-time signal processing
applications.

4.1.2. Mathematical Model of the FIR Filter

The FIR filter's output y[n] is a weighted sum of its past inputs x[n], and the
filter can be represented mathematically as:

Where:
y[n] is the output signal at time step.
x[n−k] is the input signal at time n−k, where k is the index of the filter taps.
h[k] are the filter coefficients (or impulse response), which determine the
frequency response of the filter.
N is the filter order (number of taps).

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The filter coefficients h[k] are typically determined using design algorithms such
as the Window Method, Parks-McClellan algorithm, or Least Squares method.
These methods ensure that the FIR filter meets the specified frequency response
(cutoff frequencies, passband ripple, and stopband attenuation).

4.1.3. Design Considerations

Several considerations play a vital role in designing a high-speed FIR filter

suitable for FPGA implementation. These include:

Pipelining: Pipelining is a crucial technique for improving the throughput and

reducing the latency of the FIR filter. In pipelined designs, the computations are
divided into stages, allowing for concurrent processing of multiple data samples.
This results in higher throughput by enabling each stage of the filter to operate
on different data points simultaneously.

Parallelism: Implementing multiple parallel paths can further increase the speed
of the FIR filter. This involves distributing the filter taps across different
processing units, allowing for simultaneous computation of the weighted sums.
For example, by processing multiple input samples at the same time, parallelism
can significantly boost performance.

Bit-width Optimization: The choice of bit-width for the input data, filter
coefficients, and intermediate results impacts both performance and resource
usage. Using a reduced bit-width for fixed-point implementation can lower the
number of logic resources required on the FPGA, but may affect the precision of
the filter. A balance between resource usage and precision must be achieved.

Fixed-Point vs. Floating-Point Arithmetic: In FPGA-based designs, fixed-point

arithmetic is typically used due to its lower resource requirements and faster
operation. However, for designs requiring higher precision, floating-point
arithmetic may be used, though it comes at the cost of increased resource usage.

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Distributed Arithmetic: Distributed Arithmetic (DA) is a technique often
employed in FPGA-based FIR filter designs to replace multiplication operations
(which are resource-intensive) with shift-and-add operations. This method
reduces the resource usage and is highly efficient for specific types of FIR
filters.

Efficient Multiplication: Multiplication is an essential operation in FIR filter

design. FPGAs are equipped with DSP (Digital Signal Processing) slices that can
be utilized to implement fast multiplications. Using these DSP blocks effectively
can lead to significant speed improvements.

4.1.4. HDL Implementation (VHDL/Verilog)

Once the filter specifications and design considerations are in place, the next
step is to implement the FIR filter in a hardware description language (HDL).
Typically, VHDL or Verilog is used for modeling FPGA designs.

Modeling the Filter: The FIR filter's computation is described as a series of

register-based operations. The input values are stored in registers, the filter’s
coefficients are defined, and the outputs are computed by performing the
weighted sum of input values. This process is repeated for every clock cycle.
The design is structured into stages, with pipelining used to ensure high
throughput.

Test bench Development: Alongside the filter implementation, a test bench is

created to verify the functionality of the FIR filter design. The test bench
provides stimulus in the form of input test vectors and checks the filter's output
to ensure correctness. Simulations are run to validate that the FIR filter produces
the expected output for various input signals, including edge cases and transient
signals.

4.1.5. Toolchain Setup (Vivado)

Project Creation: The next step is to create a new FPGA project in Vivado. In
Vivado, the user specifies the target FPGA device (e.g., Xilinx Artix-7, Virtex-7,

35 | P a g e
Ultra Scale+), and the HDL files (VHDL or Verilog) for the FIR filter design are
added to the project.

IP Core Utilization (Optional): Vivado provides a FIR Compiler IP that can be

used for generating the filter automatically. This IP can be customized based on
the filter specifications, including the number of taps, filter type, and coefficient
format. For more complex designs, custom RTL (Register Transfer Level) code
might be required.

Synthesis: After the FIR filter design is modeled in HDL and the project setup is
complete, Vivado synthesizes the design. Synthesis converts the high-level
description into a netlist, which is a gate-level representation of the filter logic.

Implementation: After synthesis, Vivado implements the design, including the

placement and routing of logic elements on the FPGA. Placement involves
assigning the design's logic to the FPGA's resources (e.g., LUTs, DSP slices),
and routing ensures that the design’s components are connected as specified.

Timing Analysis: Vivado performs timing analysis to verify that the filter
operates correctly at the desired clock frequency. The timing constraints, such as
clock period and setup/hold times, must be met for the design to function
properly.

Bit stream Generation: After successful synthesis and implementation, Vivado

generates a bit stream file that can be used to configure the FPGA.

4.1.6. Simulation and Verification

Functional Simulation: Before programming the FPGA, the filter’s functionality

is verified through simulation. Vivado's built-in simulator or external tools like
ModelSim are used to run simulations. The input and output of the filter are
checked against expected results to ensure correctness.

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Post-Implementation Simulation: After generating the bit stream, post-
implementation simulation is performed to ensure the design works correctly on
the actual FPGA hardware.

4.1.7. Hardware Implementation and Testing

FPGA Programming: The final bit stream file is uploaded to the FPGA using a
JTAG interface or other programming tools.

Hardware Testing: The design is tested on the FPGA to ensure it meets the
performance requirements. This includes testing the throughput, latency, and
functional correctness. Input signals are provided to the FPGA, and the outputs
are monitored and compared to the expected values.

4.1.8. Performance Analysis and Optimization

Throughput: The performance of the filter is evaluated based on throughput. The

throughput is determined by the clock frequency and the number of pipelining
stages implemented in the design.

Latency: The latency, or delay, from input to output is also analyzed.

Minimizing latency is crucial for high-speed applications where real-time
processing is essential.

Resource Utilization: The number of FPGA resources used (such as LUTs, DSP
slices, and memory blocks) is analyzed. Optimizations such as reducing bit-
widths, using shared resources, and efficient pipelining can reduce resource
usage.

Power Consumption: Finally, the power consumption of the design is analyzed.

Power optimization techniques such as clock gating, voltage scaling, and using
low-power FPGA families can help reduce the overall power consumption.

4.2 Algorithm

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The algorithm for designing a high-speed FIR filter on an FPGA involves
several key steps, from defining filter parameters to implementation and testing.
Here's a step-by-step breakdown of the algorithm:

4.2.1. Initialize Filter Specifications

 Input parameters: Filter type (low-pass, high-pass, band-pass, band-stop),

filter order (N), cutoff frequency, passband ripple, stopband attenuation, and
sampling frequency.
 Choose the arithmetic type: fixed-point or floating-point.
 Determine the FPGA resources and clock frequency based on the required
throughput and latency.

4.2.2. Compute Filter Coefficients

 Use a filter design method (e.g., windowing, Parks-McClellan, or least

squares) to compute the filter coefficients.
 If using the windowing method:
 Select a window type (e.g., Hamming, Blackman-Harris).
 Calculate the filter coefficients based on the desired cutoff frequency and
order.
 If using Parks-McClellan, use the algorithm to minimize the error in the
stopband.

4.2.3. Design FPGA-Friendly Architecture

 Choose the architecture: pipelined, parallel, or a combination.

 Implement fixed-point or floating-point multiplication, ensuring that the
hardware can handle the required precision with minimal resource usage.
 Apply techniques like Distributed Arithmetic (DA) for efficient resource
utilization and faster computation.

4.2.4. Implement FIR Filter in HDL (VHDL/Verilog)

 Write the Verilog or VHDL code to implement the filter.

 Input: Register input data.
 Process: Calculate weighted sums of inputs using filter coefficients.

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 Output: Store the result in the output register.
 Create a pipelined structure to increase throughput by processing multiple
data samples concurrently.

4.2.5. Develop Test bench for Verification

 Create a test bench to simulate the FIR filter in Vivado.

 Provide input test vectors and expected output for verification.
 Run simulations (functional and timing) to ensure that the filter works as
expected.

4.2.6. Implement in Vivado

 Create a new project in Vivado and import the HDL files.

 Choose the target FPGA device and constraints (e.g., clock frequency).
 Perform synthesis and implementation (placement and routing).
 Generate the bit stream file for FPGA programming.

4.2.7. Program the FPGA and Test Hardware

 Program the FPGA with the generated bit stream file.

 Test the hardware with real input signals and compare the output against
exected results.
 Perform additional optimizations if necessary (e.g., optimizing resource
usage, power consumption).

4.2.8. Performance Analysis and Optimization

 Evaluate throughput, latency, resource utilization (LUTs, DSPs, BRAM),

and power consumption.
 Optimize based on testing results. Apply any necessary adjustments to
achieve high performance.

4.2.9. Final Validation

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 Ensure the filter meets performance requirements in terms of throughput,
accuracy, and latency.
 Finalize the design for deployment.

4.3 Flowchart for proposed model

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 Figure 6 Flow chart for proposed system

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4.4 Implementation of proposed model

 Design Specification
 Filter Coefficient Generation (using MATLAB or Python)
 FIR Filter VHDL/Verilog Code
 Vivado Project Setup
 Simulation with Test bench
 Synthesis and Implementation
 Bit stream Generation
 Hardware Testing (optional)

4.4.1 Design Specification

 Filter Type: FIR (Low-pass / High-pass )

 Order: 31 (example, can vary)
 Sampling Frequency: 100 MHz
 Input Width: 8 or 12 bits
 Coefficient Width: 16 bits
 Output Width: 24 bits
 Target Device: Xilinx Artix-7 / Spartan-6 / Zynq

4.4.2. Filter Coefficient Generation (MATLAB)

Use MATLAB’s fir1() or Python [Link]() to generate coefficients:

N = 31; % Filter order

Fc = 0.2; % Normalized cutoff frequency (Fc = f_cutoff / (Fs/2))
b = fir1(N, Fc);
b_fixed = round(b * 2^15); % Fixed-point format
disp(b_fixed);

After calculated the values, copy these fixed-point values into our HDL code.

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4.4.3. FIR Filter Verilog Code(Sample code)

module fir_filter #(
parameter N = 32
)(
input clk,
input reset,
input signed [7:0] x_in,
output reg signed [23:0] y_out
);
// Replace with actual coefficients
reg signed [15:0] h [0:N-1] = '{16'd45, 16'd112, 16'd212, ..., 16'd45};

reg signed [7:0] x_reg [0:N-1];

integer i;

always @(posedge clk or posedge reset) begin

if (reset) begin
for (i = 0; i < N; i = i + 1)
x_reg[i] <= 0;
y_out <= 0;
end else begin
// Shift register
for (i = N-1; i > 0; i = i - 1)
x_reg[i] <= x_reg[i-1];
x_reg[0] <= x_in;

// Multiply-accumulate
y_out <= 0;
for (i = 0; i < N; i = i + 1)
y_out <= y_out + x_reg[i] * h[i];
end
end
endmodule

4.4.4. Vivado Project Setup

o Open Vivado
o Create New Project

Name: fir_filter_fpga
Language: Verilog
Board/Device: Your FPGA board (e.g., Nexys A7, Basys 3)

o Add Sources

Add fir_filter.v
Add testbench tb_fir_filter.v

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4.4. 5. Verilog Test bench

module tb_fir_filter;
reg clk = 0;
reg reset = 1;
reg signed [7:0] x_in;
wire signed [23:0] y_out;

fir_filter uut (
.clk(clk),
.reset(reset),
.x_in(x_in),
.y_out(y_out)
);

always #5 clk = ~clk;

initial begin
#20 reset = 0;
#10 x_in = 8'd1;
#10 x_in = 8'd2;
#10 x_in = 8'd3;
#10 x_in = 8'd4;
#10 x_in = 8'd5;
#100 $stop;
end
endmodule

4.4. 6. Synthesis and Implementation

o Click Run Synthesis

o Check for critical warnings or errors.
o Click Run Implementation
o Review resource usage and timing.

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 Chapter 5 - Results and Discussions

5.1 Propose Model (HIGH PASS FILTER)

5.1.1 RTL Schematic for Propose Model (HIGH PASS FILTER)

Figure 7 RTL Schematic diagram

The RTL Schematic diagram that illustrates in figure 7 a digital signal
processing system implemented on an FPGA using two main components:
1. FIR Filter Block
2. UART Transmitter Block
1. Inputs:
 clk (clock): Drives the timing for all synchronous components.
 rst (reset): Used to initialize or reset the state of both FIR and UART
blocks.
 data_in[11:0]: A 12-bit parallel input data bus feeding the FIR filter.
Likely represents sampled data from a sensor or ADC.
2. FIR Filter Block (fir_inst):
 Module Name: fir_filter
 Inputs:
o clk: Clock input for synchronous operation.
o rst: Reset signal to initialize internal states.
o data_in [11:0]: 12-bit parallel data input.
 Outputs:
o data_out [23:0]: 24-bit filtered output (usually a result of internal
multiplication and accumulation which increases bit-width).

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 o valid: Control signal indicating when the data_out is valid and
ready to be processed by the next stage.
Functionality:
o Performs Finite Impulse Response (FIR) filtering, a common
digital filter used to remove noise or extract features from input
signals.
o Once enough samples are processed, the valid signal goes high.
3. UART Transmitter Block (uart_inst):
 Module Name: uart_tx
 Inputs:
o clk: Shared clock.
o rst: Reset.
o data_in[23:0]: 24-bit filtered data from FIR.
o data_valid: Control signal, connected to valid output of FIR filter,
indicates data is ready to be sent.
 Outputs:
o tx: UART transmit line (serial bitstream output).
o tx_done: Indicates that transmission of one frame is complete.
Functionality:
o This module serializes the 24-bit parallel data for transmission
over a UART protocol.
o Data is only transmitted when data_valid is high.
o Once transmission is completed, tx_done goes high.
4. Output:
 data_out[23:0]: This is the filtered output from the FIR block which is
also fed into the UART block. Useful if you want to observe the output
before or independently of the UART transmission.
Signal Flow Summary:
1. data_in[11:0] → FIR Filter (fir_inst)
2. fir_inst produces data_out[23:0] and valid when ready.
3. data_out → both to output port and uart_inst for transmission.
4. valid → data_valid of uart_inst, initiating UART transmission.
5. uart_inst sends data out serially via tx and raises tx_done when done.

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5.1.2 Top Level model:

The Figure-8 shows a long bus connection, likely representing a bit expansion,
mapping, or routing of a signal bus in your digital system design. The horizontal
line with many small circular nodes is a bus signal, likely 24 bits wide or more.
In Figure 9 to Figure 13 shows the part wise of top level model for the proposed
system design which gives clear diagrammatic view.

Figure 8 Top Level model

The green lines at the end connect to a small cluster of component this is usually
where:
 Bits are split or grouped.
 The bus is routed to output pins or other modules.

Figure 9 Part -1 of Top Level model

Figure 10 Part -2 of Top Level model

Figure 11 Part -3 of Top Level model

Figure 12 Part -4 of Top Level model

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 Figure 13 Part -5 of Top Level model

1. Modules: RTL_mux_AXIWC

Each yellow box labeled RTL_mux_AXIWC represents an instance of a custom

module or an IP core. These modules appear to:
 Accept input from a shared bus (data_wr_reg),
 Output to another signal bus (data_wr_regN, where N = 1 to 5),
 Likely implement multiplexing, registering, or arbitration logic (based
on the name mux_AXIWC).

2. Input and Output Bus Signals

 Input:
o data_wr_reg[23:0] is the original 24-bit bus fed into the first
module.
 Output:
o Each subsequent module produces a modified or delayed output:
data_wr_reg1[23:0], data_wr_reg2[23:0], ..., up to
data_wr_reg6[23:0].
This pattern indicates a pipelined processing structure.

3. Signal Flow

 Each module receives the clk (clock) and rst (reset) signals — indicating
synchronous operation.
 The outputs of each stage feed into the next stage, forming a chain
(like a shift register, pipelined FIR filter taps, or staged multiplexers).
Interpretation:
From your earlier diagrams (with FIR filter and UART), this figure likely
belongs to a register or multiplexer pipeline that:

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  Stages data before sending it for transmission or output (e.g., in a
UART),
 Could implement a data buffer for pipelined FIR output samples,
 Or may be a parallel bus multiplexer/scheduler if using AXI-
compatible logic.

1. RTL_mux_AXIWC Modules (Left Side)

 Modules: RTL_mux_AXIWC are receiving signals like

data_wr_reg1[23:0], data_wr_reg2[23:0], etc.
 These likely extract or pass specific delayed data samples in a shift-
register-like fashion (e.g., FIR tap inputs).

2. RTL_MUL (Multiplier Block)

 Takes two inputs (data from the above mux modules).

 Output: accumulator1
 Likely function: accumulator1 = data_wr_reg1 × data_wr_reg2

3. RTL_ADD (Adder Block)

 Input: accumulator1 and possibly another term (could be prior

accumulated value).
 Output: accumulator2
 Operation: accumulator2 = accumulator1 + previous value
This is a common structure for multiply-accumulate operations (MAC) used
in DSP filters.

4. RTL_mux and RTL_mux_AXIWC (Right Side)

 There is a MUX (RTL_MUX) deciding between two sources:

accumulator2 and some other bus (possibly bypass or reset).
 This output goes into another register module (accumulator_reg[23:0]),
storing the accumulated value.

5. Final Output Stage

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  Another RTL_mux_AXIWC fetches accumulator_reg[23:0] and routes it
to the output: data_wr_out[23:0].

Control Signals

 Control signals like valid, mux_sel, and clk/rst are used to enable
pipelining, synchronization, and multiplexer control.

Figure 14 (Register Transfer Level) schematic

 Left Side (Linear Array of Elements):

o This likely represents a register bank or data buffer — possibly
a shift register, FIFO input, or bit-serialized input interface.
o The repeated small logic cells could be flip-flops (DFFs) used for
bit storage or delay lines.
 Middle Section:
o Appears to include multiplexers, control logic, or possibly state
machine decoders. The connections here are more centralized,
suggesting coordination or routing.
 Right Side:
o Multiple logic gate structures and registers seem to drive output
logic or state transitions.
o Could also contain the control path of a UART, FIR filter
controller, or FSM-based unit.

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5.1. 3 RTL data path

Figure 15 RTL data path

Figure 15 shows a much more complex RTL data path, likely a fully
pipelined or parallelized FIR filter or MAC-based DSP unit. The structure
appears to involve multiple stages of:
 Multipliers
 Adders
 MUXes
 Registers
1. Pipelined Multiply-Accumulate (MAC) Units

 Several chains of multiply → add → register blocks.

 Each multiplier likely corresponds to a tap in an FIR filter.
 Adders combine results across the taps.
 Registers are placed between stages → ensures pipelining and
synchronization.

2. MUX Logic

 Multiple MUX components are used to control data flow paths.

 This likely implements data selection (e.g., between init/reset values and
accumulated results).
 May also support control logic for enable/disable, flushing, or
dynamic reconfiguration.
3. Final Output Path
 The final stage seems to combine all accumulated values and route them
toward an output bus.

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  Registers at the end store the computed result, likely synchronized with a
clock and valid signal.
Functionality
This RTL architecture looks like a parallel and pipelined FIR filter or
vectorized MAC array with high throughput:
 Multiple taps and stage-wise accumulation.
 Latency is reduced by pipelining.
 Suitable for high-speed signal processing (e.g., audio, image, or RF
applications).

5.1.4 Top-level RTL netlist

This latest figure 16 shows a top-level RTL netlist or block diagram that
appears to be the input/output interface logic of your system, likely for data
acquisition and UART transmission. Architecture Breakdown
Input Section (Left)
 16 Inputs: data_in[0] to data_in[15], each connected to a buffer (e.g.,
BUF).
 This resembles parallel input data acquisition, likely from sensors or a
memory bus.
 All are connected to internal wires named data_in_BUF[xx]_inst.
Control Section (Center)
 A clock buffer (clk_BUF_inst) and reset buffer (rst_BUF_inst) handle
timing and reset signals.
 Two important modules:
o rx_inst: Possibly receives control/config data (e.g., from UART
or another serial interface).
o uart_inst: Handles data transmission, suggesting a UART
interface for output.
Output Section (Right)
 16 data_out lines from data_out_BUF[xx]_inst.
 These feed into the uart_inst block.
 Signals like tx, tx_done, and data_out[255:0] indicate that a UART
transmitter is outputting a 256-bit wide data stream.

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Functional Summary
This block likely performs:
 Input buffering of 16 parallel data signals.
 UART-based serialization of those signals for communication.
 Possibly part of a signal processing chain output, such as:
o FIR filter results
o Sensor data logging
o Image data stream
 Control over TX via tx_done, tx signals.

Figure 16 Block diagram

Purpose of IBUF Block
This structure ensures:
 The incoming external signal is safely brought into the FPGA fabric.

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  You retain the option to disable the buffer or control I/O behavior
dynamically, which is crucial for power-sensitive or reconfigurable
systems.
The figure 17 that provided is a zoomed-in RTL schematic view of the IBUF
(Input Buffer) instance for data_in_IBUF[0]_inst, specifically showing how
external input data is being handled in your design.

Figure 17 RTL schematic view of the IBUF

Detailed Component Breakdown

1. INBUF_INST (Primitive: IBUF)
 This primitive buffers the signal from the FPGA pad (physical input pin).
 Input: PAD (I/O pad)
 Output: O (internal logic signal)
2. IBUFCTRL_INST (Primitive: IBUFCTRL)
 Provides fine control over the IBUF behavior.
 Key control pins (unused in your case):
o IBUFDISABLE: Disables the IBUF if high (n/c = not connected
here).
o INTERMDISABLE: Controls termination circuitry (optional).
o T: High-Z control for tri-state input.
 Output: Drives the internal signal forward to logic.

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5.1.5 Power Estimation

 Total On-Chip Power: 31.063 W

This is relatively high, depending on the FPGA and use case — it
suggests a demanding design.
 Dynamic Power (90%): 28.072 W
o I/O: 27.109 W → 97% of dynamic power!
This is unusually high and suggests heavy toggling or high drive
strength settings on the I/O pins.
o Logic: 0.311 W → minimal contribution from internal gates.
o Signals (routing): 0.652 W
 Device Static Power: 2.991 W (10%)
o This is the baseline leakage/idle consumption of the FPGA fabric.
Thermal Info
o Junction Temperature: 41.2°C
o Well below thermal limits, so current cooling is sufficient.
o Thermal Margin: 58.8°C (104.5 W max allowable)
o Good headroom — no immediate overheating risk.

Figure 18 Power Estimation Summary report

5.1.6 Output waveform of proposed model (HIGH PASS FILTER)

1. clk and rst (Clock and Reset):

 Clock (clk) is toggling correctly.
 Reset (rst) is deasserted (0) from the beginning.

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2. data_in = "789" (Changing over time):
 Data input seems to progress through values: "000" → "abc" → "123" →
"456" → "789" at ~20 ns intervals.
 This indicates some kind of input stimulus or testbench cycling data
every 20 ns.
3. data_out = 000000 (Flat line):
 Starts as xxxxxxx (undefined), becomes 000000 and stays flat — not
responding to data_in.
4. tx = 1 (Stuck high):
 Transmission line is high (idle state in UART).
 No transition → no data is being serialized/transmitted.
5. tx_ready = 0:
 Indicates not ready to transmit — possible internal FSM or buffer not
enabling tx.

Figure 19 Output waveform of proposed model

5.1.7 Xilinx Ultrascale+ Integrated Block for PCI Express

The image depicts a high-level block diagram featuring a Xilinx Ultrascale+

Integrated Block configured for PCI Express (PCIe) Gen4. This block, labeled
"pcie4_uscale_plus_0," interfaces with several external signals and internal
utility blocks.
Connectivity and Functionality:
 The pcie_refclk signal is buffered by the util_ds_buf to generate
differential clock signals (IBUF_DS_ODIV2[0:0]) that are likely used as

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 the reference clock for the PCIe SerDes (sys_clk_gt) and potentially the
system clock (sys_clk) of the PCIe core.
 The pcie_perstn signal directly connects to the reset input of the
"pcie4_uscale_plus_0" block.
 The "pcie4_uscale_plus_0" block manages the entire PCIe
communication stack, from the physical layer signaling through the data
link and transaction layers, as indicated by its numerous ports.
 The wide "pcie_express_x16" output indicates a high-bandwidth PCIe
connection, capable of significant data transfer rates.

Figure 20 high-level block diagram featuring a Xilinx Ultrascale+ Integrated Block

configured for PCI Express (PCIe) Gen4

This block diagram illustrates the integration of a Xilinx Ultrascale+ FPGA's

PCIe Gen4 IP core. It highlights the necessary clock and reset inputs, the
extensive control and data interfaces of the PCIe core, and the high-bandwidth
x16 physical interface for communication with a PCIe endpoint or root port. The
use of a utility buffer for the reference clock suggests careful clock distribution
within the FPGA design.

5.2 Propose Model (LOW PASS FILTER)

5.2.1 RTL Diagram:

The diagrams illustrate a pipelined dataflow architecture.

1. Input Ports:
o rst: A single-bit reset signal.

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 o clk: A single-bit clock signal.
o data_in[11:0]: An 12-bit input data bus.
2. Registers (RTL_REG_ASYNC): There are several registers labeled
RTL_REG_ASYNC. These are likely asynchronous reset flip-flops.
They are used to store intermediate results and pipeline the dataflow.
You can see the data flowing through a chain of these registers.
3. Multipliers (RTL_MULT): There are three multiplier blocks labeled
RTL_MULT. These blocks take two input operands and perform
multiplication.
o One multiplier takes x_reg[1][11:0] and data_out31_i.
o Another takes x_reg[2][11:0] and data_out30_i.
o A third takes x_reg[4][11:0] and data_out29_i.
4. Adders (RTL_ADD): There are two adder blocks labeled RTL_ADD.
These blocks take two input operands and perform addition.
o One adder takes the output of the first multiplier and
data_out30_i.
o Another adder takes the output of the second multiplier and
data_out29_i.
5. Signals: The green lines represent data signals connecting the different
blocks. The bit widths of these signals are indicated in square brackets
(e.g., [11:0] for 12 bits, [16:0] for 17 bits).
6. Dataflow: The input data data_in is registered and then used in
subsequent operations. The outputs of the registers (x_reg) are fed into
the multipliers. The outputs of the multipliers are then fed into the
adders, creating a chain of arithmetic operations. The data_out signals
likely represent intermediate or final outputs of the computation.

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 Figure 21 RTL View for propose model ( Low Pass Filter)

Figure 22 Part- 1 RTL View for propose model

Figure 23 Part -2 RTL View for propose model

Figure 24 Part -3 RTL View for propose model

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 Figure 25 Part - 4 RTL View for propose model

Figure 26 Part -5 RTL View for propose model

Figure 27 Part -6 RTL View for propose model

Figure 28 Part -7 RTL View for propose model

5.2.2 TOP LEVEL MODEL

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 Figure 29 Top Level Model
Interpretation Tips
Identifying specific components or trace signal flow:
1. Use Schematic Navigation Tools:
o In Vivado, click elements and use “Highlight Net” to trace
[Link] hierarchy browser to focus on specific blocks
(e.g., FSM, datapath).
2. Label Decoding:
o Try zooming in or exporting the RTL schematic with signal
names. Look for modules named ctrl, fsm, mux, reg, or alu.
3. Simulation/Elaboration Tools:
o Use Vivado's elaborated design or post-synthesis netlist for
clearer logic breakdown.

5.2.3 OUTPUT WAVE FORM (LOWPASS Filter)

The three provided simulation waveforms, and here's a comparison across

Behavioral Simulation, Post-Synthesis Functional Simulation, and Post-
Synthesis Timing Simulation:
Observations from the Waveforms:
All three waveforms show the same set of signals over a simulation time of 1000
ns. The key signals and their behaviors are:

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  clk: A periodic clock signal with a period of approximately 40 ns
(frequency of 25 MHz).
 rst: An active-low reset signal that is asserted at the beginning of the
simulation and then de-asserted after around 80 ns.
 data_in[11:0]: An input data bus that takes on different hexadecimal
values at different times (e.g., 7d0, 000, 7d0).
 data_in_tlast: A single-bit signal that appears to be associated with the
input data stream, possibly indicating the last data element. It is high
when data_in is 7d0 around the 120 ns mark and again around the 760 ns
mark.
 valid: A single-bit signal that goes high after the reset is de-asserted and
stays high for most of the simulation, indicating that the input data is
valid.
 reg_out[31:0]: A 32-bit output register. It shows a change in value
(000001b0) shortly after the reset is released and valid goes high. This
value remains constant for a period. Later, there's activity around the 700
ns mark, but the exact values are difficult to discern from the zoomed-out
view.
 exp_out[23:0]: A 24-bit output signal. It remains at 000000 for a
significant portion and then shows activity towards the end of the
simulation (around 700 ns). Similar to reg_out, the exact values during
this activity are hard to read.
CLK_DIV_inst_CLK_OUT: A clock signal that appears to be a divided
version of the main clk signal. Its frequency is visibly lower than clk

Behavioral simulation: This simulation confirms the intended functional

behavior of your RTL code in an ideal environment without considering any
hardware implementation details or timing delays. It's the first step to ensure
your design's logic is correct is shown in figure 30.

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 Figure 30 Output wave form in Behaviour Simulation

Post-Synthesis Timing Simulation: This is the most realistic simulation. It

incorporates the timing delays introduced by the actual hardware components
and their interconnections after the place and route stages, shown in figure 31.

Figure 31 Output wave form in Post Synthesis Timing Simulation

Post-Synthesis Functional Simulation: This simulation verifies the

functionality of the design after it has been translated into a netlist of hardware
1
primitives. If there are any logical errors introduced during the synthesis
process, they should be caught here. However, it still operates under the
assumption of zero timing delays. The waveforms should ideally match the
behavioral simulation. Any discrepancies would indicate a problem with the
synthesis process or a misunderstanding of how the RTL is being implemented,
shown in figure 32.

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 Figure 32 Output wave form in Post Synthesis Function Simulation

Comparison Across Simulation Types:

Post-Synthesis
Behavioral Post-Synthesis Timing
Feature Functional
Simulation Simulation
Simulation
Realistic timing;
Ideal timing;
Ideal timing; still considers the delays
assumes zero
Timing assumes zero delay introduced by
delay for logic
Accuracy for logic gates and synthesized logic gates
gates and
interconnects. and the physical routing
interconnects.
of interconnects.
Abstract RTL Uses the synthesized
Uses the synthesized
model; does not netlist composed of
Gate-Level netlist with added timing
reflect the actual actual hardware
Detail information extracted
synthesized primitives (LUTs,
from place and route.
hardware. flip-flops, etc.).
Verify the functional
Verify the correctness while
Verify the functional
functional accounting for real-
Purpose correctness of the
correctness of the world timing behavior.
synthesized netlist.
RTL design. Identify potential timing
violations.
Transitions might be
Similar to behavioral, delayed, and glitches or
Clean transitions
but might show minor race conditions due to
at clock edges,
Waveform differences due to the timing issues can be
predictable
Appearance synthesized structure observed. Signal changes
delays based on
(e.g., different might not occur exactly
RTL description.
internal signal order). at the clock edge as in
ideal simulations.
reg_out Shows a clear Should functionally The transitions to the
Behavior transition to match the behavioral new values might be
000001b0 after simulation in terms of delayed compared to the
reset and valid. the sequence of behavioral and
Subsequent values. functional simulations
changes are due to propagation

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 aligned with the
delays.
clock.
Shows a
transition to The activity observed
exp_out
000000 and later Should functionally might be delayed, and
Behavior activity aligned match the behavioral the timing of the value
with the clock simulation. changes will reflect the
based on the RTL actual hardware delays.
functionality.
The divided The frequency
The divided clock's
clock will have a division will be the
transitions will be
CLK_DIV_inst precise frequency same, but the
_CLK_OUT subject to propagation
division based on implementation might
delays within the clock
the RTL involve specific clock
divider logic.
description. divider primitives.

5.2.4 Power Estimation

 Total On-Chip Power: 50.953 W

o This is the estimated total power consumption of the FPGA based on the
synthesized netlist and activity derived from constraints files, simulation
files, or vector less analysis. The note indicates this is an early estimate and
can change after implementation (place and route).
 Design Power Budget: Not Specified
o The target power budget for the design has not been defined. This makes it
difficult to assess if the estimated power consumption is within acceptable
limits.
 Process: typical
o Indicates that the power estimation is based on typical process variations for
the chosen FPGA family.
 Power Budget Margin: N/A
o Since the design power budget is not specified, the margin cannot be
calculated.
 Junction Temperature: 51.6 °C
o This is the estimated temperature of the silicon die (junction) during
operation.
 Thermal Margin: 48.4 °C (85.3 W)
o This represents the difference between the maximum allowable junction
temperature for the device and the estimated junction temperature. A

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 positive thermal margin indicates that the device is operating within its
thermal limits. The value in Watts (85.3 W) likely represents the additional
power dissipation the device could handle before exceeding the maximum
junction temperature.
 Ambient Temperature: 25.0 °C
o The assumed temperature of the surrounding environment.
 Effective θJA: 0.5 °C/W
o This is the junction-to-ambient thermal resistance, indicating how much the
junction temperature will rise above the ambient temperature for every Watt
of power dissipated. A lower θJA indicates better heat dissipation.
 Power supplied to off-chip devices: 0 W
o The design is currently estimated to supply no power to external
components.
 Confidence level: Low
o This is an important indicator. A "Low" confidence level suggests that the
activity information used for power estimation might be incomplete or not
very accurate. This could be due to the use of vector less analysis or
incomplete simulation data. The power estimates are likely to become more
accurate after more detailed simulations or implementation.

Figure 33 Power estimation

On-Chip Power Breakdown:

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The pie chart and the table provide a breakdown of the total on-chip power into
dynamic and static components:

 Dynamic Power (47.362 W, 93%): This is the power consumed due to

the switching activity of the logic gates and interconnects within the
FPGA. It is further broken down into:
o Signals (1.170 W, 2%): Power consumed by the switching of
signals.
o Logic (0.310 W, 1%): Power consumed by the switching of logic
elements (LUTs, etc.).
o DSP (6.574 W, 14%): Power consumed by the Digital Signal
Processing blocks within the FPGA. This suggests your design
utilizes DSP resources significantly.
o I/O (39.308 W, 83%): Power consumed by the input/output pins
of the FPGA. This is the largest contributor to the dynamic
power, indicating high I/O activity or potentially high-capacitance
loads on the I/O pins.
 Device Static Power (3.591 W, 7%): This is the power consumed by the
FPGA even when there is no switching activity. It is primarily due to
leakage currents in the transistors.

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Summary Report

The proposed FPGA-based digital signal processing system incorporates both

High Pass Filter and Low Pass Filter models, designed and implemented using
RTL-level architecture. The system consists of key modules including FIR
filtering, UART transmission, and PCIe interfacing for high-speed
communication. Both filter designs leverage pipelined Multiply-Accumulate
(MAC) structures, offering high throughput and efficient data handling.

The High Pass Filter model utilizes FIR filtering with UART integration and is
implemented using modular RTL blocks including fir_filter, uart_tx,
RTL_MUL, and RTL_ADD. Despite correct RTL structure, waveform analysis
indicates the system has not yet responded correctly to input stimuli—suggesting
further debugging is required for functional completeness.

The Low Pass Filter design shows improved simulation results across
behavioral, post-synthesis functional, and timing simulations. It uses a more
complex MAC pipeline and demonstrates correct data flow, register operation,
and timing behavior.

Power estimations revealed a total on-chip power consumption of 31.063 W

for the high pass model and 50.953 W for the low pass model. The latter also
shows high dynamic power (~93%) with significant I/O activity (83% of
dynamic power), indicating intense external communication or data acquisition
demands.

The integration of PCIe Gen4 using Xilinx Ultrascale+ architecture showcases

readiness for high-bandwidth data transmission, beneficial for real-time, high-
volume signal processing applications.

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Conclusion

Functional Performance and Design Architecture: The low-pass filter (LPF)

design exhibits robust performance across behavioral, post-synthesis, and timing
simulations. Its architecture leverages a pipelined multiply-accumulate (MAC)
structure, ensuring high throughput and efficient data processing. The integration
of UART and PCIe Gen4 interfaces further enhances its capability for high-
speed communication, making it suitable for real-time applications.
Conversely, the high-pass filter (HPF) design, while structurally sound, currently
lacks a functional output. This discrepancy suggests potential issues in control
signal synchronization or testbench configuration, necessitating further
debugging to achieve functional completeness.
Power Consumption Analysis: Power estimation reveals that the LPF design
consumes approximately 50.953 W, with dynamic power constituting about 93%
of the total, and I/O activities accounting for 83% of the dynamic power. In
contrast, the HPF design exhibits a total power consumption of 31.063 W. These
figures underscore the importance of optimizing I/O usage and implementing
power-saving techniques to enhance energy efficiency.
Comparative Analysis with Existing Literature: The observed power
consumption in the LPF design aligns with findings from Parmar et al. (2017),
who reported that efficient FPGA implementations could achieve sampling rates
above 49 MHz with reduced resource utilization. Their design utilized 18
multipliers and achieved a maximum clock frequency of 61.512 MHz,
demonstrating the feasibility of high-performance, low-power FPGA-based
filters. Similarly, the work by John et al. (2021) introduced a floating-point
processing element (FPPE) for FIR filters, achieving a power consumption of
6.526 mW with a delay of 3.487 ns. Their approach emphasizes the potential of
optimized architectures in reducing power consumption while maintaining high-
speed performance. Furthermore, the study by Pandey et al. (2019) on energy-
efficient FIR filter design on Spartan-6 FPGA demonstrated that techniques like
capacitance scaling and frequency scaling could significantly reduce power
consumption, making such designs suitable for green communication
applications.

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 Applications

This system can be used in real-time digital signal acquisition, filtering, and
communication—ideal for applications like:
 Biomedical signals (e.g., ECG filtering and transmission)
 Industrial sensors (filtered sensor data over UART)
 Audio processing and streaming

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 Future Scope
Develop Reconfigurable Filter Architectures: Allow runtime switching
between high pass and low pass configurations using partial reconfiguration or
control FSMs. Hardware Acceleration for AI/ML Tasks: Utilize the
filtering hardware as a pre-processing stage for machine learning models
running on FPGA or SoC platforms, especially in biomedical or industrial
applications. Optimize Power Consumption: Focus on reducing I/O toggling
and logic transitions to minimize dynamic power, particularly by leveraging
clock gating and low-power design strategies. Implement Real-Time Data
Interface: Integrate real-world analog signal acquisition modules (e.g., ADC
interfaces) to validate the system in a practical setting. Expand
Communication Protocols: Extend data transmission capabilities by
integrating Ethernet or wireless modules alongside UART and PCIe for
broader application. Thermal and Power-Aware Layouts: Post-place-and-
route power estimation and thermal simulation should be performed for
precise deployment planning, especially in embedded or portable devices.

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 References

1. Lathi, B. P., & Ding, Z. (2009). Modern Digital and Analog Communication
Systems. Oxford University Press.
2. Xilinx Inc. (2021). Artix-7 FPGAs Data Sheet: DC and AC Switching
Characteristics. [Online]. Available: [Link]
3. Mitra, S. K. (2006). Digital Signal Processing: A Computer-Based
Approach. McGraw-Hill.
4. Xilinx Inc. (2022). Vivado Design Suite User Guide: Synthesis (UG901).
5. Ifeachor, E. C., & Jervis, B. W. (2002). Digital Signal Processing: A
Practical Approach. Pearson Education.
6. Kuon, I., & Rose, J. (2007). “Measuring the gap between FPGAs and
ASICs,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems.
7. Vivado Design Suite. (2023). Xilinx Documentation Navigator. [Online].
Available: [Link]
8. Y. Zhao and L. Liu, “Efficient FPGA Implementation of Transposed Form
FIR Filters for High-Speed Applications,” IEEE Access, vol. 8, pp. 100234–
100245, 2020. doi: 10.1109/ACCESS.2020.2998047.
9. A. Banerjee, R. Singh, and P. Das, “Design and Implementation of Systolic
Array Based FIR Filter on FPGA,” IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol. 29, no. 3, pp. 623–632, 2021. doi:
10.1109/TVLSI.2020.3045651.
10. P. K. Meher, S. Chandrasekaran, and A. Amira, “FPGA Realization of FIR
Filters by Efficient Distributed Arithmetic Architectures,” IEEE
Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 7, pp.
1349–1360, Jul. 2019. doi: 10.1109/TCSI.2019.2912137.
11. S. Kalaiselvan and R. Anitha, “Area-Efficient FIR Filter Implementation
Using Canonical Signed Digit Encoding on FPGA,” Microprocessors and
Microsystems, vol. 76, 2020, Art. no. 103089. doi:
10.1016/[Link].2020.103089.
12. A. Sharma and A. Gupta, “High Throughput Pipelined FIR Filter
Architecture for FPGA-Based DSP Applications,” International Journal of
Electronics and Communications (AEÜ), vol. 135, 2021, Art. no. 153737.
doi: 10.1016/[Link].2021.153737.
13. A. Dandapat, B. Majumdar, and P. Bhattacharya, “FPGA Implementation of
Parallel FIR Filter Architecture for High-Speed Applications,” Journal of
Systems Architecture, vol. 91, pp. 35–45, 2018. doi:
10.1016/[Link].2018.08.001.
14. P. Rane, S. Acharya, and M. Parikh, “Accelerating FIR Filter Design Using
High-Level Synthesis for FPGA-Based Signal Processing,” in Proc. IEEE
Int. Conf. VLSI Design (VLSID), 2019, pp. 245–250. doi:
10.1109/VLSID.2019.00054.
15. S. Gupta and A. Roy, “Fixed-Point Design Techniques for FPGA-Based
Digital Filters,” Procedia Computer Science, vol. 115, pp. 613–620, 2017.
doi: 10.1016/[Link].2017.09.129.

72 | P a g e
16. D. Rao, A. Jain, and S. Kumar, “Design of High-Speed FIR Filter Using
Artix-7 FPGA for DSP Applications,” in Proc. IEEE Int. Conf. Advances in
Computing, Communications and Informatics (ICACCI), 2018, pp. 2039–
2043. doi: 10.1109/ICACCI.2018.8554799.
17. N. Patel and R. Gajjar, “Comparative Analysis of FIR Filter on Xilinx FPGA
Platforms,” in Proc. IEEE Int. Conf. Intelligent Systems and Control (ISCO),
2017, pp. 1–6. doi: 10.1109/ISCO.2017.7856069.
18. V. Joshi and P. Jain, “Low Power FIR Filter Design for Embedded DSP
Applications Using Spartan-6 FPGA,” International Journal of Embedded
Systems, vol. 13, no. 1, pp. 58–66, 2021. doi: 10.1504/IJES.2021.112891.
19. N. Tuan, M. H. Pham, and T. H. Phan, “Multiplier-Less Distributed
Arithmetic Based FIR Filter Architecture for High-Speed Applications,”
Microelectronics Journal, vol. 87, pp. 16–23, 2018. doi:
10.1016/[Link].2018.04.002.
20. A. Goswami, P. Bhattacharya, and B. Majumdar, “Efficient FPGA
Realization of LUT-Based Multiplier Structures for FIR Filters,” Integration,
the VLSI Journal, vol. 68, pp. 143–151, 2019. doi:
10.1016/[Link].2019.02.004.
21. P. Bala, S. Saha, and A. Das, “Pipelining Techniques for Speed
Enhancement in FPGA-Based FIR Filters,” Engineering Science and
Technology, an International Journal, vol. 22, no. 1, pp. 150–158, 2019. doi:
10.1016/[Link].2018.05.007.
22. R. Kumar, D. Singh, and M. Kaur, “High-Performance FIR Filter Design
Using Parallel Pipelining Architecture on FPGA,” Journal of King Saud
University – Computer and Information Sciences, 2021. doi:
10.1016/[Link].2021.02.012.
23. A. Sharma, V. Saini, and P. Verma, “Optimized FIR Filter Design Using
High-Level Synthesis in Vivado HLS,” in Proc. IEEE Int. Conf. Signal
Processing and Integrated Networks (SPIN), 2020, pp. 342–347. doi:
10.1109/SPIN48934.2020.9071176.
24. K. Venkatesh, R. Babu, and S. K. Narayan, “Power-Efficient FIR Filter
Design Using Clock Gating and DVFS on FPGA,” Microprocessors and
Microsystems, vol. 81, 2021, Art. no. 103740. doi:
10.1016/[Link].2021.103740.
25. K. Niranjan, P. Kumar, and R. Sinha, “Resource Sharing Techniques for
Low Power FIR Filter Implementation on FPGA,” Journal of Systems
Architecture, vol. 100, p. 101688, 2019. doi: 10.1016/[Link].2019.101688.
26. R. Sivaram, M. R. Vasanth, and S. D. Venkatesh, “Design and
Implementation of CSD-Based Low Power FIR Filter on FPGA,” AEÜ -
International Journal of Electronics and Communications, vol. 116, 2020,
Art. no. 153063. doi: 10.1016/[Link].2019.153063.

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