MODULE II MEMORY AND PROGRAMMABLE LOGIC 8

Introduction - Basic memory structure – ROM -PROM – EPROM – EEPROM, RAM –

Static and dynamic RAM – Programmable Logic Devices – Programmable Logic
Array (PLA) – Programmable Array Logic (PAL) – Field Programmable Gate Arrays
(FPGA) – Implementation of combinational logic circuits using PLA, PAL. Types of
Memories, Memory Decoding, error detection and correction, RAM and ROMs.
Programmable Logic Array, Programmable Array Logic, Sequential Programmable
Devices.
Topics yet to be covered

I. Sequential Programmable Logic Devices - (SPLD, CPLD,FPGA)

II. RAM – Static and dynamic RAM - Internal construction and Memory Decoding
I. Sequential Programmable Logic Devices
● include both gates and flip flops
● 3 types

a. SPLD (Simple / Sequential Programmable Logic Devices)

b. CPLD (Complex Sequential Programmable Logic Devices)
c. FPGA (Field Programmable Gate Array)
● is a combinational PAL together with D flip a. SPLD
flops. Ex. 2 input 5 wide PAL

● Each section of an SPLD is called a

macrocell, which is a circuit that contains a
sum-of-products combinational logic function
and an optional flip-flop.

● A typical SPLD has 8 to 10 macrocells within

one IC package. All the flip-flops are
connected to the common CLK input, and all
three-state buffers are controlled by the OE macrocell

input.
 a. SPLD
● In addition to programming the AND array, a
macrocell may have other programming
features.
○ the ability to either use or bypass the
flip-flop,
○ the selection of clock edge polarity (+ or -)
○ the selection of preset and clear for the
register
○ the selection of the true value or
complement of an output.

macrocell
● Consists of multiple SPLDs interconnected through b. CPLD
a programmable switch matrix.
● The input–output (I/O) blocks provide the S S S S
connections to the IC pins.
● Each I/O pin can be programmed to act as input or
output.
● The switch matrix receives inputs from the I/O
block and directs them to the individual macrocells.
● Similarly, selected outputs from macrocells are
sent to the outputs as needed.
● Each SPLD typically contains from 8 to 10 S S S S
macrocells, usually fully connected.
● In some cases the macrocell flip-flop is
programmed to act as a D, JK, or T flip-flop.
 Characteristics CPLD FPGA

Logic Cells It has a small number of logic cells. It has a large number of logic cells.

Interconnect Structure It has a fixed interconnect structure. It has a flexible interconnect structure.

Flexibility Less Flexible More Flexible

Cost Low Cost High Cost
Power Consumption Less power consumption Higher power consumption
Reconfigurability Less reconfigurability More reconfigurability
Density Low to medium Medium to high
Flip-flop ratios Less flip-flop ratio More flip-flop ratio
Best for simple applications Best for complex applications
Applications
CLB c. FPGA
IOB
SM
PIC CDN
CDN
BRAM
BRAM

BRAM

BRAM
● “Field-Programmable” → Programmed by the user in the field (after manufacturing)
“Gate Array” → Array of logic gates that can be connected in different ways.

● A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be

configured by the user after manufacturing to implement different digital circuits.

● Unlike fixed-function chips, an FPGA can be reprogrammed many times to perform

various hardware tasks.
1. CLB - Configurable Logic
Blocks
CLB is the heart of FPGA or
Fundamental Building block of
FPGA
a. Look-Up Table (LUT) –
Implement combinational logic
functions.
b. D Flip-flop – provide a
delayed version of the output
of look up table.
c. 2x1 Multiplexer – Select
between direct output or
delayed output.
In general, a LUT with n inputs
comprise of 2n single-bit memory cells
followed by a 2n:1 multiplexer or its
equivalent (say, two 2n-1:1 muxes
followed by one 2:1 mux).
Implementation of boolean function using LUT
2. IOB - Input/output blocks or Input output Pads

a.I/O blocks are placed around the periphery of the FPGA chip to communicate with external
devices easily.

[Link] act as an interface between internal FPGA logic and external devices.

[Link] input signals from outside

a. Send output signals to external systems

3. PIC - Programmable Interconnection network
a. This is the routing structure that connects CLBs, I/O blocks, and other resources to transfer
the data.
[Link] consists of programmable switches and wiring channels.
[Link] allows signals to travel between different logic blocks so that complex digital circuits can be
formed.

4. SM - Switch Matrix / Switch Block

a.A switch matrix controls the routing between logic blocks and interconnection channels.
[Link] enables flexible signal connections within the FPGA.
Switch Matrix
5. CDN - Clock Distribution Network

Provides a global clock signal to all logic blocks to ensure synchronous

operation of sequential circuits.

6. Embedded Memory Blocks for data storage and buffering.(BRAM)

BRAM (Block Random Access Memory) is a dedicated on-chip memory block

inside an FPGA used to store data temporarily during processing. It is faster than
external memory and is built directly into the FPGA fabric.
Key Characteristics of Block RAM (BRAM)

● Embedded Memory: Built directly into the FPGA fabric, allowing for fast, localized data storage.
● Dual-Port Capability: Features two independent ports, allowing simultaneous reading and writing
to different memory addresses.
● Fixed Sizes: Common sizes include 18 Kb and 36 Kb, though multiple blocks can be cascaded to
form larger, customized memory structures.
● Performance: Offers higher performance and lower resource consumption compared to
distributed RAM for large memory needs.
● Configuration: BRAM is synchronous and can be configured in various depths and widths

Example

A typical FPGA BRAM block may have:

● 18 Kb or 36 Kb memory size
18Kb can be configured as 1024 × 18 bits or 2048 × 9 bits
II. Basic memory structure

● Memory unit is a collection of storage cells, together with associated

circuits needed to transfer information into and out of the device.

● The process of storing new information into memory is called write

operation.

● The process of transferring the stored information out of memory is called

read operation.

● The architecture of the memory is such that the information can be

selectively
(i) stored in any of its internal locations
(ii) retrieved from any of its internal locations.
● ROM (Read Only Memory) can perform only read operation. i.e The binary information is already
stored inside the memory and it can be retrieved at any time.

● RAM (Random Access Memory) or R/W memory (Read-Write Memory) can perform both read and
write operations.

● It allows data to be read and written randomly, i.e any location in the memory can be directly
accessed rather than having to read or write the data in a specific order.

● The time it takes to read the binary information from any desired random location is always same.
Similarly the time it takes to write the binary information to any desired random location is always
same. Hence the name Random access memory.

● Whereas the time required to retrieve the information that is stored in magnetic tape depends on the
location of the data. Therefore magnetic tape comes under the classification of sequential access
memory.
 RAM ROM
Both read and write operations are allowed. Only read operation is allowed.
Volatile in nature, which means if the power Nonvolatile, which means stored information is
goes off, the stored information is lost. retained even after removal of the power supply.
Temporary storage Permanent storage
Very fast Slow
High Capacity 1-256 GB per chip Low 4-8 MB
Purpose: RAM holds data for the CPU to ROM holds critical, permanent startup
access immediately (working memory). instructions (booting).
RAM
● Communication between memory and its environment
is achieved through
○ data input lines - n data input lines provide the
information to be stored in memory
○ data output lines -n data output lines supply the
information coming out of memory
○ address selection lines -k address lines specify the
particular word chosen among the many available
○ control lines that specify the direction of transfer
■ The Write input causes binary data to be
transferred into the memory
■ The Read input causes binary data to be
transferred out of memory.
● Size 2k X n
k - address bits and n - data bits

● The 1K×16 memory has 10 bits

in the address and 16 bits in
each word.

● The number of bits in the

address is determined from the
relationship 2k≥m, where m is
the total number of words and k
is the number of address bits
needed to satisfy the
relationship.
Write and Read Operations
● The write signal specifies a transfer-in operation and the read signal specifies a transfer-out operation.
● Steps for write operation
1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data input lines.
3. Activate the write input.
The memory unit will then take the bits from the input data lines and store them in the word specified
by the address lines.
● Steps for read operation
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.
The memory unit will then take the bits from the word that has been selected by the address and apply
them to the output data lines. The contents of the selected word do not change after the read
operation, that is, the read operation is nondestructive.
 Types of RAM

Static RAM (SRAM) consists essentially of

internal latches (made up of several transistors)
that store the binary information.

Dynamic RAM (DRAM) stores the binary

information in the form of electric charges on
capacitors provided inside the chip by MOS
transistors (one transistor and one capacitor for
each cell). The stored charge on the capacitors
tends to discharge with time, and the capacitors
must be periodically recharged by refreshing the
dynamic memory.
 SRAM DRAM

Uses a flip-flop circuit to store data Uses a capacitor and a transistor to store data

SRAM does not require refresh time. DRAM requires periodic refresh time.
SRAM has a lower access time, so it is faster DRAM has a higher access time, so it is slower
compared to DRAM. than SRAM.

Due to complex internal circuitry, less storage is Due to the small internal circuitry in the one-bit
available compared to the same physical size of a memory cell of DRAM, a large storage capacity is
DRAM memory chip. available.
SRAM has a storage capacity of 1 MB to 16 MB in DRAM, which is often found in tablets and
most cases. smartphones, has a capacity of 1 GB to 2 GB

SRAM is costlier than DRAM. DRAM costs less compared to SRAM.

DRAM offers reduced power consumption due to

SRAM requires a constant power supply, which
the fact that the information is stored in the
means this type of memory consumes more power.
capacitor.

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 SRAM DRAM

Good choice for applications that may be exposed

Not suitable for such applications.
to extreme temperatures.

SRAM has low packaging capacity. DRAM has a high packing density.

SRAMs are used as cache memory in computer DRAMs are used as main memory in computer
and other computing devices. systems.

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 SRAM
1. Internal Construction
2. Memory Decoding - Coincident Decoding
 1. Internal Construction of SRAM
● The binary storage cell is the basic building
block of a memory unit. 1 3

● The binary cell stores one bit in its internal

2
latch.
● 3 inputs and 1 output
● The select input enables the cell for reading
or writing, and the read/write input
Binary Storage Cell or Binary Cell (BC)
determines the operation of the cell when it is
selected.
 Write operation
○ provides a path from the input terminal to
the latch. input
○ A 0 in the read/write input makes output 1 3
of Gate 1 same as input. and output of
2
Gate 2 same as complement of input.
○ For example if input =0; S =0 and R=1;
therefore Q=0; Same as input. Thereby
1 0
the data at the input terminal is stored in
Binary Storage Cell or Binary Cell (BC)
the memory cell.
○ This output Q is not available at the output
line as Gate 3 is not enabled.
 Read operation
○ provides a path from the latch to the output
terminal.
0 Q
○ A 1 in the read/write input makes output of Gate 1 3
1 and 2 zero. or gates 1 and 2 are disabled.
2
Hence input is not allowed to pass through the
gates. S=0; R=0; The output Q is same as
0
before. 0 1
○ As read/write input is 1, Gate 3 is enabled and
Binary Storage Cell or Binary Cell (BC)
output of cell is same as Q.(content of the flip
flop). Thereby the data stored in the flip flop is
made available at the terminal when read/write
input = 1.
Logical construction of SRAM

● The internal construction of a RAM of m

words and n bits per word consists of
(i) m×n binary storage cells and
(ii) associated decoding circuits for selecting
individual words.
● This RAM consists of four words of four bits
each and has a total of 16 binary cells.
● The small blocks labeled BC represent the
binary cell with its three inputs (input data,
select, read/write) and one data output.
● A memory with four words needs two address
lines. The two address inputs go through a 2×4
decoder to select one of the four words.
● The decoder is enabled with the memory enable
input.
● When the memory enable is 0, all outputs of the
decoder are 0 and none of the memory words are
selected. The contents of all cells remain
unchanged regardless of the value of the
read/write input.
● When the memory enable is 1, one of the four
words is selected, dictated by the value in the two
address lines.
● Once a word has been selected, the read/write
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input determines the operation.
WRITE OPERATION:
For example if the 4 bit data 1011 is to be
written as the third word(in the location 11)
(i) address inputs 11 is applied to the
address inputs. This will make the
decoder output 1000.
ie. signal at Word 0 become 0.
signal at Word 1 become 0.
signal at Word 2 become 0.
signal at Word 3 become 1.
○ As these signals are connected to select
input of the binary cells in each row,
binary cells in the first 3 rows are not
selected and binary cells in the last row
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are selected.
(ii) data input 1011 is applied to the input lines.
The first binary cell in the last row receives the
msb 1, the next binary cell in the last row
receives 0, the next binary cell in the last row
receives 1 and the last binary cell in the last
row receives 1.

(iii) Apply 0 to the read/write input. This activates

write operation, provides path from the input of
each binary cell to the latch, thereby stores the
input data in the binary cell.

(iv) The binary cells that are not selected are

disabled, and their previous binary values
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remain unchanged.
READ OPERATION:
For example if the 4 bit data in the last row (in
the location 11) is to be read
(i) address inputs 11 is applied to the
address inputs. This will make the
decoder output 1000.
ie. signal at Word 0 become 0.
signal at Word 1 become 0.
signal at Word 2 become 0.
signal at Word 3 become 1.
○ As these signals are connected to select
input of the binary cells in each row,
binary cells in the first 3 rows are not
selected and binary cells in the last row
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are selected.
(ii) Apply 1 to the read/write input. This
activates read operation, provides path
from the latch of each binary cell to
output terminal of the binary cell. This
output is passed through the OR gate
and received as the final output.

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 2. Memory Decoding - Coincident
Decoding
● A decoder with k inputs and 2k outputs requires 2k
AND gates with k inputs per gate.
● The 1K×16 memory has 10 (210=1024=1K) bits in
the address and 16 bits in each word.
● It requires 1024 AND gates with 10 inputs per gate.
● The total number of gates and the number of inputs
per gate can be reduced by employing two
decoders in a two-dimensional selection
scheme.
 2. Memory Decoding - Coincident Decoding
● in a two-dimensional selection scheme two k/2-input (5 input)
decoders are used instead of one k-input (10 input) decoder. Instead of
using a single 10×1024 decoder, two 5×32 decoders are used.

● With the single decoder, we would need 1,024 AND gates with 10
inputs in each. In the two-decoder case, we need 64 AND gates with 5
inputs in each.

● One decoder performs the row selection and the other the column
selection in a two-dimensional matrix configuration.
 2. Coincident Decoding
● Each word within the memory array is selected by
the coincidence of one X line and one Y line. Thus,
each word in memory is selected by the coincidence
between 1 of 32 rows and 1 of 32 columns, for a total
of 1,024 words. Each intersection represents a word
that may have any number of bits.
● As an example, consider the word whose address is
404.
● The 10-bit binary equivalent of 404 is 01100 10100.
This makes X=01100 (binary 12) and Y=10100
(binary 20). The n-bit word that is selected lies in the
X decoder output number 12 and the Y decoder
output number 20. All the bits of the word are
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selected for reading or writing.
 DRAM
1. Internal Construction
2. Memory Decoding - Address Multiplexing
1. Internal Construction of DRAM

For storing information in this cell, transistor T

is turned on and an appropriate voltage is
applied to the bit line. This causes a known
amount of charge to be stored in the capacitor
C.

After the transistor is turned off, due to the

property of the capacitor, it stores the charge.
The stored charge on the capacitors tends to
discharge with time, and the capacitors must
be periodically recharged by refreshing the
dynamic memory.
Advantages of DRAM

● The DRAM cell contains a single MOS transistor and a capacitor.

● Because of their simple cell structure, DRAMs typically have four times the density of SRAMs.
This allows four times as much memory capacity to be placed on a given size of chip.

● The cost per bit of DRAM storage is three to four times less than that of SRAM storage.

● A operational cost of DRAM is less because of the lower power requirement of DRAM cells.

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 2. Memory Decoding - Address Multiplexing
● DRAM chips are available in capacities from 64K to 512M bits.

● Most DRAMs have a 1- bit word size, so several chips have to be combined to produce a
larger word size.

● Because of their large capacity, the address decoding of DRAMs is arranged in a

two-dimensional array, and larger memories often have multiple arrays.

● To reduce the number of pins in the IC package, designers utilize address multiplexing
whereby one set of address input pins accommodates the address components.

● In a two-dimensional array, the address is applied in two parts at different times, with the
row address first and the column address second.

● Since the same set of pins is used for both parts of the address, the size of the
package is decreased significantly. 42
2. Address Multiplexing for a 64K DRAM

● 64K= 64 X 1024 = 65536 words are to be stored

● Requires
○ 16 bit address lines (216=65536) and
○ (a) a 16X 65536 decoder or
(b) two 8X(28) i.e 8X256 decoders and two 8
bit registers one for storing row addresses
and one for storing column address.

● The memory consists of a two-dimensional array of

cells arranged into (28) 256 rows by 256 columns, for
a total of 28×28=216=65536= 65536/1024 = 64K
words.

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2. Address Multiplexing for a 64K DRAM

● There is a single data input line, a single data output line,

and a read/write control, as well as an eight-bit address
input and two address strobes for enabling the row and
column address into their respective registers. The row
address strobe enables the eight-bit row
register, and the column address strobe enables
the eight-bit column register.

● The bar on top of the name of the strobe symbol

indicates that the registers are enabled on the zero level
of the signal (active low).

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2. Address Multiplexing for a 64K DRAM
● The 16-bit address is applied to the DRAM in two
steps using and

Step I:
(i) Initially, both strobes are in the 1 state.

(ii) The 8-bit row address is applied to the address

inputs and is changed to 0. This loads the row
address into the row address register.

(iii) also enables the row decoder so that it

can decode the row address and select one row of
the array.

(iv) After a time equivalent to the settling time of the row

selection, is set to the 1 level.
Step II:
(i) The 8-bit column address is then applied to the address
inputs, and is driven to the 0 state.

(ii) This transfers the column address into the column

register and enables the column decoder. Now the two parts
of the address are in their respective registers, the decoders
have decoded them to select the one cell corresponding
to the row and column address, and a read or write
operation can be performed on that cell.

(iii) must go back to the 1 level before initiating

another memory operation.