BIHAR ENGINEERING UNIVERSITY · B.
TECH 5TH SEM · CODE 104504
Linear Integrated Circuits
& Applications
Complete exam notes — all 6 units · repeated questions · important derivations
OP-AMP IC FABRICATION FILTERS OSCILLATORS
555 TIMER VOLTAGE REGULATORS DAC/ADC
UNIT 1
IC Fabrication
IC Classification
BY FUNCTION BY INTEGRATION SCALE
• Analog/Linear ICs — op-amps, • SSI — <10 gates
amplifiers • MSI — 10–100 gates
• Digital ICs — logic gates, flip- • LSI — 100–1000 gates
flops
• VLSI — >1000 gates
• Mixed-signal — ADC, DAC
Monolithic IC Fabrication — 9 Steps
Monolithic = all components (transistors, resistors, capacitors, diodes) fabricated on a single
silicon chip simultaneously.
1. Silicon wafer preparation — Czochralski method, p-type silicon crystal, sliced into
0.25mm wafers, polished.
2. Epitaxial growth — Thin n-type silicon layer (1–2μm) on p-type substrate using CVD at
1150°C. Forms active device region. Provides isolation.
3. Oxidation — Furnace with O₂/H₂O at 1000°C. Forms SiO₂ (0.5–1μm). Acts as insulating
mask.
4. Photolithography (Masking) — Photoresist → UV exposure through mask →
development → SiO₂ etching with HF. Transfers circuit pattern.
5. Etching — Wet etching (HF) or dry etching (plasma). Creates windows for diffusion.
6. Diffusion of impurities — Boron (p-type) or phosphorus (n-type) at 900–1200°C. Forms
p-n junctions, base, emitter, collector.
7. Ion implantation — Precise alternative to diffusion. Lower temperature, better control of
doping profile.
8. Metallization — Aluminium sputtered and patterned by photolithography. Forms
interconnections and bonding pads.
9. Packaging — Individual dies tested, diced, wire-bonded in DIP/SOIC/QFP packages.
Component Fabrication in Monolithic IC
DIODE RESISTOR
Reverse-biased base-collector junction of Sheet resistance of p-type base diffusion. R
NPN transistor. Collector left open. Good = ρ·L/W. Typical range: 20Ω–50kΩ.
switching characteristics.
CAPACITOR MOSFET
Junction type (reverse-biased p-n) or MOS p-substrate, n+ source/drain, SiO₂ gate
type (SiO₂ between conductors). Limited to insulator, metal gate. Channel forms when
<100pF. Vgs > Vth.
MOST ASKED — 7 MARKS
Draw and explain fabrication steps. Always include cross-section showing: p-substrate → n-
epitaxial → SiO₂ → p+ isolation → n+ emitter. Draw at each step.
UNIT 2
Op-Amp Characteristics
Ideal vs Actual (µA741) Parameters
PARAMETER IDEAL VALUE ΜA741 TYPICAL
Open-loop gain (Aol) ∞ 200,000
Input impedance ∞ 2 MΩ
Output impedance 0 75 Ω
Bandwidth ∞ 1 MHz (ft)
CMRR ∞ 90 dB
Slew rate ∞ 0.5 V/µs
Input offset voltage 0 2 mV
Input bias current 0 80 nA
DC Characteristics
Output error due to Vos: Voe = Vos × (1 + Rf/R1)
Output error due to IB: Voe = IB × Rf
Compensation resistor: Rcomp = R1 || Rf (at non-inverting input)
Offset current: Ios = |IB1 − IB2| → output error = Ios × Rf
AC Characteristics
Slew rate: SR = dVo/dt|max (V/µs)
Max frequency (undistorted): fmax = SR / (2π × Vp)
e.g. SR=0.5V/µs, Vp=10V: fmax = 0.5×10⁶/(2π×10) = 7.96 kHz
GBW product: GBW = Aol × BW = ft = constant = 1 MHz (741)
CMRR: CMRR = Ad/Ac = 20·log(Ad/Ac) dB
Two Golden Rules (from ideal op-amp):
(1) V+ = V− (virtual short — when negative feedback present)
(2) I+ = I− = 0 (no current flows into input terminals)
These two rules solve EVERY op-amp circuit analysis problem.
UNIT 3
Basic Op-Amp Applications
INVERTING AMPLIFIER NON-INVERTING AMPLIFIER
Vout = −(Rf/Rin)×Vin Vout = (1+Rf/R1)×Vin
Av = −Rf/Rin Av = 1+Rf/R1 ≥ 1
Zin = Rin Zin = very high
Inverting summing amp: Vout = −Rf(V1/R1 + V2/R2 + V3/R3)
Integrator: Vout = −(1/RC)∫Vin dt → slope −20dB/dec
Differentiator: Vout = −RC·dVin/dt → slope +20dB/dec
Voltage follower (buffer): Rf=0, R1=∞ → Av = 1, Zin = ∞, Zout = 0
DESIGN TRICK — WEIGHTED SUMMER (PYQ Q8B)
Vo = 0.2V1 + 2V2 + 5V3: Set Rf=10kΩ → R1=50kΩ, R2=5kΩ, R3=2kΩ (inverting). Add unity
inverter for positive output.
UNIT 4
Advanced Op-Amp Applications
Instrumentation Amplifier
Vout = (1 + 2R/RG) × (V2−V1) × Rf/R1
Gain set by single resistor RG. Very high CMRR. Used in sensor/bridge
measurements.
Active Filters
TYPE TRANSFER FUNCTION ROLLOFF
1st order LPF H(s) = Ao·ωc/(s+ωc) −20 dB/dec
1st order HPF H(s) = Ao·s/(s+ωc) +20 dB/dec below ωc
2nd order LPF (Sallen- H(s) = Ao·ωn²/(s²+2ζωns+ωn²) −40 dB/dec
Key)
2nd order LPF cutoff: fo = 1/(2π√(R1·R2·C1·C2))
Butterworth: Q=0.707, ζ=0.707, Ao=1.586, Rf/R=0.586
Design for fo: Set R1=R2=R, C1=C2=C → C = 1/(2π·fo·R)
Comparator / Schmitt Trigger
Upper threshold: VUT = +Vsat·R1/(R1+R2)
Lower threshold: VLT = −Vsat·R1/(R1+R2)
Hysteresis = VUT − VLT = 2·Vsat·R1/(R1+R2)
R-2R Ladder DAC
Vout = −(Rf/R)·(Vref/2^N)·(b1·2^(N-1)+b2·2^(N-2)+...+bN)
Resolution (LSB) = Vref/2^N
Advantages over weighted: only 2 resistor values, scalable to any N
bits.
UNIT 5
Special ICs
555 Timer — Pin Diagram Memory
Pin 1=GND · 2=Trigger(−) · 3=Output · 4=Reset · 5=Control · 6=Threshold
· 7=Discharge · 8=Vcc
Astable Mode (Square wave generator)
tHigh = 0.693(RA+RB)C
tLow = 0.693·RB·C
f = 1.44/((RA+2RB)C)
Duty cycle D = (RA+RB)/(RA+2RB) [always >50% without diode trick]
Monostable Mode (One-shot)
Trigger: negative pulse at pin 2 (< Vcc/3)
tp = 1.1·RA·C (output HIGH pulse width)
IC 566 VCO / IC 565 PLL
VCO (566): fo = 2(Vcc−Vc)/(R1·C1·Vcc)
PLL (565) lock range: fL = ±8fo/Vcc
PLL free-running: fo = 1/(3.7·R1·C1)
UNIT 6
Application ICs — Voltage Regulators
LM78XX (FIXED +VE) LM79XX (FIXED −VE)
7805=+5V, 7808=+8V, 7812=+12V, 7905=−5V, 7912=−12V, 7915=−15V. Same
7815=+15V. 3-pin: IN(1), GND(2), OUT(3). pin layout as 78XX but for negative supply.
Min input = Vout+2.5V
LM317 — Adjustable Positive Regulator
Vout = 1.25(1 + R2/R1) [Vref = 1.25V between OUT and ADJ]
Range: 1.25V to 37V, up to 1.5A
Set R1=240Ω (standard). Then: R2 = R1(Vout/1.25 − 1)
Example — Vout=9V: R2 = 240(9/1.25−1) = 240×6.2 = 1488Ω ≈ 1.5kΩ
LM723 — Variable Regulator
Low voltage (Vo < 7.15V): Vo = Vref·R2/(R1+R2)
High voltage (Vo > 7.15V): Vo = Vref(1+R1/R2)
Current limit sense resistor: Rsc = 0.6/Imax
SMPS vs Linear Regulator Comparison
PARAMETER LINEAR REGULATOR SMPS
Efficiency 30–50% (Vout/Vin×100%) 70–95%
Size/Weight Heavy (large transformer) Small and light
Output noise Very low High (switching noise)
Cost Low Higher
Thermal dissipation High — needs large heatsink Low
ICL8038 Function Generator
Generates sine, square and triangle waves simultaneously
fo = 0.3/(R·C) (RA=RB=R, 50% duty cycle)
Range: 0.001 Hz to 300 kHz. Sine distortion <1%
LM380 AUDIO AMPLIFIER
Fixed gain Av=50 (34dB) · Supply 10–22V · Max output power 2.5W · Input impedance 150kΩ
Repeated Questions — Appear Almost Every Year
REPEATED Monolithic IC fabrication steps with cross-section diagram 7 marks
9 steps: Wafer prep → Epitaxial growth → Oxidation → Photolithography → Etching →
Diffusion → Ion implantation → Metallization → Packaging.
Cross-section layers (bottom to top): p-substrate → n-epitaxial layer → SiO₂ → p+
isolation walls → n-type collector → p-type base → n+ emitter → Al metallization.
Epitaxial growth detail: n-type layer grown by CVD at 1150°C using SiCl₄ + H₂ gas.
Provides electrical isolation between adjacent components in same substrate.
Diffusion detail: Two-step — pre-deposition at ~1000°C then drive-in at higher temp.
Base region: boron (p-type). Emitter: phosphorus (n+ type).
REPEATED DC characteristics of op-amp — Vos, IB, Ios and their 7 marks
compensation
Voe from Vos: Voe = Vos(1+Rf/R1) [amplified by closed-loop gain]
Voe from IB: Voe = IB × Rf [reduced by Rcomp = R1||Rf at +input]
Voe from Ios: Voe = Ios × Rf [due to mismatch IB1≠IB2]
Input Offset Voltage (Vos): ~2mV for 741. Caused by mismatch in diff pair transistors.
Compensated using 10kΩ pot between pins 1 and 5 (offset null pins).
Input Bias Current (IB): ~80nA for 741. Average of two base currents. Compensate by
adding Rcomp = R1||Rf at non-inverting input — makes error voltages equal and cancel.
Input Offset Current (Ios): ~20nA for 741. Difference |IB1−IB2|. Minimized by matched
transistors (JFET input op-amps have much lower IB and Ios).
REPEATED 555 timer monostable multivibrator — design with 7 marks
calculations (PYQ 2024 Q4(a))
Circuit: RA between Vcc and pins 6,7. Capacitor C between pin 6 and GND. Trigger at
pin 2 (active LOW). Output at pin 3. Pin 4 (Reset) to Vcc. Pin 5 via 0.01µF to GND.
Operation: Normally output LOW, C discharged. Negative trigger (<Vcc/3) at pin 2 →
flip-flop sets → output HIGH → discharge transistor OFF → C charges through RA
toward Vcc → when Vc reaches 2Vcc/3 → flip-flop resets → output LOW → C
discharges rapidly.
tp = 1.1 × RA × C
Example: RA=100kΩ, C=10µF → tp = 1.1×10⁵×10⁻⁵ = 1.1 seconds
Design for tp=5ms: Choose C=1µF → RA = tp/(1.1×C) = 5×10⁻³/(1.1×10⁻⁶) =
4.55kΩ ≈ 4.7kΩ
Applications: Time delay, frequency divider, missing pulse detector, touch switch,
debounce circuit.
REPEATED LM317 adjustable voltage regulator — working and design 7 marks
for given Vout
Pins: Input (1), Output (2), Adjustment/ADJ (3).
Working: Internal 1.25V Vref maintained between OUT and ADJ pins. Current through
R1 = Vref/R1. Adjusting R2 sets output level.
Vout = 1.25(1 + R2/R1) [Iadj negligible]
Design for Vout = 12V: R1=240Ω
R2 = R1(Vout/1.25−1) = 240×(12/1.25−1) = 240×8.6 = 2064Ω ≈ 2.2kΩ
Design for Vout = 5V: R2 = 240×(5/1.25−1) = 240×3 = 720Ω ≈ 750Ω
REPEATED Slew rate — definition, cause, effect, and max frequency 7 marks
calculation
SR = dVo/dt|max (V/µs) [741: 0.5 V/µs]
Max undistorted freq: fmax = SR/(2π×Vp)
At Vp=1V: fmax = 0.5M/(2π×1) = 79.6 kHz
At Vp=5V: fmax = 0.5M/(2π×5) = 15.9 kHz
At Vp=10V: fmax = 0.5M/(2π×10) = 7.96 kHz
Cause: Internal 30pF compensation capacitor charges at constant rate I/C where
I~19µA. SR = 19µA/30pF = 0.63V/µs.
Effect: If output tries to change faster than SR → output becomes triangular wave →
harmonic distortion. Called slew-rate limiting.
Solution: Use high-SR op-amps: TL071=13V/µs, LF351=10V/µs, AD811=2500V/µs.
REPEATED R-2R Ladder DAC — circuit, working, advantages over 7 marks
weighted resistor DAC
Weighted resistor DAC problem: N-bit requires resistors R, 2R, 4R, ... 2^(N-1)R. For 8-
bit: ratio 128:1 — impossible to match accurately.
R-2R Ladder: Only two values regardless of N bits. Each node sees Thevenin resistance
= R. Each bit switch contributes binary-weighted current.
4-bit R-2R output (Rf=R):
Vout = −Vref(b1/2 + b2/4 + b3/8 + b4/16)
For input 1010 (decimal 10): Vout = −Vref(1/2+0+1/8+0) = −Vref×0.625
Resolution = Vref/2^N = Vref/16 per bit
Advantages: Only R and 2R values (easy precision matching), scalable, monotonic,
high accuracy, used in all modern DACs.
REPEATED Compare SMPS and linear regulators — efficiency and 7 marks
thermal (PYQ 2024 Q9(c))
Linear efficiency: η = Vout/Vin × 100%
e.g. Vin=12V, Vout=5V → η = 5/12 = 41.7% (58.3% wasted as heat)
SMPS typical efficiency: 70–95%
Linear regulator: Pass transistor in active region. Excess voltage (Vin−Vout) dropped as
heat. Power loss = (Vin−Vout)×IL. Needs large heatsink. Low EMI, simple design.
SMPS: Transistor switches ON/OFF at 20kHz–1MHz. Energy stored in inductor/
transformer. Duty cycle controls output. Tiny heatsink needed. Generates switching noise
requiring EMI filters.
Summary: Use linear for low-noise audio/analog. Use SMPS for battery-powered
devices, high power applications where efficiency matters.
Important Questions — High Probability for Exam
IMPORTANT Design second-order LPF and derive transfer function 7 marks
(PYQ 2024 Q6(b))
Sallen-Key 2nd order LPF: Two RC sections with op-amp unity gain (or gain Ao).
Positive feedback from output to non-inverting input through C2.
H(s) = Ao·ωn² / (s² + (ωn/Q)·s + ωn²)
ωn = 1/√(R1·R2·C1·C2) [natural frequency]
Q = √(R1·R2·C1·C2)/[C2(R1+R2)] [quality factor]
Butterworth: Q=0.707, ζ=0.707, Ao=1.586, Rf/R=0.586
Design for fo=1kHz, R1=R2=10kΩ:
C = 1/(2π×10³×10⁴) = 15.9nF ≈ 16nF
Rf = 0.586×R = 0.586×10k = 5.86kΩ ≈ 5.6kΩ
IMPORTANT IC 723 variable voltage regulator — working and circuit 7 marks
(PYQ 2024 Q7(a))
LM723 internal blocks: Voltage reference (Vref=7.15V), error amplifier (compares Vref
with feedback), series pass transistor (NPN controls output current), current limiting
transistor.
Low voltage (Vo < 7.15V): Vo = Vref × R2/(R1+R2)
High voltage (Vo > 7.15V): Vo = Vref × (1+R1/R2)
Current limit resistor: Rsc = 0.6/Imax
e.g. Imax=500mA → Rsc = 0.6/0.5 = 1.2Ω
Advantages over 78XX: Adjustable output (2V–37V), programmable current limiting,
foldback protection possible, external pass transistor for higher current capability.
CALCULATION Design adder: Vo = 0.2V1 + 2V2 + 5V3 (PYQ 2024 Q8(b)) 7 marks
Two-stage approach (inverting summer + unity inverter):
Stage 1: Choose Rf = 10kΩ
Coefficient 0.2 → R1 = Rf/0.2 = 10k/0.2 = 50kΩ
Coefficient 2 → R2 = Rf/2 = 10k/2 = 5kΩ
Coefficient 5 → R3 = Rf/5 = 10k/5 = 2kΩ
Stage 1 output: V'o = −(0.2V1+2V2+5V3)
Stage 2 (unity gain inverter, R=Rf=10kΩ):
Vo = +(0.2V1+2V2+5V3) ✓
Verify: Rf/R1=10k/50k=0.2✓ Rf/R2=10k/5k=2✓ Rf/R3=10k/2k=5✓
IMPORTANT List ideal op-amp characteristics + two golden rules 7 marks
(PYQ 2024 Q9(b))
• Infinite open-loop gain (Aol=∞) — amplifies infinitesimally small differential
signals
• Infinite input impedance (Rin=∞) — no current drawn from source
• Zero output impedance (Ro=0) — drives any load without voltage drop
• Infinite bandwidth (BW=∞) — amplifies all frequencies equally
• Infinite CMRR — perfect common-mode rejection
• Zero input offset voltage — output=0 when both inputs=0
• Zero input bias current — no DC current into inputs
• Infinite slew rate — instantaneous response to input change
• Zero drift — parameters stable with temperature
• Infinite PSRR — output unaffected by supply variation
Two golden rules:
1. V+ = V− (virtual short — when negative feedback present)
2. I+ = I− = 0 (no current into either input terminal)
These two rules solve EVERY op-amp circuit analysis problem.
IMPORTANT Positive clamper using op-amp and diode — circuit and 7 marks
waveforms (PYQ 2024 Q2(b))
Clamper principle: Shifts DC level of waveform without changing shape. Positive
clamper shifts waveform up so minimum = 0 (or reference).
Precision clamper circuit: Input → series capacitor C → inverting input. Diode from op-
amp output to inverting input (feedback diode). Non-inverting input at Vref. When output
goes negative: diode conducts, charges C to peak-negative voltage. Virtual ground
maintained at summing point.
For sinusoidal input Vm·sin(ωt), positive clamper:
Vout = Vm·sin(ωt) + Vm
Minimum = 0V, Maximum = 2Vm
Waveforms: Input = sine from −Vm to +Vm. Output = sine from 0 to 2Vm (entire wave
above zero axis). Shape unchanged.
IMPORTANT Fabrication flow for monolithic IC with diode and resistor 7 marks
(PYQ 2024 Q3(b))
1. p-type substrate — 1–10 Ω·cm, 0.25mm thick
2. Epitaxial growth — 5µm n-type layer (phosphorus, 0.5Ω·cm), CVD at 1150°C
3. Oxidation — SiO₂ 0.5µm for first mask
4. Isolation diffusion — p+ boron diffusion to substrate — creates isolated n-type
islands
5. Second oxidation — regrow SiO₂ for component windows
6. Anode/base diffusion — p-type boron creates diode anode AND resistor body in
n-island
7. Cathode diffusion — n+ phosphorus creates diode cathode
8. Resistor contacts — ohmic contacts at two ends. R = ρ×L/(W×t)
9. Metallization — Al deposited and patterned to interconnect diode + resistor
10. Passivation — protective SiO₂/Si₃N₄ layer. Bonding pads exposed.
IMPORTANT ICL8038 triangular waveform generator circuit and 7 marks
calculations (PYQ 2024 Q2(a))
ICL8038 key pins: Pin 2=sine out, 3=square out, 9=triangle out, 8=Vcc, 4=RA, 5=RB,
10=C, 6=FM bias, 11,12=sine adjust.
For 50% duty cycle (RA=RB=R):
fo = 0.3/(R×C)
Example: R=10kΩ, C=1nF → fo = 0.3/(10⁴×10⁻⁹) = 30 kHz
Example: R=100kΩ, C=10nF → fo = 0.3/(10⁵×10⁻⁸) = 300 Hz
Triangle amplitude ≈ Vcc/3 (peak-to-peak)
Design steps: (1) Choose fo. (2) Select C (0.001µF–1µF). (3) Calculate R = 0.3/(fo×C).
(4) Set RA=RB=R. (5) Adjust pins 11,12 for minimum sine distortion. (6) Triangle at pin 9,
square at pin 3.
PYQ 2024 — MCQ Answers (Code 104504)
MCQ Q1 — All 10 MCQ answers with explanations 2×7=14
(a) High slew rate — SR > 2πfVp needed to avoid distortion at high
frequencies
(b) Forming high-purity single-crystal layers — epitaxial growth creates
pure active device region
(c) Ratio of feedback and input resistors — Av = −Rf/Rin for inverting
amplifier
(d) Comparator — compares analog voltage to reference, outputs digital
HIGH or LOW
(e) Built on a single crystal substrate — "monolithic" = single stone/
chip
(f) Common Mode Rejection Ratio — CMRR = Ad/Ac = 20·log(Ad/Ac) dB
(g) Adjustable voltage regulator — LM317 adjustable from 1.25V to 37V
(h) Switching Mode Power Supply — high efficiency switching regulator
(i) Square wave generator — 555 in astable mode generates square wave
(j) Integrator and comparator — integrator makes triangle from square;
comparator makes square from triangle
LINEAR INTEGRATED CIRCUITS & ALL 6 UNITS · REPEATED QUESTIONS ·
APPLICATIONS · CODE 104504 · BEU 5TH SEM IMPORTANT QUESTIONS · PYQ 2024 ANSWERS
2024