VLSI DESIGN AND TESTING

(BEC602)
VI SEMESTER
2022 SCHEME AY 2025-26

Prepared by:
Dr. Hashinur Islam
Assistant Professor
Dept. of ECE

Department of Electronics and Communication Engineering

HKBK College of Engineering

(Approved by AICTE, Affiliated to VTU, Belagavi)
S. No. 22/1, Nagawara, Bengaluru-560045, Karnataka, India
[Link] Email: info@[Link]
Phone: +91 80 25441722/ 3744/ 3690/ 3698 Fax: +91 80 25443813
HKBK College of Engineering VLSI Design and Testing (BEC602)

HKBK College of Engineering, Bengaluru

Department of Electronics & Communication Engineering
2022 Scheme AY 2025-26
___________________________________________________________________________
BEC602 – VLSI Design and Testing
Module-IV

Syllabus:

CMOS Circuit and Logic Design: Introduction, CMOS Logic structures, CMOS Complementary
logic, Pseudo n-MOS logic, Dynamic CMOS logic, Clocked CMOS Logic, Cascade Voltage
Switch logic, Pass transistor Logic, Electrical and Physical design of Logic gates, The inverter,
NAND and NOR gates, Body effect, Physical Layout of Logic gates, Input output Pads. [Text 1:
5.1,5.2,5.2.1, , 5.2.2, 5.2.3, 5.2.4, 5.2.6, 5.2.8, 5.3,5.3.1,5.3.2, 5.3.4 ,5.3.8,5.5]

Introduction:

In earlier chapters, CMOS transistors were assumed to behave as ideal switches. However, real
CMOS circuits must consider non-ideal behavior and layout constraints when designing logic
gates.

In this chapter, the focus is on:

 Designing complementary CMOS logic circuits

 Understanding alternate CMOS logic structures
 Studying performance optimization techniques

Two major phases of CMOS circuit design are:

1. Circuit (functional) design

2. Layout (physical) design

1. Circuit (Functional) Design

 Selecting the appropriate logic structure.

 Determining transistor sizes.
 Ensuring correct logic operation.

2. Layout (Physical Design)

 Converting schematic circuits into physical layouts.

 Optimizing area and performance.
 Minimizing parasitic capacitance and resistance.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 2 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

These two phases are closely related because layout directly influences circuit performance.

CMOS Logic Structures

In some cases, a fully complementary static CMOS gate may not be the most efficient solution
due to:

 Large silicon area

 Slower operation
 High transistor count

Therefore, alternative CMOS logic structures are used to improve:

 Speed
 Area efficiency
 Power consumption
 Circuit stability

Different CMOS logic structures include:

1. Complementary CMOS Logic

2. Pseudo-NMOS Logic
3. Dynamic CMOS Logic

CMOS Complementary Logic

Complementary CMOS logic is the standard logic family used in VLSI design.

Typical gates include:

 Inverter
 NAND gate
 NOR gate

Principle

Complementary CMOS uses two transistor networks:

1. Pull-Up Network (PUN)

o Implemented using pMOS transistors

o Connects output to VDD

2. Pull-Down Network (PDN)

o Implemented using nMOS transistors

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 3 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

o Connects output to ground

Fig. 4. 1: Complementary CMOS uses two transistor networks

Key Characteristics

 Only one network conducts at a time

 No direct path between VDD and GND
 Very low static power consumption

Advantages

 High noise immunity

 Low static power consumption
 Full logic swing

Disadvantages

 Larger transistor count

 Increased chip area for complex gates

For example, a complex gate implementing the function: ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅

( ) ( ) is used as a
basis for comparison between various logic families.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 4 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 2: CMOS Complementary Logic

Pseudo-nMOS Logic

Pseudo-nMOS logic is an extension of the nMOS logic family.

In this structure:

 A single pMOS transistor acts as a load.

 The nMOS network performs the logic function.

Structure

 pMOS transistor is always ON

 nMOS transistors form the pull-down network

Unlike complementary CMOS:

 pMOS is not controlled by input

 It acts as a load transistor

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 5 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Operation

When input activates nMOS network:

 Output is pulled LOW

When nMOS network is OFF:

 Output becomes HIGH through the pMOS load.

This logic is called ratioed logic because correct operation depends on the size ratio between
pMOS and nMOS transistors.

Advantages

 Reduced transistor count

 Smaller area
 Simpler circuit

Disadvantages

 Static power dissipation

 Lower noise margin
 Slower switching due to continuous current

Fig. 4. 3: Pseudo - nMOS Logic

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 6 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Dynamic CMOS Logic

Dynamic CMOS logic is widely used in high-speed VLSI circuits. Dynamic CMOS logic uses
clock signals to control operation.

Fig. 4. 4: Dynamic CMOS Logic

A basic dynamic gate consists of:

1. Precharge transistor
2. Evaluate transistor
3. nMOS logic network

Operation of Dynamic Logic

The dynamic CMOS gate operates in two main phases, controlled by the clock signal ϕ:

1. Precharge Phase (Clock = 0)

 A pMOS transistor charges the output node

 Output node is charged to VDD
 Precharge transistor turns ON
 Evaluate transistor OFF

2. Evaluation Phase (Clock = 1)

 Precharge transistor turns OFF

 nMOS network evaluates input logic

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 7 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

If the pull-down network conducts:

 Output discharges to ground

If it does not conduct:

 Output remains HIGH

Advantages

 Very high speed

 Reduced transistor count
 Good for large logic functions

Disadvantages

 Sensitive to noise
 Requires clock synchronization
 Cannot easily cascade without special techniques

Cascading Problem in Dynamic Logic

Dynamic gates cannot be directly cascaded because:

 Precharged nodes may discharge incorrectly

 Evaluation errors may occur

This phenomenon is known as charge sharing or erroneous discharge.

To solve this, clocked dynamic logic structures such as 4-phase logic are used.

Fig. 4. 5: Cascaded Dynamic CMOS

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 8 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

4-Phase Dynamic Logic

Two types are commonly used:

Type-A Logic

 Uses four clock phases

 Ensures proper evaluation order

Type-B Logic

 Simplified structure
 Fewer clocking restrictions

Advantages of Dynamic Logic

 High speed operation

 Lower transistor count
 Reduced chip area

Disadvantages

 Clock synchronization required

 Noise sensitivity
 Charge leakage problems

Fig. 4. 6: 4- Phase Logic

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 9 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Key Comparison of Logic Styles

Table 4. 1: Key Comparison of Logic Styles

Feature Complementary CMOS Pseudo-NMOS Dynamic CMOS

Power Very low High Low
Speed Moderate High Very high
Area Large Small Small
Noise margin High Low Moderate
Transistor Count High Low Very Low

Clocked CMOS Logic (C²MOS)

Clocked CMOS logic is a clock-controlled logic style used to reduce dynamic power
dissipation in CMOS circuits.

It operates by controlling signal propagation using clock signals.

Fig. 4. 7: Clocked CMOS Logic (C²MOS)

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 10 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Structure

A clocked CMOS logic gate contains:

 Logic block
 Clock-controlled transistors
 Pull-up and pull-down networks

The clock signal determines when the logic block can evaluate or hold its value.

Operation

Two clock phases are used:

1. Evaluation Phase

 Clock enables the logic network.

 Output node evaluates based on the input signals.

2. Hold Phase

 Clock disables the logic network.

 Output state is preserved.

Advantages

 Reduced dynamic power consumption

 Improved noise immunity
 Controlled signal propagation

Limitations

 Only non-inverting structures can be easily implemented.

 Buffering may be required for signal propagation.

CMOS Domino Logic

Domino logic is a modified dynamic CMOS logic used to cascade multiple dynamic stages.

Structure

A domino gate consists of:

1. Dynamic logic block

2. Clocked precharge transistor
3. Static inverter (buffer)

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 11 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Principle

During the precharge phase:

 Dynamic node is charged to (VDD)

During the evaluation phase:

 Logic network evaluates inputs.

 Output may discharge.

The inverter ensures correct signal propagation between stages.

Domino Logic Operation

Steps:

1. Precharge node is charged to HIGH.

2. During evaluation, logic network may discharge the node.
3. The inverter converts the dynamic output to a stable logic level.

Characteristics

 Allows cascading of dynamic gates

 Faster than static CMOS
 Requires clock synchronization

Limitations

 Only non-inverting logic is possible

 Sensitive to noise and charge leakage

Cascade Voltage Switch Logic (CVSL)

CVSL is a differential CMOS logic style.

It uses:

 Two complementary outputs

 Cross-coupled pMOS transistors
 nMOS logic network

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 12 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 8: Cascade Voltage Switch Logic (CVSL)

Structure

 Uses two complementary NMOS networks

 Two PMOS load transistors
 Produces true and complementary outputs

Operation

1. Complementary input signals are applied.

2. nMOS networks determine which output node discharges.
3. Cross-coupled pMOS transistors reinforce the correct output.

Advantages

 High switching speed

 Full output swing
 Differential outputs improve noise immunity

Disadvantages

 Increased circuit complexity

 Requires complementary inputs

Modified Domino Logic

Modified domino logic is an improved version of domino logic. Modified domino logic
alternates p-type and n-type dynamic blocks.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 13 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Working Principle

 First stage uses n-transistor dynamic logic

 Second stage uses p-transistor dynamic logic

This arrangement reduces cascading problems in dynamic logic.

Key Features

 Alternating pMOS and nMOS logic stages

 Eliminates the need for buffers
 Improves noise margin

Advantages

 Smaller area than fully static gates

 Higher speed due to smaller parasitic capacitance
 Reduced glitches when properly designed

Disadvantages

 Requires careful clock design

 More complex than static CMOS

Pass Transistor Logic

Pass transistor logic implements logic functions using transistors as switches to pass signals
rather than pulling nodes to VDD or ground.

Fig. 4. 9: nMOS PTL

Basic Principle

Instead of implementing full pull-up and pull-down networks, signals are passed through
transistors.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 14 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Example

XOR function implementation using pass transistors.

Advantages

 Reduced transistor count

 Smaller area
 Potentially faster circuits

Disadvantages

 Voltage degradation
 Reduced noise margin
 Additional buffering sometimes required

XOR Implementation Using Pass Transistors

Typical XOR logic function:

Pass transistor networks select inputs based on control signals.

Example:

 If B=0, output = A
 If B=1, output = ̅

XOR Pass Transistor Truth Table

Table 4. 2: XOR Pass Transistor Truth Table

A B Output
0 0 0
0 1 1
1 0 1
1 1 0

Advantages of Dynamic Logic Styles

Dynamic logic structures offer several benefits.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 15 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Key Advantages

1. Smaller area compared to static gates

2. Reduced parasitic capacitance
3. Higher switching speed
4. Efficient implementation of complex logic

Electrical and Physical Design of Logic Gates

In CMOS design, the physical layout of MOS gates strongly influences:

 Parasitic capacitance
 Switching speed
 Propagation delay
 Power dissipation

Therefore both electrical design and physical layout design must be considered simultaneously.

The section focuses on how circuit schematics are translated into efficient layout structures.

The CMOS Inverter

The CMOS inverter is the simplest and most fundamental logic gate.

CMOS Inverter Structure

A CMOS inverter consists of:

 pMOS transistor connected to power supply VDD (pull-up network)

 nMOS transistor connected to ground VSS (pull-down network)
 Gates connected as input
 Drains connected as output

Operation

Input pMOS nMOS Output

0 ON OFF 1
1 OFF ON 0

The inverter produces a full voltage swing between VDD and VSS.

Schematic to Layout Conversion

A symbolic representation of the inverter is used before creating the layout.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 16 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 10: CMOS Inverter Circuit

Important layout rules

1. Diffusion layers form source and drain regions.

2. Polysilicon crossing diffusion forms the gate.
3. Metal layers are used for interconnections.
4. Power lines VDD and VSS are routed in metal.

Typical layout rules:

 pMOS transistors are placed in n-well

 nMOS transistors are placed in p-substrate
 Power rails run horizontally
 Input gate uses polysilicon

Various Forms of Inverter Layout

Different layout arrangements are possible depending on:

 Routing requirements
 Layout density
 Speed optimization

Typical layouts include:

 Vertical transistor orientation

 Horizontal transistor orientation
 Parallel layouts
 Multi-finger layouts

These variations allow designers to optimize capacitance and resistance.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 17 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 11: Symbolic layout representation of CMOS Inverter

The corresponding layout is shown in figure below.

Fig. 4. 12: Standard Layout of CMOS Inverter

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 18 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

An alternative layout is shown in figure below where the transistors are aligned horizontally.

Fig. 4. 13: Layout of CMOS Inverter with horizontal transistors

Fig. 4. 14: Alternative CMOS inverter layout with vertical polysilicon

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 19 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 15: CMOS inverter layout with diffusion power and ground

Fig. 4. 16: CMOS inverter layout using additional metal layers

Parallel Inverter Layouts

In high-drive circuits, multiple transistors may be placed in parallel.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 20 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

A large inverter can be created by parallelizing smaller inverters. Source and drain regions are
merged to reduce resistance. The diffusion regions are stitched together to minimize parasitic
capacitance.

Fig. 4. 17: Large CMOS inverter using parallel transistors

Further improvements can be achieved by placing transistors back-to-back to optimize drain

capacitance.

Fig. 4. 18: Back-to-Back transistor placement for large inverters

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 21 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 19: Star connection for CMOS inverter layout optimization

Advantages:

 Reduces source/drain resistance

 Improves current drive capability
 Reduces delay

The effective transistor width increases while maintaining manageable layout dimensions.

NAND and NOR Gates Layout

The same inverter layout principles are extended to multi-input gates.

NAND Gate Layout

For a 2-input NAND gate:

 nMOS transistors are connected in series

 pMOS transistors are connected in parallel

Layout Characteristics

 nMOS devices share diffusion regions

 Polysilicon lines represent inputs
 Metal connects output node

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 22 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Figure below represents the direct translation of schematic into layout of a 2-input NAND gate.

Fig. 4. 20: Basic layout translation of a 2-input NAND gate

By orienting the transistors horizontally, we obtain the layout shown in figure below, which is
cleaner and more compact.

Fig. 4. 21: Optimized layout for NAND Gate

NOR Gate Layout

For a 2-input NOR gate:

 nMOS transistors are in parallel

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 23 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

 pMOS transistors are in series

The layout structure differs slightly from NAND because of the transistor arrangement.

Fig. 4. 22: Symbolic layout of NOR gate

An alternative NOR layout is shown in figure below, where the connection to the parallel
transistors is optimized.

Fig. 4. 23: An alternative layout of NOR gate

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 24 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Body Effect

The body effect refers to the modification of the threshold voltage (Vt) due to a voltage
difference between the source and substrate. Specifically, the threshold voltage variation can be
expressed as:

(√ √ )

where

 = threshold voltage
 = zero bias threshold voltage
 = source-to-body voltage
 = body effect coefficient

Impact of Body Effect

When several transistors are connected in series:

 The source voltage of upper transistors increases

 VSB increases
 Threshold voltage increases

This reduces transistor drive strength.

Minimizing Body Effect

Body effect can be reduced by:

 Minimizing internal node capacitance

 Optimizing transistor ordering
 Reducing number of series transistors

Physical Layout of Logic Gates

The physical layout of CMOS logic gates determines how transistors are arranged on silicon
while minimizing:

 Area
 Parasitic capacitances
 Routing complexity

Most CMOS layouts use a single row of transistors where:

 nMOS transistors share common diffusion regions

 pMOS transistors share common diffusion regions

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 25 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

 Gate connections are formed using polysilicon

This arrangement simplifies routing and improves compactness.

Basic Layout Principle

All complementary CMOS gates are designed using:

 Single row of n-transistors

 Single row of p-transistors

These rows are connected through:

 Common gate connections

 Diffusion sharing
 Metal interconnects

Simple Gate Layout Strategy

Most simple CMOS gates are implemented using diffusion sharing.

Diffusion Sharing

Adjacent transistors share a common diffusion region to reduce:

 Silicon area
 Parasitic capacitance
 Routing complexity

This is achieved by arranging transistors so that:

 Diffusion regions form continuous strips

 Polysilicon gates intersect diffusion regions

This approach minimizes the need for additional interconnections.

CMOS Logic Gate Graph Representation

To optimize layout, CMOS logic gates can be represented using graphs.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 26 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 24: CMOS logic gate graph representation

Graph Components

1. Vertices
o Represent diffusion nodes (source/drain)
2. Edges
o Represent MOS transistors

Two graphs are constructed:

 p-graph → represents PMOS pull-up network

 n-graph → represents NMOS pull-down network

These graphs are dual graphs of each other.

Euler Path in CMOS Layout

An Euler path is a path in a graph that traverses each edge exactly once.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 27 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 25: Euler paths in CMOS gate and the corresponding layout

Using an Euler path helps in:

 Creating continuous diffusion regions

 Reducing layout area
 Minimizing parasitic capacitances

Steps for Euler Path Layout

1. Draw the p-network graph

2. Draw the n-network graph
3. Find Euler paths for both graphs
4. Check if both paths have the same vertex ordering

If they match:

 A single continuous diffusion layout is possible.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 28 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

If they do not match:

 The gate must be split into multiple sections.

Example: CMOS Gate Graph

A CMOS gate with inputs (A, B, C, D) can be represented as:

 pMOS graph connected to VDD

 nMOS graph connected to VSS

Both graphs share the same input ordering if Euler path exists.

This allows:

 Minimum layout area

 Reduced metal routing

Euler Path Layout Procedure

Typical layout procedure:

1. Identify Euler path

2. Arrange transistors according to input sequence
3. Place pMOS row near VDD
4. Place nMOS row near VSS
5. Use vertical polysilicon lines for gate inputs
6. Use metal lines for interconnection

Automated Layout Generation

Automated layout generation typically follows these steps:

Step 1: Route power and ground

 VDD at the top

 VSS at the bottom

Step 2: Place transistors

Transistors are placed in horizontal rows.

Step 3: Group transistors

Transistors connected to the same nodes are grouped.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 29 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Step 4: Route signals

Signals are routed using:

 Vertical diffusion
 Metal interconnects

This automation significantly speeds up VLSI physical design.

Fig. 4. 26: Outline of automated approach to CMOS gate layout

Advantages of Euler Path Based Layout

Table 4. 3: Advantages of Euler Path Based Layout

Feature Benefit
Diffusion sharing Smaller area
Reduced capacitance Higher speed
Less metal routing Simpler layout
Continuous diffusion Better performance

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 30 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Limitations

Euler path layout may not always be possible when:

 Graphs have different vertex ordering

 Networks are too complex
 Multiple transistor stacks exist

In such cases:

 The gate must be split into multiple diffusion regions.

Input–Output (I/O) Structures

In CMOS integrated circuits, Input–Output (I/O) structures connect the internal chip circuitry
to the external environment.

They must handle:

 Higher voltages and currents than internal circuits

 External noise and electrostatic discharge (ESD)
 Interface compatibility with other logic families

Unlike internal CMOS circuits, I/O circuits require careful design due to process and
reliability constraints.

Overall Organization of I/O Pads

I/O pads are typically placed around the chip boundary forming a pad frame or pad ring.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 31 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 27: General pad layouts

Typical characteristics:

 Pads have fixed positions on the chip edge.

 Pad size is typically around 150 µm × 150 µm.
 Power and ground buses run around the chip periphery.

Pads must provide:

 Mechanical support for bonding wires

 Electrical connection to package pins

Typical I/O Pad Arrangement

Example pad organization:

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 32 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Table 4. 4: Example pad organization

Chip Side Pads

Left Input signals
Top Power (VDD)
Right Output signals
Bottom Ground (VSS)

This arrangement simplifies:

 Power distribution
 Signal routing
 Package connections

The pad frame normally includes:

 Input pads
 Output pads
 Bidirectional pads
 Power pads (VDD)
 Ground pads (VSS)

Pad frames may be auto-generated from text descriptions. Example:

LEFT;

INPUT A
INPUT B

TOP;

VDD VDD
INPUT C

RIGHT;

OUTPUT Z
OUTPUT Y

BOTTOM;

OUTPUT W
VSS VSS

The resulting I/O frame is shown in figure below.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 33 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 28: I/O frame generation

VDD and VSS Pads

Power supply pads connect the external power supply to the internal circuitry.

Features

 Consist mainly of large metal contacts.

 Designed to handle high current flow.
 Often implemented using wide metal lines.

In many processes:

 The connection between pad and internal metal lines may be completed using polysilicon
or multi-level metal routing.

These pads ensure stable supply distribution throughout the chip.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 34 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 29: VDD pad design

Output Pads

Output pads must be capable of driving large capacitive loads.

Key requirements:

 high current drive capability

 fast switching
 compatibility with external logic families

For example:

 TTL loads require the output to sink around 16 mA in the LOW state.
 CMOS outputs operate with a 5 V supply and provide sufficient drive strength.

To achieve this:

 Output transistors are made larger than internal logic transistors.

Input Pads

Input pads must be designed to protect the internal circuitry.

Main Issues

1. Gate oxide breakdown

The thin oxide of MOS gates can break down if excessive voltage appears at the input.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 35 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Typical breakdown voltage:

30 – 40 V

Gate Voltage Relationship

The voltage buildup across the gate is given by:

where

 V = gate voltage
 I = charging current
 = time duration
 = gate capacitance

Even small currents can cause dangerous voltages due to the very small gate capacitance.

Electrostatic Discharge (ESD) Protection

To prevent damage from static charge, protection circuits are added.

Fig. 4. 30: Typical input protection circuit

Typical protection includes:

 Diodes connected to VDD and VSS

 Series resistors
 Guard rings

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 36 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Protection Components

1. Series resistor
2. Clamp diodes
3. Guard rings

Operation

 If voltage exceeds normal range

 Diodes conduct and divert current to VDD or VSS

This prevents damage to internal MOS gates.

Electrostatic discharge can generate thousands of volts.

Protection circuits use:

 Clamp diodes
 Guard rings
 Series resistors

These elements safely dissipate ESD energy.

Typical Input Protection Circuit

The protection diodes clamp the input voltage to safe levels.

Tri-State Pads

Tri-state pads allow three possible output states:

1. Logic 1
2. Logic 0
3. High Impedance (Hi-Z)

Truth Table

Table 4. 5: Truth Table

Control Input Output

0 X High impedance
1 0 0
1 1 1

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 37 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 31: Tri-state Pad

Applications

Tri-state pads are used in:

 Data buses
 Memory systems
 Microprocessors

High impedance allows multiple devices to share a common bus line.

Advantages

 supports bus architectures

 prevents bus contention
 enables multiplexed communication

Bidirectional Pads

Bidirectional pads allow the same pin to function as both:

 Input
 Output

They combine:

 Input buffer
 Output driver
 Tri-state control

This allows a single pin to perform both operations.

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 38 of 39
HKBK College of Engineering VLSI Design and Testing (BEC602)

Fig. 4. 32: Bi-directional Pad

They are widely used in:

 Data buses
 Microprocessors
 Memory interfaces

Structure

A bidirectional pad typically combines:

 An input buffer
 A tri-state output driver

Operation:

 When output driver is disabled → pad behaves as input

 When driver is enabled → pad behaves as output

Summary of I/O Structures

Table 4. 6: Summary of I/O Structures

Structure Function
VDD pad Supplies power to the chip
VSS pad Ground connection
Input pad Receives external signals
Output pad Drives external loads
Tri-state pad Provides high impedance state
Bidirectional pad Supports both input and output

Prepared by: Dr. Hashinur Islam, Asst. Prof., Dept. of ECE Page 39 of 39