UNIT-2

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 UNIT 2 Syllabus
• Overview of memory interfacing and I/O interfacing
• Parallel communication interface {8255 PPI}
• Serial communication interface {8251 USART}
• Timer {or counter} – {8253/8254 Timer}
• Keyboard /display controller {8279}
• Interrupt controller {8259}
• DMA controller {8237/8257}

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 Data Transfers
• Synchronous ----- Usually occur when
peripherals are located within the same
computer as the CPU. Close proximity
allows all state bits change at same time
on a common clock.
• Asynchronous ----- Do not require that
the source and destination use the same
system clock.

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Memory & I/O Interfacing

MEMORY DEVICES I/O DEVICES

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Several memory chips or I/O devices can
connected to a microprocessor. An address
decoding circuit is used to select the
required I/O device or a memory chip.

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 Memory Interfacing

• When we are executing any instruction, we need

the microprocessor to access the memory for
reading instruction codes and the data stored in
the memory.
• For this, both the memory and the
microprocessor requires some signals to read
from and write to registers.
• The interfacing circuit therefore should be
designed in such a way that it matches the
memory signal requirements with the signals of
the microprocessor.
 I/O Interfacing
There are various communication devices like the keyboard,
mouse, printer, etc. So, we need to interface the keyboard and
other devices with the microprocessor by using latches and
buffers. This type of interfacing is known as I/O interfacing.

In memory interfacing:8 bit data line, 16 bit address line ,

control signals are connected to corresponding lines of
memory IC.
In I/O device interfacing:8 bit data line, only 8 bit address line ,
control signals are connected to corresponding lines of I/O
devices.
 I/O mapped I/O V/s Memory Mapped I/O

Memory Mapped I/O I/O Mapped I/O

• I/O is treated as memory. • I/O is treated I/O.
• 16-bit addressing. • 8- bit addressing.
• More Decoder Hardware. • Less Decoder Hardware.
• Can address 216=64k • Can address 28=256
locations. locations.
• Less memory is available. • Whole memory address
space is available.

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 Memory Mapped I/O I/O Mapped I/O

• Memory Instructions are • Special Instructions are

used. used like IN, OUT.
• Memory control signals • Special control signals
are used. are used.
• Arithmetic and logic • Arithmetic and logic
operations can be operations cannot be
performed on data. performed on data.
• Data transfer b/w register • Data transfer b/w
and I/O. accumulator and I/O.

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Parallel communication
interface
INTEL 8255

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 8255 PPI
• The 8255 chip is also called as Programmable
Peripheral Interface.
• The Intel’s 8255 is designed for use with Intel’s 8-
bit, 16-bit and higher capability microprocessors
• The 8255 is a 40 pin IC, designed to perform a
variety of interface functions in a computer
environment.
• It is flexible and economical.

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PIN DIAGRAM OF 8255

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Signals of 8255

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 8255 PPI
• It has 24 input/output lines which may be
individually programmed.
• 2 groups of I/O pins are named as
Group A (Port-A & Port C Upper)
Group B (Port-B & Port C Lower)
• 3 ports(each port has 8 bit)
Port A lines are identified by symbols PA0-PA7
Port B lines are identified by symbols PB0-PB7
Port C lines are identified by PC0-PC7 , PC3-PC0
ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)

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D0 - D7: data input/output lines for the device.
All information read from and written to the
8255 occurs via these 8 data lines.

CS (Chip Select). If this line is a logical 0, the

microprocessor can read and write to the
8255.

RESET : The 8255 is placed into its reset state if

this input line is a logical 1

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• RD : This is the input line driven by the
microprocessor and should be low to
indicate read operation to 8255.
• WR : This is an input line driven by the
microprocessor. A low on this line
indicates write operation.
• A1-A0 : These are the address input lines
and are driven by the microprocessor.

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 Control Logic
• CS signal is the master Chip Select
• A0 and A1 specify one of the two I/O Ports
CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is not
selected
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Block Diagram of 8255A

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 Block Diagram of 8255 (Architecture)
It has a 40 pins - 4 parts.
1. Data bus buffer
2. Read/Write control logic
3. Group A and Group B controls
4. Port A, B and C

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 1. Data bus buffer
• This is a tristate bidirectional buffer used
to interface the 8255 to system data bus.
• Data is transmitted or received by the
buffer on execution of input or output
instruction by the CPU.

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 2. Read/Write control logic
• This unit accepts control signals ( RD, WR ) and
also inputs from address bus and issues
commands to individual group of control blocks
( Group A, Group B).
• It has the following pins.

CS , RD , WR , RESET , A1 , A0

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 3. Group A and Group B controls
• This block receives control from the CPU
and issues commands to their respective
ports.
Group A - PA and PCU ( PC7 –PC4)
Group B – PB and PCL ( PC3 –PC0)

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a) Port A: This has an 8 bit latched/buffered
O/P and 8 bit input latch. It can be
programmed in 3 modes – mode 0, mode
1, mode 2.
b) Port B: It can be programmed in mode 0,
mode1
c) Port C : It can be programmed in mode 0

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CONTROL WORD REGISTER(CWR)

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Modes of Operation of 8255
 Bit Set/Reset(BSR) Mode
 Set/Reset bits in Port C
 I/O Mode
 Mode 0 (Simple input/output)
 Mode 1 (Handshake mode)
 Mode 2 (Bidirectional Data Transfer)

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1. BSR Mode

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 Bit/pin of port C
B3 B2 B1
selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

Concerned only with the 8-bits of Port C.

Set or Reset by control word
Ports A and B are not affected 28
 2. I/O MODE
a) Mode 0 (Simple Input or Output):

• Ports A and B are used as Simple I/O

Ports
• Port C as two 4-bit ports
•Features
–Outputs are latched
–Inputs are not latched
–Ports do not have handshake or
interrupt capability
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30
b) Mode 1: (Input or Output with Handshake)

• Handshake signals are exchanged

between MPU & Peripherals
•Features
–Ports A and B are used as Simple I/O Ports
–Each port uses 3 lines from Port C as
handshake signals
–Input & Output data are latched
–Interrupt logic supported
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b) Mode 1: (Input or Output with Handshake)
• Input Handshaking signals
1. IBF (Input Buffer Full) - It is an output indicating that the input latch contains
information.
2. STB (Strobed Input) - The strobe input loads data into the port latch, which holds the
information until it is input to the microprocessor via the IN instruction.
3. INTR (Interrupt request) - It is an output that requests an interrupt. The INTR pin
becomes logic 1 when the STB input returns to a logic 1, and is cleared when the data
are input from the port by the microprocessor.
4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
programmed via the port PC4 (port A) or PC2 (port B) bit position.
• Output Handshaking signals
1. OBF (Output Buffer Full) - It is an output that goes low whenever data are
output(OUT) to the port A or port B latch. This signal is set to logic 1 whenever the
ACK pulse returns from the external device.
2. ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK signal is
a response from an external device, indicating that it has received the data from the
82C55A port.
3. INTR (Interrupt request) - It is a signal that often interrupts the microprocessor when
the external device receives the data via the signa, this pin is qualified by the internal
INTE(interrupt enable) bit.
4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
programmed to enable or disable the INTR pin. The INTE A bit is programmed using
the PC6 bit and INTE B is programmed using the PC2 bit. 32
c) Mode 2: Bidirectional Data Transfer

• Used primarily in applications such as data

transfer between two computers
• Features
– Ports A can be configured as the bidirectional Port
– Port B in Mode 0 or Mode 1.
– Port A uses 5 Signals from Port C as handshake
signals for data transfer
– Remaining 3 Signals from Port C Used as – Simple
I/O or handshake for Port B

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 Example 1
• Consider 8255 programmable peripheral interface is used for the following
situations
• (i) An A/D converter is interfaced to a microprocessor through an 8255. The
conversion is initiated by a signal from the 8255 on Port C. A signal on Port
C causes data to be strobed into Port A.
Ans Mode 1

• (ii) Two computers exchange data using a pair of 8255s. Port A works as a
bidirectional data port supported by appropriate handshaking signals.
Ans Mode 2

Find the appropriate modes of operation of the 8255 for I and II.
 Example 2
Find control word
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input

Solution:

1 0 1 0 1 1 1 0 = AEH

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 Example 3
Find the control word for the register arrangement
of the ports of Intel 8255 for mode 0 operation.
Port A: Output, Port B: Output,
Port CU: Output, Port CL: Output

Solution:

1 0 0 0 0 0 0 0 = 80H

The control word register for the above ports of Intel 8255 is
80H.
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 Example 4
Find the control word for the register arrangement
of the ports of Intel 8255 for mode 0 operation.
Port A: Input, Port B: Input,
Port CU: Input, Port CL: Input

Solution:

1 0 0 1 1 0 1 1 = 9BH
The control word register for the above ports of intel
8255 is 9BH.
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 Basics of serial communication
1. Transmitter:
- A parallel-in, serial-out
shift register

2. Receiver:
- A serial-in, parallel-out
Parallel Transfer
shift register.

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TRANSMITTER

Receiver

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Serial communication
interface
INTEL 8251 USART

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 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
• Programmable chip designed for synchronous
and asynchronous serial data transmission
• 28 pin DIP
• Converts parallel data into a serial stream of
bits suitable for serial transmission.
• Receives a serial stream of bits and convert it
into parallel data bytes to be read by a
microprocessor.
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42
BLOCK DIAGRAM

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 Five Sections
– Read/Write Control Logic
• Interfaces the chip with MPU
• Determine the functions according to the control word
• Monitors data flow
– Transmitter
• Converts parallel word received from MPU into serial bits
• Transmits serial bits over TXD line to a peripheral.
– Receiver
• Receives serial bits from peripheral
• Converts serial bits into parallel word
• Transfers the parallel word to the MPU
– Data Bus Buffer- 8 bit Bidirectional bus.
– Modem Controller
• Used to establish data communication modems over
telephone line
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 Input Signals
• CS – Chip Select
When this signal goes low, 8251 is selected by
MPU for communication
• C/D – Control/Data
– When this signal is high, the control register
or status register is addressed
– When it is low, the data buffer is addressed
– Control and Status register is differentiated by
WR and RD signals, respectively

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• WR – Write
– Writes in the control register or sends outputs to the
data buffer.
– This is connected to I/O Write or Memory Write
• RD – Read
– Either reads a status from status register or accepts
data from the data buffer
– This is connected to either I/O Read or Memory Read
• RESET - Reset
• CLK - Clock
– Connected to system clock
– Necessary for communication with microprocessor.
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CS C/D RD WR Function
0 1 1 0 MPU writes instruction in the
control register
0 1 0 1 MPU reads status from the status
register
0 0 1 0 MPU outputs the data to the Data
Buffer
0 0 0 1 MPU accepts data from the Data
Buffer
1 X X X USART is not Selected

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• Control Register
– 16-bit register
– This register can be accessed an output port
when the C/D pin is high
• Status Register
– Checks the ready status of a peripheral
• Data Buffer

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 Transmitter Section
• Accepts parallel data and converts it into serial
data
• Two registers
– Buffer Register
To hold eight bits
– Output Register
Converts eight bits into a stream of serial bits
– Transmits data on TxD pin with appropriate
framing bits(Start and Stop)

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 Signals Associated with Transmitter
Section
• TxD – Transmit Data
– Serial bits are transmitted on this line
• TxC – Transmitter Clock
– Controls the rate at which bits are transmitted
• TxRDY – Transmitter Ready
– Can be used either to interrupt the MPU or
indicate the status
• TxE – Transmitter Empty
– Logic 1 on this line indicate that the output
register is empty

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 Receiver Section

• Accepts serial data from peripheral and

converts it into parallel data
• The section has two registers
– Input Register
– Buffer Register

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 Signals Associated with Receiver
Section
• RxD – Receive Data
– Bits are received serially on this line and
converted into parallel byte in the receiver input
• RxC – Receiver Clock
• RxRDY – Receiver Ready
– It goes high when the USART has a character in
the buffer register and is ready to transfer it to the
MPU

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 Signals Associated with Modem
Control
• DSR- Data Set Ready
– Normally used to check if the Data Set is ready when
communicating with a modem (terminal)
• DTR – Data Terminal Ready
– Device is ready to accept data when the 8251 is
communicating with a modem.(modem)
• RTS – Request to send Data
– The receiver is ready to receive a data byte from modem.
(terminal)
• CTS – Clear to Send
--- This is an input terminal for MODEM interface which is
used for controlling a transmit circuit.(modem)

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 SYNDET/BD pin

• This is pin 16 of 8251 and stands for sync. detect (SYNDET)/Break Detect
(BRKDET).
• This pin is used for detection of SYNC characters in synchronous mode and
Break characters in asynchronous mode.
• Synchronous mode: In the synchronous case this pin (SYNDET) can be
used as either input or output pin with the help of control word. When the
system is RESET, the status of this pin is low in the output mode.
• BRKDET: In this mode, this pin acts as an output pin to detect break
characters. If RXD remains low for two consecutive stop bit sequences, this
pin (BRKDET) goes high.

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 Programming 8251
8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Parity enable
Stop bits
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length
11: x64 clock
11: 2 bits 00: 5 bits
01: 6 bits
Parity
10: 7 bits
0: odd
11: 8 bits
1: even
11-55
 Programming 8251

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enable

DTR: data terminal ready, DTR pin will be low
RxE: receiver enable
SBPRK: send break character, TxD pin will be low
ER: error reset
RTS: request to send, CTS pin will be low
IR: internal reset
EH: enter hunt mode (1=enable search for SYN character)
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 Programming 8251

8251 status register

status
DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY
register

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready 11-57
TIMER/COUNTER
INTEL 8253/8254

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Pin diagram

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• RD: read signal
• WR: write signal
• CS: chip select signal
• A0, A1: address lines
• Clock :This is the clock input for the counter. The
counter is 16 bits.
• Out :This single output line is the signal that is
the final programmed output of the device.
• Gate :This input can act as a gate for the clock
input line, or it can act as a start pulse

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61
Control Word Register :This internal register is used to write information
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8254 Programming

11-63
 Mode 0 Interrupt on Terminal Count

• It is used to generate an interrupt to the microprocessor after a certain

interval.
• Initially the output is low after the mode is set. The output remains LOW after
the count value is loaded into the counter.
• The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero and the output goes HIGH and will
remain high until it reloads a new count.
• The GATE signal is high for normal counting. When GATE goes low, counting is
terminated and the current count is latched till the GATE goes high again.
 Mode 1 Programmable One Shot

• It can be used as a mono stable multi-vibrator.

• The gate input is used as a trigger input in this
mode.
• The output remains high until the count is
loaded and a trigger is applied.
 8254 Modes
Gate is low the
count will be Mode 0: An events counter enabled with G.
paused
N 1 2 2 2 3 4 5

CLK
Gate is high
OUT
Will continue
counting
GATE
count of 5 load
Mode 1: One-shot mode Counter will be reloaded
After gate high.
1 2 3 4 5

CLK Gate is
High output
GATE will be high

OUT trigger with count of 5 66

 Mode 2 Rate Generator

• The output is normally high after initialization.

• Whenever the count becomes zero, another
low pulse is generated at the output and the
counter will be reloaded.
 Mode 3 Square Wave Generator

• This mode is similar to Mode 2 except the

output remains low for half of the timer
period and high for the other half of the
period.
Mode 2: Counter generates a series of pulses 1 clock
pulse wide

1 2 3 4 5 1 2 3 4 5 1

CLK

OUT cycle is repeated until

count of 5 loaded reprogrammed or G pin
set to 0

Mode 3: Generates a continuous square-wave with G set to 1

1 2 3 4 1 2 3 4

CLK

OUT
If count is even, 50% duty cycle
count of 6 loaded otherwise OUT is high 1 cycle longer 69
 Mode 4 Software Triggered Mode

• In this mode, the output will remain high until

the timer has counted to zero, at which point
the output will pulse low and then go high
again.
• The count is latched when the GATE signal
goes LOW.
• On the terminal count, the output goes low
for one clock cycle then goes HIGH. This low
pulse can be used as a strobe.
 Mode 5 Hardware Triggered Mode

• This mode generates a strobe in response to

an externally generated signal.
• This mode is similar to mode 4 except that the
counting is initiated by a signal at the gate
input, which means it is hardware triggered
instead of software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the
output goes low for one clock cycle.
 Mode 4: Software triggered one-shot.

1 2 3 4 5 6 7 8

CLK

OUT
Trigger with count of 8 In the last counting
Will be stop
(not repeated)

Mode 5: Hardware triggered one-shot. G controls similar to Mode 1.

In the last count
1 2 3 4 5 Out will be low

CLK

GATE

OUT trigger with count of 5

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Keyboard/Display
Controller
INTEL 8279

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 Introduction
INTEL 8279 is specially developed for
interfacing keyboard and display devices to
8085/8086 microprocessor based system

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 Features of 8279
• Simultaneous keyboard and display operations
• Scanned keyboard mode
• Scanned sensor mode
• 8-character keyboard FIFO
• 16-character display

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Pin Diagram

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 4 sections
• Keyboard section
• Display section
• Scan section
• CPU interface section

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78
79
 Keyboard section

• The keyboard section consists of 8 return lines

RL0 - RL7 that can be used to form the rows of
a keyboard matrix.
• It has two additional input : shift and
control/strobe. The keys are automatically
debounced.
• The two operating modes of keyboard section
are 2-key lockout and N-key rollover.

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• In the 2-key lockout mode, if two keys are
pressed simultaneously, only the first key is
recognized.
• In the N-key rollover mode simultaneous keys are
recognized and their codes are stored in FIFO.
• The keyboard section also have an 8 x 8 FIFO
(First In First Out) RAM.
• The FIFO can store eight key codes in the scan
keyboard mode. The status of the shift key and
control key are also stored along with key code.
The 8279 generate an interrupt signal (IRQ)when
there is an entry in FIFO.
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 Display section
• The display section has eight output lines
divided into two groups A0-A3 and B0-B3.
• The output lines can be used either as a single
group of eight lines or as two groups of four
lines, in conjunction with the scan lines for a
multiplexed display.
• The output lines are connected to the anodes
through driver transistor in case of common
cathode 7-segment LEDs.

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• The cathodes are connected to scan lines
through driver transistors.

• The display can be blanked by BD (low) line.

• The display section consists of 16 x 8 display

RAM. The CPU can read from or write into any
location of the display RAM.

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 Scan section
• The scan section has a scan counter and four scan
lines, SL0 to SL3.
• In decoded scan mode, the output of scan lines will
be similar to a 2-to-4 decoder.
• In encoded scan mode, the output of scan lines will
be binary count, and so an external decoder should
be used to convert the binary count to decoded
output.
• The scan lines are common for keyboard and display.

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 CPU interface section
• The CPU interface section takes care of data
transfer between 8279 and the processor.
• This section has eight bidirectional data lines
DB0 to DB7 for data transfer between 8279
and CPU.
• It requires two internal address: A =0 for
selecting data buffer and A = 1 for selecting
control register of8279.

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• The control signals WR (low), RD (low), CS
(low) and A0 are used for read/write to 8279.
• It has an interrupt request line IRQ, for
interrupt driven data transfer with processor.
• The 8279 require an internal clock frequency
of 100 kHz. This can be obtained by dividing
the input clock by an internal prescaler.

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 Operational Modes of 8279
There are two modes of operation on 8279 − Input Mode and Output Mode.
Input Mode
This mode deals with the input given by the keyboard and this mode is further classified
into 3 modes.
•Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using
either encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the
decoded scan, a 4×8 keyboard can be interfaced. The code of key pressed with SHIFT
and CONTROL status is stored into the FIFO RAM.
•Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the
processor using either encoder or decoder scans. In the encoder scan, 8×8 sensor
matrix or with decoder scan 4×8 sensor matrix can be interfaced.
•Strobed Input − In this mode, when the control line is set to 0, the data on the return
lines is stored in the FIFO byte by byte.
Output Mode
This mode deals with display-related operations. This mode is further classified into two
output modes.
•Display Scan − This mode allows 8/16 character multiplexed displays to be organized
as dual 4-bit/single 8-bit display units.
•Display Entry − This mode allows the data to be entered for display either from the
right side/left side.
 When a Key is Pressed
(what happens?)

• Scan Counter scans rows.

• Return line detects pressed key.
• Debounce confirms valid press.
• Data stored in FIFO.
• CPU reads from FIFO via Data Buffer.
 When Display is updated
(what happens?)

• CPU writes data into Display RAM.

• Timing unit scans display positions.
• Data sent to output pins.
• Display glows.
All the command words or status words are written or read with A0 = 1 and
CS = 0 to or from 8279.
a) Keyboard Display Mode Set : The format of the command word to select different
modes of operation of 8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K

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SENSOR MATRIX

SENSOR MATRIX

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B) Programmable clock :

➢The clock for operation of 8279 is obtained by dividing

the external clock input signal by a programmable
constant called prescaler.
➢ PPPPP is a 5-bit binary constant.
➢The input frequency is divided by a decimal constant
ranging from 2 to 31, decided by the bits of an internal
prescaler, PPPPP.
D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 P P P P P

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c)Read FIFO / Sensor RAM : The format of this command is given
below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A

AI – Auto Increment Flag

AAA – Address pointer to 8 bit FIFO RAM
X- Don’t care
✓This word is written to set up 8279 for reading FIFO/ sensor RAM.
✓In scanned keyboard mode, AI and AAA bits are of no use. The 8279
will automatically drive data bus for each subsequent read, in the same
sequence, in which the data was entered.
✓In sensor matrix mode, the bits AAA select one of the 8 rows of RAM.
✓If AI flag is set, each successive read will be from the subsequent
RAM location.

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d) Read Display RAM :
This command enables a programmer to read the display RAM data.

D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A

❖The CPU writes this command word to 8279 to prepare it for

display RAM read operation.
❖AI is auto increment flag and AAAA, the 4-bit address points to
the 16-byte display RAM that is to be read.
❖If AI=1, the address will be automatically, incremented after each
read or write to the Display RAM.
❖The same address counter is used for reading and writing.

96
d) Write Display RAM :
This command enables a programmer to write the display RAM data.

D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A

AI – Auto increment Flag.

AAAA – 4 bit address for 16-bit display RAM to be written.

e) Display Write Inhibit/Blanking :

D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 X IW IW BL BL

IW - inhibit write flag

BL - blank display bit flags
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g) Clear Display RAM :

D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 CD2 CD1 CD0 CF CA

CD2 CD1 CD0

0X - All zeros ( x don’t care ) AB=00

ENABLES CLEAR DISPLAY
10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
WHEN CD2=1
11 - All ones (AB =FF), i.e. clear RAM
• CD2 must be 1 for enabling the clear display command.
• If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly same as
above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared and IRQ
line is pulled down and the sensor RAM pointer is set to row 0.
•If CA=1, this combines the effect of CD and CF bits. 98
h) End Interrupt / Error mode Set :
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 E X X X 1

E- Error mode
X- don’t care

➢For the sensor matrix mode, this command lowers the

IRQ line and enables further writing into the RAM.
➢Otherwise, if a change in sensor value is detected, IRQ
goes high that inhibits writing in the sensor RAM.
➢ For N-Key roll over mode, if the E bit is programmed to
be ‘1’, the 8279 operates in special Error mode

99
 Use a keyboard / display controller to interface a 64 key keyboard and an
8 digit seven segment display in right entry mode. Determine the
appropriate commands needed to be given in control word register before
the CPU sends the characters to displayed to the 8279 and inputting data
from return lines into FIFO memory byte by byte

Solution
The format of the command word to select different modes of operation of
8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
0 0 0 1 0 1 1 0 = 16

100
 INTERRUPT
CONTROLLER
INTEL 8259

101
 8259 Programmable Interrupt Controller (PIC)

1. This IC is designed to simplify the implementation of the interrupt interface in the 8088
and 8086 based microcomputer systems.
2. This device is known as a ‘Programmable Interrupt Controller’ or PIC.
3. It is manufactured using the NMOS technology and It is available in 28-pin DIP.
4. 8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
5. This controller can be expanded without additional hardware to accept up to 64
interrupt request inputs. This expansion required a master 8259A and eight 8259A
slaves.
6. Some of its programmable features are:
· The ability to accept level-triggered or edge-triggered inputs.
· The ability to be easily cascaded to expand from 8 to 64 interrupt-inputs.
· Its ability to be configured to implement a wide variety of priority schemes.
8259A PIC- PIN DIGRAM

8
2
5
9
ASSINGMENT OF SIGNALS FOR 8259:
1. D7- D0 is connected to microprocessor data bus D7-D0 (AD7-AD0).
2. IR7- IR0, Interrupt Request inputs are used to request an interrupt and to connect to a slave
in a system with multiple 8259As.
3. WR - the write input connects to write strobe signal of microprocessor.
4. RD - the read input connects to the IORC signal.
5. INT - the interrupt output connects to the INTR pin on the microprocessor from the master,
and is connected to a master IR pin on a slave.
6. INTA - the interrupt acknowledge is an input that connects to the INTA signal on the system.
In a system with a master and slaves, only the master INTA signal is connected.
7. A0 - this address input selects different command words within the 8259A.
8. CS - chip select enables the 8259A for programming and control.
9. SP/EN - Slave Program/Enable Buffer is a dual-function pin.
SP/EN
❖When the 8259A is in buffered mode, this pin is an
output that controls the data bus transceivers in a
large microprocessor-based system.
❖When the 8259A is not in buffered mode, this pin
programs the device as a master (1) or a slave (0).
CAS2-CAS0
❖ Cascade lines are used as outputs from the master to
the slaves for cascading multiple 8259As in a system.
8259A PIC- BLOCK DIAGRAM
 EXPLANATION OF BLOCKS
The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write
Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver and 3 registers-
ISR, IRR, IMR.
[Link] bus buffer –
This Block is used as a mediator between 8259 and 8086 microprocessor by
acting as a buffer. The data bus buffer consists of 8 bits represented as D0-D7 in
the block diagram. Thus, shows that a maximum of 8 bits data can be transferred
at a time.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low).
This block is responsible for the flow of data depending upon the inputs of RD
and WR. These two pins are active low pins used for read and write operations.
3. Control logic –
It is the centre of the microprocessor and controls the functioning of every block.
It has pin INTR which is connected with other microprocessor for taking interrupt
request and pin INT for giving the output. If 8259 is enabled, and the other
microprocessor Interrupt flag is high then this causes the value of the output INT
pin high and in this way 8259 responds to the request made by other
microprocessor.
 EXPLANATION OF BLOCKS
[Link] request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
[Link] service register (ISR) –
It stores the interrupt level which are currently being executed.
[Link] mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits
of the interrupt level.
[Link] resolver –
It examines all the three registers and set the priority of interrupts and according
to the priority of the interrupts, interrupt with highest priority is set in ISR
register. Also, it reset the interrupt level which is already been serviced in IRR.
[Link] buffer –
To increase the Interrupt handling capability, we can further cascade more
number of pins by using cascade buffer. So, during increment of interrupt
capability, CSA lines are used to control multiple interrupt structure.

SP/EN (Slave program/Enable buffer) pin is when set to high, works in master
mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify
whether 8259 work as master or slave and in Buffered mode, SP/EN pin is used as
an output to enable data bus.
A microprocessor accepts external interrupts (Ext INT) through a
Programmable Interrupt Controller as shown in the figure.

Assuming vectored interrupt, explain the correct sequence

of operations when a single external interrupt (Ext INT1) is
received.
 SOLUTION

STEP 4: This is vectored interrupt so, their address is fixed and

ISR (interrupt service Routine) execution will takes place from
that address..

Ext INT1 → INT → INTA → ISR (reading data from the device
connected Ext INT1
8237/8257 DMA CONTROLLER

128
 Introduction
 Direct Memory Access (DMA) is a method of allowing
data to be moved from one location to another in a
computer without intervention from the central
processor (CPU).
 It is also a fast way of transferring data within (and
sometimes between) computer.
 The DMA I/O technique provides direct access to the
memory while the microprocessor is temporarily
disabled.
 The DMA controller temporarily borrows the address
bus, data bus and control bus from the microprocessor
and transfers the data directly from the external devices
to a series of memory locations (and vice versa).

129
The 8257 DMA controller

130
How DMA Operations are Performed?
Following is the sequence of operations performed by a
DMA −
•Initially, when any device has to send data between the
device and the memory, the device has to send DMA
request (DRQ) to DMA controller.
•The DMA controller sends Hold request (HRQ) to the
CPU and waits for the CPU to assert the HLDA.
•Then the microprocessor tri-states all the data bus,
address bus, and control bus. The CPU leaves the control
over bus and acknowledges the HOLD request through
HLDA signal.
•Now the CPU is in HOLD state and the DMA controller
has to manage the operations over buses between the
CPU, memory, and I/O devices.
DRQ0−DRQ3
8257 pins
These are the four individual channel DMA request inputs, which are used by the peripheral devices for using
DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3 has the
lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of
their request by the CPU. These lines can also act as strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data bus of DMA
controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In the master
mode, these lines are used to send higher byte of the generated address to the latch. This address is further
latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of 8257 in
the Slave mode. In the master mode, it is used to read data from the peripheral devices during a memory write
cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit mode
register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it is
used to load the data to the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3
These are the four least significant address lines. In the slave mode, they act as an input, which selects one of the
registers to be read or written. In the master mode, they are the four least significant memory address output
lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In the
master mode, it disables the read/write operations to/from 8257.
A4 - A7
132
These are the higher nibble of the lower byte address generated by DMA in the master mode.
READY
8257 pins
It is an active-high asynchronous input signal, which makes DMA ready by inserting
wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with
HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit. 133
8257 block diagram

134
 Features of 8257
Here is a list of some of the prominent features of 8257 −
•It has four channels which can be used over four I/O devices.
•Each channel has 16-bit address and 14-bit counter.

•Each channel can transfer data up to 64kb.

•Each channel can be programmed independently.
•Each channel can perform read transfer, write transfer and verify
transfer operations.
•It generates MARK signal to the peripheral device that 128 bytes
have been transferred.
•It operates in 2 modes, i.e., Master mode and Slave mode.
 Block Diagram Description
1. Data bus buffer
2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.

136
DATA BUS BUFFER:
• It contains tristate, 8 bit bi-directional buffer.
• Slave mode, it transfers data between
microprocessor and internal data bus.
• Master mode, outputs A8-A15 bits of memory
address on data lines (Unidirectional).
READ/CONTROL LOGIC:
• It controls all internal Read/Write operation.
• Slave mode, it accepts address bits and control
signal from microprocessor.
• Master mode, it generate address bits and
control signal.
137
Control logic block
1. Control logic
2. Mode set register and
3. Status Register.

CONTROL LOGIC:
• Master mode - It controls the sequence of DMA
operation during all DMA cycles.
• It generates address and control signals.
• It increments 16 bit address and decrement 14 bit
counter registers.
• It activate a HRQ signal on DMA channel Request.
• Slave mode - it is disabled.
138
 SLAVE MODE
In this mode the DMA controller is treated as a
peripheral and performs the following steps:
• The microprocessor selects the DMA
controller chip through CS
• Microprocessor initializes the DMAC by giving
the starting address to the 16 bit address
register and number of bytes to be transferred
to the 14 bit count register with the help of
control signals IOR and IOW.
 MASTER MODE
After initialization the 8257 enters in master mode and continuously checking
the DMA request from the peripheral and perform the following steps:
• When the I/O device is ready for data transfer, it sends a DMA
request signal to the DMAC through DREQ line.
• The DMA in turn sends a request signal to the µP through the HOLD
line.
• The µP finishes the current machine cycle and releases the system
bus (disconnected from it) and acknowledge the I/O device by
sending a signal through HLDA line.
• After receiving the HLDA signal the DMA controller acknowledge the
I/O device by sending a low signal on DACQ.
• In the mean time the 8257 make use of AEN and ADSTB signals to
take control over buses. After that the DMA transfer begins.
• After every byte is transferred, the address register is incremented
and the count register decremented.
• This continues till the count reaches zero (Terminal Count=1). Now
the DMA transfer is completed.
• At the end of the transfer, the system bus is released by the DMAC by
making the HOLD=0. Then µP takes control over the system buses and
continues its operation
 The DMA controller transfers data
in three modes
[Link] Mode: Here, once the DMA controller gains the charge of the
system bus, then it releases the system bus only after completion of data
transfer. Till then the CPU has to wait for the system buses.

[Link] Stealing Mode: In this mode, the DMA controller forces the CPU to
stop its operation and relinquish the control over the bus for a short term to
DMA controller. After the transfer of every byte, the DMA
controller releases the bus and then again requests for the system bus. In
this way, the DMA controller steals the clock cycle for transferring every
byte.

[Link] Mode: Here, the DMA controller takes the charge of system
bus only if the processor does not require the system bus.
 Problem
Consider a computer system with DMA support. The DMA
module is transferring one 8-bit character in one CPU cycle from
a device to memory through cycle stealing at regular intervals.
Consider a 2 MHz processor. If 0.5% processor cycles are used for
DMA, calculate the data transfer rate of the device in bits per
second.

Solution
• To complete one cycle at 2 MHz it will take 1/ (2×10^6) seconds. So
the total number of CPU cycles in one second will be 2×10^6.

Now 0.5% of these cycles are taken by DMA to transfer the data.

So total number of cycles taken to transfer the data will

be 0.5/100×2×10^6=10,000 and in each cycle 8 bits are transferred.

So, data transfer rate in bits per second =8×10000=80,000